8 #include "usbfifo_api.h"
14 #define CMD_GET_CUSTOM_DATA 4
15 LOCAL void flash_read(uint16_t len, uint16_t ofset);
17 SetupPacket ControlCmd;
18 USB_FIFO_CONFIG usbFifoConf;
19 uint32_t fwCheckSum = 0;
22 uint16_t UsbStatus[3];
24 /* Variable for USB EP0 pipe (USB.c) */
25 uint16_t *pu8DescriptorEX;
26 uint16_t u16TxRxCounter;
27 uint16_t *u8ConfigDescriptorEX;
28 //extern BOOLEAN bUsbEP0HaltSt;
29 Action eUsbCxFinishAction;
30 CommandType eUsbCxCommand;
31 BOOLEAN UsbChirpFinish;
33 uint16_t u8UsbConfigValue;
34 uint16_t u8UsbInterfaceValue;
35 uint16_t u8UsbInterfaceAlternateSetting;
36 uint16_t u16FirmwareComplete;
38 extern uint16_t *UsbDeviceDescriptor;
39 extern uint16_t *String00Descriptor;
40 extern uint16_t *String10Descriptor;
41 extern uint16_t *String20Descriptor;
42 extern uint16_t *String30Descriptor;
44 /////////////////////////////////////////////////
45 // should be declared as extern array not pointer
46 extern uint16_t u8DeviceQualifierDescriptorEX[];
47 extern uint16_t u8OtherSpeedConfigDescriptorEX[];
49 uint16_t *u8UsbDeviceDescriptor;
50 uint16_t *u8String00Descriptor;
51 uint16_t *u8String10Descriptor;
52 uint16_t *u8String20Descriptor;
53 uint16_t *u8String30Descriptor;
56 #if 0 // use macro instead of function
57 void mUsbEPinRsTgSet(uint8_t u8ep)
59 //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1));
61 USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
62 (USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))|BIT4));
66 void mUsbEPinRsTgClr(uint8_t u8ep)
68 //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1));
70 USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
71 (USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))&(~BIT4)));
74 void mUsbEPoutRsTgSet(uint8_t u8ep)
76 //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1));
78 USB_BYTE_REG_WRITE((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
79 (USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))|BIT4));
82 void mUsbEPoutRsTgClr(uint8_t u8ep)
84 //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1));
86 USB_BYTE_REG_WRITE((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
87 (USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))&(~BIT4)));
90 void mUsbEPinStallSet(uint8_t u8ep)
92 //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1));
94 USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
95 USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))|BIT3);
98 void mUsbEPinStallClr(uint8_t u8ep)
100 //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1));
103 USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
104 (USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))&(~BIT3)));
107 void mUsbEPoutStallSet(uint8_t u8ep)
109 //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1));
111 USB_BYTE_REG_WRITE((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
112 (USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))|BIT3));
115 void mUsbEPoutStallClr(uint8_t u8ep)
117 //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1));
119 USB_BYTE_REG_WRITE((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
120 (USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))&(~BIT3)));
123 uint8_t mUsbEPinStallST(uint8_t u8ep)
125 //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1));
126 //return ((*reg & BIT3) >> 3);
127 return ((USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))& BIT3) >> 3);
130 uint8_t mUsbEPoutStallST(uint8_t u8ep)
132 //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1));
133 //return ((*reg & BIT3) >> 3);
134 return ((USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))& BIT3) >> 3);
137 uint8_t mUsbEPMapRd(uint8_t EPn)
139 //uint8_t *reg = (uint8_t*) (ZM_FUSB_BASE+0x30+(EPn-1));
141 return (USB_BYTE_REG_READ((0x30+(EPn-1))));
144 uint8_t mUsbFIFOCfgRd(uint8_t FIFOn)
146 //uint8_t *reg = (uint8_t*) (ZM_FUSB_BASE+0x90+FIFOn);
148 return (USB_BYTE_REG_READ((0x90+FIFOn)));
151 void vUsb_Data_Out0Byte(void)
153 //ZM_INTR_SOURCE_7_REG &= ~BIT7;
154 USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_REG, \
155 (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_REG&(~BIT7))));
159 void vUsb_Data_In0Byte(void)
161 //ZM_INTR_SOURCE_7_REG &= ~BIT6;
163 USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_REG, \
164 (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_REG&(~BIT6))));
168 /***********************************************************************/
171 // 1. End this transfer.
174 /***********************************************************************/
175 void vUsb_ep0end(void)
177 eUsbCxCommand = CMD_VOID;
178 //ZM_CX_CONFIG_STATUS_REG = 0x01;
179 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01);
180 //mUsbEP0DoneSet(); // Return EP0_Done flag
183 /***********************************************************************/
186 // 1. Stall this transfer.
189 /***********************************************************************/
190 void vUsb_ep0fail(void)
192 //ZM_CX_CONFIG_STATUS_REG = 0x04;
193 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04);
194 //mUsbEP0StallSet(); // Return EP0_Stall
198 /***********************************************************************/
201 // 1. Change descriptor table (High or Full speed).
204 /***********************************************************************/
207 // zfUartSendStr((uint8_t *) "vUsb_rst\r\n");
208 //ZM_INTR_SOURCE_7_REG &= ~0x02;
209 USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \
210 (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&(~BIT1)));
211 UsbChirpFinish = FALSE;
214 /***********************************************************************/
220 /***********************************************************************/
221 void vUsb_suspend(void)
223 // uP must do-over everything it should handle
224 // and do before into the suspend mode
225 //mUsbIntSuspClr(); // Go Suspend status
226 //ZM_INTR_SOURCE_7_REG &= ~0x04;
227 USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \
228 (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&(~BIT2)));
231 /***********************************************************************/
234 // 1. Change descriptor table (High or Full speed).
237 /***********************************************************************/
240 // uP must do-over everything it should handle
241 // and do before into the suspend mode
243 // mUsbIntResmClr(); // uP must wakeup immediately
244 //ZM_INTR_SOURCE_7_REG &= ~0x08;
245 USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \
246 (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&(~BIT3)));
251 #define mUsbEPinRsTgSet(u8ep) USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
252 USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))|BIT4)
254 #define mUsbEPinRsTgClr(u8ep) USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
255 USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))&~BIT4)
257 #define mUsbEPoutRsTgSet(u8ep) USB_BYTE_REG_WRITE((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
258 USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))|BIT4)
260 #define mUsbEPoutRsTgClr(u8ep) USB_BYTE_REG_WRITE((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
261 USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))&~BIT4)
263 #define mUsbEPinStallSet(u8ep) USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
264 USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))|BIT3)
266 #define mUsbEPinStallClr(u8ep) USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
267 USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))&~BIT3)
269 #define mUsbEPoutStallSet(u8ep) USB_BYTE_REG_WRITE((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
270 USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))|BIT3)
272 #define mUsbEPoutStallClr(u8ep) USB_BYTE_REG_WRITE((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \
273 USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))&~BIT3)
275 #define mUsbEPinStallST(u8ep) ((USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))& BIT3) >> 3)
277 #define mUsbEPoutStallST(u8ep) ((USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))& BIT3) >> 3)
279 #define mUsbEPMapRd(EPn) (USB_BYTE_REG_READ((0x30+(EPn-1))))
281 #define mUsbFIFOCfgRd(FIFOn) (USB_BYTE_REG_READ((0x90+FIFOn)))
283 #define vUsb_Data_Out0Byte(void) USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_REG, \
284 USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_REG&~BIT7))
287 #define vUsb_Data_In0Byte(void) USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_REG, \
288 USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_REG&~BIT6))
290 #define vUsb_ep0end(void) \
292 eUsbCxCommand = CMD_VOID; \
293 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01); \
296 #define vUsb_ep0fail(void) USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04)
300 USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \
301 (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT1)); \
302 UsbChirpFinish = FALSE; \
305 #define vUsb_suspend() USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \
306 (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT2))
308 #define vUsb_resm() USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \
309 (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT3))
314 LOCAL void flash_read_data(void)
318 // to keep tracking the txrx fifo
319 // max 64 bytes for transmission one time,
320 if (u16TxRxCounter < EP0MAXPACKETSIZE)
321 u8temp = (uint8_t) u16TxRxCounter;
323 u8temp = EP0MAXPACKETSIZE;
325 u16TxRxCounter -= (uint16_t) u8temp;
328 register uint8_t u8count;
331 for (u8count = 0; u8count < (u8temp/4); u8count ++)
337 // pack data into word size
338 ep0_low = *pu8DescriptorEX++;
339 ep0_high = *pu8DescriptorEX++;
341 // composed the data as a word
342 ep0_data = (ep0_high << 16) + ep0_low;
344 USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, ep0_data);
347 remainder = u8temp % 4;
349 // Check whether there are data needed to be filled into the FIFO
356 // pack data into word size
357 ep0_low = *pu8DescriptorEX++;
358 ep0_high = *pu8DescriptorEX++;
360 ep0_data = (ep0_high << 16) + ep0_low;
362 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x7);
363 USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, ep0_data);
365 else if (remainder == 2)
367 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x3);
368 USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, *pu8DescriptorEX);
370 else if (remainder == 1)
372 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1);
373 USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, *pu8DescriptorEX);
376 // Restore CBus FIFO size to word size
377 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xf);
380 // end of the data stage
381 if (u16TxRxCounter == 0)
383 eUsbCxCommand = CMD_VOID;
384 eUsbCxFinishAction = ACT_DONE;
388 /***********************************************************************/
391 // 1. Transmit data to EP0 FIFO.
394 /***********************************************************************/
395 LOCAL void vUsb_ep0tx(void)
397 switch (eUsbCxCommand)
399 case CMD_GET_DESCRIPTOR:
404 /* Mark endpoint STALL */
405 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, BIT6);
410 // eUsbCxFinishAction = ACT_IDLE;
414 /***********************************************************************/
417 // 1. Receive data from EP0 FIFO.
420 /***********************************************************************/
421 LOCAL void vUsb_ep0rx(void)
424 switch (eUsbCxCommand)
426 case CMD_SET_DESCRIPTOR:
434 if (u16TxRxCounter != 0)
435 eUsbCxFinishAction = ACT_IDLE;
439 LOCAL void vUsbClrEPx(void)
443 // Clear All EPx Toggle Bit
444 for (u8ep = 1; u8ep <= FUSB200_MAX_EP; u8ep ++)
446 mUsbEPinRsTgSet(u8ep);
447 mUsbEPinRsTgClr(u8ep);
449 for (u8ep = 1; u8ep <= FUSB200_MAX_EP; u8ep ++)
451 mUsbEPoutRsTgSet(u8ep);
452 mUsbEPoutRsTgClr(u8ep);
457 /***********************************************************************/
460 // 1. Send 2 bytes status to host.
462 // output: TRUE or FALSE (BOOLEAN)
463 /***********************************************************************/
464 LOCAL BOOLEAN bGet_status(void)
466 uint8_t RecipientStatusLow;
468 RecipientStatusLow = UsbStatus[mDEV_REQ_REQ_RECI() & 0x0F];
470 //ZM_CBUS_FIFO_SIZE_REG = 0x3;
471 //ZM_EP0_DATA_REG = RecipientStatusLow;
473 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x3);
474 USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, RecipientStatusLow);
476 // Restore CBus FIFO size to word size
477 //ZM_CBUS_FIFO_SIZE_REG = 0xf;
478 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xf);
480 eUsbCxFinishAction = ACT_DONE;
484 /***********************************************************************/
487 // 1. Send 2 bytes status to host.
489 // output: TRUE or FALSE (BOOLEAN)
490 /***********************************************************************/
491 LOCAL BOOLEAN bClear_feature(void)
493 if (mDEV_REQ_VALUE() > cUSB_FEATSEL_END)
496 if ((mDEV_REQ_VALUE() == 0) && (mDEV_REQ_REQ_RECI() != cUSB_REQTYPE_ENDPOINT))
500 eUsbCxFinishAction = ACT_DONE;
505 /***********************************************************************/
508 // 1. Send 2 bytes status to host.
510 // output: TRUE or FALSE (BOOLEAN)
511 /***********************************************************************/
512 #if ZM_SELF_TEST_MODE
516 #define TEST_SE0_NAK 0x08
517 #define TEST_PKY 0x10
519 uint16_t TestPatn0[] = { TEST_J, TEST_K, TEST_SE0_NAK };
520 uint32_t TestPatn1[] = {
521 0x00000000, 0x00000000, 0xAA00AA00, // JKJKJKJK x 9
522 0xAAAAAAAA, 0xEEAAAAAA, // AA x 8
523 0xEEEEEEEE, 0xFEEEEEEE, // EE x 8
524 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF, // FF x 11
525 0xF7EFDFBF, 0x7EFCFDFB, 0xFDFBDFBF};
528 LOCAL BOOLEAN bSet_feature(void)
531 //A_PRINTF("bSet_feature...\n\r");
533 switch (mDEV_REQ_VALUE()) // FeatureSelector
535 case 0: // ENDPOINT_HALE
537 // always check RECEIPIENT
538 if (mDEV_REQ_REQ_RECI() == cUSB_REQTYPE_ENDPOINT)
540 eUsbCxFinishAction = ACT_DONE;
549 case 1 : // Device Remote Wakeup
550 // Set "Device_Remote_Wakeup", Turn on the"RMWKUP" bit in Mode Register
552 //USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT0);
553 eUsbCxFinishAction = ACT_DONE;
556 #if ZM_SELF_TEST_MODE
557 case 2 : // Test Mode
558 // ii = mDEV_REQ_INDEX() >> 8;
559 // switch (ii) // TestSelector
560 switch (mDEV_REQ_INDEX() >> 8) // TestSelector
564 case 0x3: // TEST_SE0_NAK
565 // mUsbTsMdWr(TestPatn0[(mDEV_REQ_INDEX() >> 8) - 1]);
566 //ZM_PHY_TEST_SELECT_REG = TestPatn0[(mDEV_REQ_INDEX() >> 8) - 1];
567 USB_BYTE_REG_WRITE(ZM_PHY_TEST_SELECT_OFFSET, (TestPatn0[(mDEV_REQ_INDEX() >> 8) - 1]));
568 eUsbCxFinishAction = ACT_DONE;
571 case 0x4: // Test_Packet
572 // mUsbTsMdWr(TEST_PKY);
573 // mUsbEP0DoneSet(); // special case: follow the test sequence
574 //ZM_PHY_TEST_SELECT_REG = TEST_PKY;
575 //ZM_CX_CONFIG_STATUS_REG = 0x01;
576 USB_BYTE_REG_WRITE(ZM_PHY_TEST_SELECT_OFFSET, TEST_PKY);
577 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, BIT0);
578 /***********************************************************************///////
579 // Jay ask to modify, 91-6-5 (Begin) //
580 /***********************************************************************///////
581 // mUsbTsMdWr(TEST_PKY);
582 // mUsbEP0DoneSet(); // special case: follow the test sequence
583 //ZM_PHY_TEST_SELECT_REG = TEST_PKY;
584 USB_BYTE_REG_WRITE(ZM_PHY_TEST_SELECT_OFFSET, TEST_PKY);
586 //ZM_CX_CONFIG_STATUS_REG = 0x01;
587 /***********************************************************************///////
588 // Jay ask to modify, 91-6-5 (Begin) //
589 /***********************************************************************///////
593 /* Set to two bytes mode */
594 //ZM_CBUS_FIFO_SIZE_REG = 0x0f;
595 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x0f);
597 for (ii = 0; ii < sizeof(TestPatn1)/sizeof(uint32_t); ii++)
599 //ZM_EP0_DATA_REG = TestPatn1[ii];
600 USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, TestPatn1[ii]);
603 /* Set to one byte mode */
604 //ZM_CBUS_FIFO_SIZE_REG = 0x07;
605 //ZM_EP0_DATA_REG = 0x007EFDFB;
606 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x07);
607 USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, 0x007EFDFB);
609 /* Set to four bytes mode */
610 //ZM_CBUS_FIFO_SIZE_REG = 0x0f;
611 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x0f);
613 /***********************************************************************///////
614 // Jay ask to modify, 91-6-5 (End) //
615 /***********************************************************************///////
617 // Turn on "r_test_packet_done" bit(flag) (Bit 5)
619 //ZM_CX_CONFIG_STATUS_REG = 0x02;
620 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, BIT1);
623 case 0x5: // Test_Force_Enable
624 //FUSBPort[0x08] = 0x20; //Start Test_Force_Enable
636 if (eUsbCxFinishAction == ACT_DONE)
643 /***********************************************************************/
646 // 1. Set addr to FUSB200 register.
648 // output: TRUE or FALSE (BOOLEAN)
649 /***********************************************************************/
650 LOCAL BOOLEAN bSet_address(void)
653 //A_PRINTF("bSet_feature...\n\r");
655 if (mDEV_REQ_VALUE() >= 0x0100)
659 // zfUartSendStrAndHex((uint8_t *) "USB_SET_ADDRESS=", mDEV_REQ_VALUE());
660 //ZM_DEVICE_ADDRESS_REG = mDEV_REQ_VALUE();
661 USB_BYTE_REG_WRITE(ZM_DEVICE_ADDRESS_OFFSET, mDEV_REQ_VALUE());
663 eUsbCxFinishAction = ACT_DONE;
668 /***********************************************************************/
671 // 1. Point to the start location of the correct descriptor.
672 // 2. set the transfer length
674 // output: TRUE or FALSE (BOOLEAN)
675 /***********************************************************************/
676 LOCAL BOOLEAN bGet_descriptor(void)
678 //A_PRINTF("bGet_descriptor...\n\r");
680 // Change Descriptor type
682 u8ConfigDescriptorEX[mTABLE_IDX(1)] =
683 m2BYTE(CONFIG_LENGTH, DT_CONFIGURATION);
684 u8OtherSpeedConfigDescriptorEX[mTABLE_IDX(1)] =
685 m2BYTE(CONFIG_LENGTH, DT_OTHER_SPEED_CONFIGURATION);
688 //*(volatile uint32_t*)0x1c0004 = 'G';
690 switch (mDEV_REQ_VALUE_HIGH())
692 case 1: // device descriptor
693 pu8DescriptorEX = u8UsbDeviceDescriptor;
694 u16TxRxCounter = mTABLE_LEN(u8UsbDeviceDescriptor[0]);
695 //u16TxRxCounter = 18;
698 case 2: // configuration descriptor
699 // It includes Configuration, Interface and Endpoint Table
700 // zfUartSendStr((uint8_t *)"Configuration Descriptor\r\n");
701 switch (mDEV_REQ_VALUE_LOW())
703 case 0x00: // configuration no: 0
704 pu8DescriptorEX = u8ConfigDescriptorEX;
705 u16TxRxCounter = u8ConfigDescriptorEX[1];
706 //u16TxRxCounter = 46;
713 case 3: // string descriptor
714 // DescriptorIndex = low_byte of wValue
715 // zfUartSendStr((uint8_t *)"String Descriptor\r\n");
716 switch (mDEV_REQ_VALUE_LOW())
719 pu8DescriptorEX = u8String00Descriptor;
720 //u16TxRxCounter = 4;
724 pu8DescriptorEX = u8String10Descriptor;
725 //u16TxRxCounter = 12;
729 pu8DescriptorEX = u8String20Descriptor;
730 //u16TxRxCounter = 24;
734 pu8DescriptorEX = u8String30Descriptor;
740 u16TxRxCounter = mTABLE_LEN(pu8DescriptorEX[0]);
743 case 6: // Device_Qualifier descritor
744 // zfUartSendStr((uint8_t *) "Device_Qualifier Descriptor\r\n");
745 pu8DescriptorEX = u8DeviceQualifierDescriptorEX;
746 u16TxRxCounter = mTABLE_LEN(u8DeviceQualifierDescriptorEX[0]);
747 //u16TxRxCounter = 10;
750 case 7: // Other_Speed_Configuration
751 // zfUartSendStr((uint8_t *)"Other_Speed Descriptor\r\n");
752 // It includes Configuration, Interface and Endpoint Table
753 pu8DescriptorEX = u8OtherSpeedConfigDescriptorEX;
754 u16TxRxCounter = u8OtherSpeedConfigDescriptorEX[1];
755 //u16TxRxCounter = 46;
759 // zfUartSendStrAndHex((uint8_t *) "Descriptor error=", mDEV_REQ_VALUE_HIGH());
763 if (u16TxRxCounter > mDEV_REQ_LENGTH())
764 u16TxRxCounter = mDEV_REQ_LENGTH();
769 // somehow if there is still data need to send out, we shouldn't set CX_DONE
770 // wait for another EP0_IN
771 if( u16TxRxCounter > 0 )
773 eUsbCxCommand = CMD_GET_DESCRIPTOR;
780 /***********************************************************************/
781 // bGet_configuration()
783 // 1. Send 1 bytes configuration value to host.
786 /***********************************************************************/
787 LOCAL BOOLEAN bGet_configuration(void)
790 //A_PRINTF("bGet_configuration...\n\r");
792 //ZM_CBUS_FIFO_SIZE_REG = 0x1;
793 //ZM_EP0_DATA_REG = u8UsbConfigValue;
794 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1);
795 USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, u8UsbConfigValue);
797 // Restore CBus FIFO size to word size
798 //ZM_CBUS_FIFO_SIZE_REG = 0xf;
799 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xf);
801 eUsbCxFinishAction = ACT_DONE;
806 /***********************************************************************/
807 // bSet_configuration()
809 // 1. Get 1 bytes configuration value from host.
810 // 2-1. if (value == 0) then device return to address state
811 // 2-2. if (value match descriptor table)
812 // then config success & Clear all EP toggle bit
813 // 2-3 else stall this command
815 // output: TRUE or FALSE
816 /***********************************************************************/
817 LOCAL BOOLEAN bSet_configuration(void)
819 void vUsbClrEPx(void);
821 //A_PRINTF("bSet_configuration...\n\r");
823 if (mLOW_BYTE(mDEV_REQ_VALUE()) == 0)
825 u8UsbConfigValue = 0;
827 //ZM_DEVICE_ADDRESS_REG &= ~BIT7;
828 USB_BYTE_REG_WRITE(ZM_DEVICE_ADDRESS_OFFSET, (USB_BYTE_REG_READ(ZM_DEVICE_ADDRESS_OFFSET)&~BIT7));
832 if (mUsbHighSpeedST()) // First judge HS or FS??
834 if (mLOW_BYTE(mDEV_REQ_VALUE()) > HS_CONFIGURATION_NUMBER)
837 u8UsbConfigValue = mLOW_BYTE(mDEV_REQ_VALUE());
838 vUsbFIFO_EPxCfg_HS();
840 // Set into 512 byte mode */
841 //ZM_SOC_USB_MODE_CTRL_REG |= BIT2;
842 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
843 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT2));
848 if (mLOW_BYTE(mDEV_REQ_VALUE()) > FS_CONFIGURATION_NUMBER)
851 u8UsbConfigValue = mLOW_BYTE(mDEV_REQ_VALUE());
852 vUsbFIFO_EPxCfg_FS();
854 // Set into 64 byte mode */
855 //M_SOC_USB_MODE_CTRL_REG &= ~BIT2;
856 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
857 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&~BIT2));
861 //ZM_DEVICE_ADDRESS_REG |= BIT7;
862 USB_BYTE_REG_WRITE(ZM_DEVICE_ADDRESS_OFFSET, \
863 (USB_BYTE_REG_READ(ZM_DEVICE_ADDRESS_OFFSET)|BIT7));
868 mUSB_REG_OUT_INT_ENABLE();
872 eUsbCxFinishAction = ACT_DONE;
877 /***********************************************************************/
882 // output: TRUE or FALSE
883 /***********************************************************************/
884 LOCAL BOOLEAN bGet_interface(void)
887 // A_PRINTF("bGet_interface...\n\r");
888 if (mUsbCfgST() == 0)
891 // If there exists many interfaces, Interface0,1,2,...N,
892 // You must check & select the specific one
893 switch (u8UsbConfigValue)
895 #if (HS_CONFIGURATION_NUMBER >= 1)
898 if (mDEV_REQ_INDEX() > HS_C1_INTERFACE_NUMBER)
902 #if (HS_CONFIGURATION_NUMBER >= 2)
905 if (mDEV_REQ_INDEX2() > HS_C2_INTERFACE_NUMBER)
913 //ZM_CBUS_FIFO_SIZE_REG = 0x1;
914 //ZM_EP0_DATA_REG = u8UsbInterfaceAlternateSetting;
915 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1);
916 USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, u8UsbInterfaceAlternateSetting);
918 // Restore CBus FIFO size to word size
919 //ZM_CBUS_FIFO_SIZE_REG = 0xf;
920 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x0f);
922 u16TxRxCounter = 1; //sizeof(u8UsbInterfaceAlternateSetting);
923 eUsbCxFinishAction = ACT_DONE;
927 /***********************************************************************/
930 // 1-1. If (the device stays in Configured state)
931 // &(command match the alternate setting)
932 // then change the interface
933 // 1-2. else stall it
935 // output: TRUE or FALSE
936 /***********************************************************************/
937 LOCAL BOOLEAN bSet_interface(void)
939 void vUsbClrEPx(void);
941 //A_PRINTF("bSet_interface...\n\r");
946 // If there exists many interfaces, Interface0,1,2,...N,
947 // You must check & select the specific one
948 switch (mDEV_REQ_INDEX())
950 case 0: // Interface0
952 if (mLOW_BYTE(mDEV_REQ_VALUE()) == mLOW_BYTE(u8ConfigDescriptorEX[mTABLE_IDX(12)]))
954 u8UsbInterfaceValue = (uint8_t) mDEV_REQ_INDEX();
955 u8UsbInterfaceAlternateSetting = mLOW_BYTE(mDEV_REQ_VALUE());
956 if (mUsbHighSpeedST()) // First judge HS or FS??
958 vUsbFIFO_EPxCfg_HS();
960 // Set into 512 byte mode */
961 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
962 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT2));
966 vUsbFIFO_EPxCfg_FS();
968 // Set into 64 byte mode */
969 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
970 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&~BIT2));
973 eUsbCxFinishAction = ACT_DONE;
976 mUSB_REG_OUT_INT_ENABLE();
979 // case 1: // Interface1
980 // case 2: // Interface2
988 /***********************************************************************/
991 // 1. Send data(max or short packet) to host.
994 /***********************************************************************/
995 LOCAL void vUsbEP0TxData(void)
1000 //wait a little to make sure ep0 fifo is empty before sending data out
1004 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, USB_BYTE_REG_READ(ZM_CX_CONFIG_STATUS_OFFSET)|BIT3);
1008 if(USB_BYTE_REG_READ(ZM_CX_CONFIG_STATUS_OFFSET)&BIT5)
1013 // to keep tracking the txrx fifo
1014 // max 64 bytes for transmission one time,
1015 if (u16TxRxCounter < EP0MAXPACKETSIZE)
1016 u8temp = (uint8_t) u16TxRxCounter;
1018 u8temp = EP0MAXPACKETSIZE;
1020 u16TxRxCounter -= (uint16_t) u8temp;
1023 register uint8_t u8count;
1026 for (u8count = 0; u8count < (u8temp/4); u8count ++)
1032 // pack data into word size
1033 ep0_low = *pu8DescriptorEX++;
1034 ep0_high = *pu8DescriptorEX++;
1036 // composed the data as a word
1037 ep0_data = (ep0_high << 16) + ep0_low;
1039 USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, ep0_data);
1042 remainder = u8temp % 4;
1044 // Check whether there are data needed to be filled into the FIFO
1051 // pack data into word size
1052 ep0_low = *pu8DescriptorEX++;
1053 ep0_high = *pu8DescriptorEX++;
1055 ep0_data = (ep0_high << 16) + ep0_low;
1057 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x7);
1058 USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, ep0_data);
1060 else if (remainder == 2)
1062 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x3);
1063 USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, *pu8DescriptorEX);
1065 else if (remainder == 1)
1067 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1);
1068 USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, *pu8DescriptorEX);
1071 // Restore CBus FIFO size to word size
1072 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xf);
1075 // end of the data stage
1076 if (u16TxRxCounter == 0)
1078 eUsbCxCommand = CMD_VOID;
1079 eUsbCxFinishAction = ACT_DONE;
1083 /***********************************************************************/
1086 // 1. Receive data(max or short packet) from host.
1089 /***********************************************************************/
1090 LOCAL void vUsbEP0RxData(void)
1094 if (u16TxRxCounter < EP0MAXPACKETSIZE)
1095 u8temp = (uint8_t) u16TxRxCounter;
1097 u8temp = EP0MAXPACKETSIZE;
1099 u16TxRxCounter -= (uint16_t) u8temp;
1101 // Receive u8Temp bytes data
1103 register uint8_t u8count;
1104 uint8_t *p = (uint8_t *) pu8DescriptorEX;
1106 for (u8count = 0; u8count < ((u8temp+3) >> 2); u8count ++)
1110 ep0_data = USB_WORD_REG_READ(ZM_EP0_DATA_OFFSET); //read usb ep0 fifo data,
1113 // skip the writing to ram if not build for rom code
1114 #if 0 //1 defined(_ROM_)
1115 *p++ = mGetByte0(ep0_data);
1116 *p++ = mGetByte1(ep0_data);
1117 *p++ = mGetByte2(ep0_data);
1118 *p++ = mGetByte3(ep0_data);
1120 fwCheckSum = fwCheckSum ^ ep0_data;
1124 pu8DescriptorEX += (u8count << 1);
1127 // end of the data stage
1128 if (u16TxRxCounter == 0)
1130 eUsbCxCommand = CMD_VOID;
1131 eUsbCxFinishAction = ACT_DONE;
1136 /***********************************************************************/
1137 // vUsb_SetupDescriptor()
1139 // Setup the pointer to the descriptor in the SRAM and EEPROM
1141 /***********************************************************************/
1142 LOCAL void vUsb_SetupDescriptor(void)
1144 // eeprom exist the usb configuration is only supportted in rom version
1147 // check the offset of PID's value is correct or not, need to be defined!!, ryan
1150 if( *((uint32_t*)USB_DESC_IN_EEPROM_FLAG_ADDR) == USB_DESC_IN_EEP_PATTERN)
1152 A_PRINTF("- custom usb config\n");
1154 u8UsbDeviceDescriptor = (uint16_t *) USB_DEVICE_DESCRIPTOR_ADDR;
1155 u8String00Descriptor = (uint16_t *) USB_STRING00_DESCRIPTOR_ADDR;
1156 u8String10Descriptor = (uint16_t *) USB_STRING10_DESCRIPTOR_ADDR;
1157 u8String20Descriptor = (uint16_t *) USB_STRING20_DESCRIPTOR_ADDR;
1158 u8String30Descriptor = (uint16_t *) USB_STRING30_DESCRIPTOR_ADDR;
1163 u8UsbDeviceDescriptor = (uint16_t *) &UsbDeviceDescriptor;
1164 u8String00Descriptor = (uint16_t *) &String00Descriptor;
1165 u8String10Descriptor = (uint16_t *) &String10Descriptor;
1166 u8String20Descriptor = (uint16_t *) &String20Descriptor;
1167 u8String30Descriptor = (uint16_t *) &String30Descriptor;
1170 /* Point Device Qualifierdescriptors and Other Speed Descriptor
1171 * - Device Qualifierdescriptor is located in RAM segment, extern these
1172 * symbol at the beginning of this file
1177 /***********************************************************************/
1178 // bStandardCommand()
1180 // 1. Process standard command.
1182 // output: TRUE or FALSE
1183 /***********************************************************************/
1184 LOCAL BOOLEAN bStandardCommand(void)
1186 switch (mDEV_REQ_REQ()) // by Standard Request codes
1188 case USB_GET_STATUS:
1189 return (A_USB_GET_STATUS());
1191 case USB_CLEAR_FEATURE:
1192 return (A_USB_CLEAR_FEATURE());
1194 case USB_SET_FEATURE:
1195 return (A_USB_SET_FEATURE());
1197 case USB_SET_ADDRESS:
1198 return (A_USB_SET_ADDRESS());
1200 case USB_GET_DESCRIPTOR:
1201 return (A_USB_GET_DESCRIPTOR());
1204 case USB_SET_DESCRIPTOR:
1205 // if (!bUsbEP0HaltSt)
1206 return (bSet_descriptor());
1209 case USB_GET_CONFIGURATION:
1210 return (A_USB_GET_CONFIG());
1212 case USB_SET_CONFIGURATION:
1213 //A_PRINTF(" \n--> SET_CONFIGURATION\r\n");
1214 // if (!bUsbEP0HaltSt)
1215 // return (A_USB_SET_CONFIG());
1220 #if ENABLE_SWAP_DATA_MODE
1221 // SWAP FUNCTION should be enabled while DMA engine is not working,
1222 // the best place to enable it is before we trigger the DMA
1223 MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1;
1224 MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1;
1226 #if SYSTEM_MODULE_HP_EP5
1227 MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1;
1230 #if SYSTEM_MODULE_HP_EP6
1231 MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1;
1234 #endif //ENABLE_SWAP_DATA_MODE
1237 #if !ENABLE_STREAM_MODE
1238 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT3);
1242 // 04/01: bit0 could disable lpdn dma, which is good at debugging while async_fifo have problem,
1243 // we could disable this and check the fifo_rcv_size to see if we have correct at fifo or not
1245 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, ((USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT1))); // upstream DMA enable
1246 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, ((USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT0))); // downstream DMA enable
1248 #if SYSTEM_MODULE_HP_EP5
1249 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, ((USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT8)));
1252 #if SYSTEM_MODULE_HP_EP6
1253 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, ((USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT9)));
1257 /////////////ENABLE_STREAM_MODE/////////////////
1258 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
1259 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT1))); // disable upstream DMA mode
1260 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
1261 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT3))); // enable upstream stream mode
1262 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET,
1263 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(BIT1))); // enable upstream DMA mode
1265 #if SYSTEM_MODULE_HP_EP1
1266 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
1267 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT0))); // diable LP downstream DMA mode
1268 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
1269 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(BIT6))); // enable LP downstream stream mode
1270 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
1271 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(BIT0))); // enable LP downstream DMA mode
1274 #if SYSTEM_MODULE_HP_EP5
1275 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
1276 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT8))); // disable HP downstream DMA mode
1277 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
1278 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(BIT7))); // enable HP downstream stream mode
1279 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
1280 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT8)); // enable HP downstream DMA mode
1284 #if SYSTEM_MODULE_HP_EP6
1285 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
1286 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT9))); // disable MP downstream DMA mode
1287 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
1288 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT10)); // enable MP downstream stream mode
1289 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
1290 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT9)); // enable MP downstream DMA mode
1293 USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \
1294 (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(BIT4))); // define the host dma buffer size - 4096(00) 8192 (01) 16384(10) 32768(11) bytes
1296 USB_WORD_REG_WRITE(ZM_SOC_USB_TIME_CTRL_OFFSET, USB_STREAM_MODE_TIMEOUT_CTRL); // set stream mode timeout critirea
1298 USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, USB_STREAM_MODE_AGG_CNT); // set stream mode packet buffer critirea
1299 #endif //!ENABLE_STREAM_MODE
1303 //extern void Magpie_init(void);
1309 case USB_GET_INTERFACE:
1310 // A_PRINTF(" \n--> GET_INTERFACE\r\n");
1311 // if (!bUsbEP0HaltSt)
1312 //return (bGet_interface());
1313 return (A_USB_GET_INTERFACE());
1315 case USB_SET_INTERFACE:
1316 // A_PRINTF(" \n--> SET_INTERFACE\r\n");
1317 // if (!bUsbEP0HaltSt)
1318 // return (bSet_interface());
1319 // return (A_USB_SET_INTERFACE());
1320 A_USB_SET_INTERFACE();
1327 LOCAL void flash_read(uint16_t len, uint16_t ofset)
1332 uint16_t end_addr = 0x0;
1333 uint16_t start_addr = 0x0;
1334 uint32_t ep0_data = 0x0;
1337 //sanity check, just in case
1338 if(u16TxRxCounter < EP0MAXPACKETSIZE)
1339 u8temp = (uint8_t) u16TxRxCounter;
1342 if( u16TxRxCounter > 64 )
1343 len = EP0MAXPACKETSIZE;
1345 len = u16TxRxCounter + 4-(u16TxRxCounter%4);
1349 end_addr = start_addr + len;
1351 A_PRINTF("read flash from %x to %x\n", ofset, end_addr);
1353 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF);
1355 for (i = 0; start_addr < end_addr; i++, start_addr+=4)
1357 // A_SFLASH_READ(1, ofset, 4, buf + i*4);
1358 // *((volatile uint32_t *)(buf+i*4)) = *(uint32_t *)(0xf000000+start_addr);
1359 // A_PRINTF(" %08x ", *(uint32_t *)(0xf000000+start_addr));
1360 USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, *(uint32_t *)(0xf000000+start_addr));
1363 // A_PRINTF("\n\n\r");
1364 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, BIT0);
1370 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF);
1372 for(i=0; i<len; i+4)
1374 ep0_data = *(uint32_t *)(buf+i);
1376 USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, ep0_data);
1379 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF);
1381 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, BIT0);
1385 extern BOOLEAN download_enable;
1387 LOCAL void VendorCommand(void)
1389 #define cUSB_REQ_DOWNLOAD 0x30
1390 #define cUSB_REQ_DOWNLOAD_COMP 0x31
1391 #define cUSB_REQ_BOOT 0x32
1392 #define cUSB_REQ_RESERVED_1 0x33
1393 #define cUSB_REQ_RESERVED_2 0x34
1395 #define cUSB_REQ_FLASH_READ 0x35
1396 #define cUSB_REQ_FLASH_READ_COMP 0x36
1398 //#define ZM_FIRMWARE_ADDR 0x200000
1400 void (*funcPtr)(void);
1401 uint16_t *text_addr = 0;
1402 uint32_t ep0_data = 0x0;
1403 // static download_enable = FALSE;
1405 CURRENT_PROGRAM = (uint32_t)VendorCommand;
1407 switch (mDEV_REQ_REQ())
1409 case cUSB_REQ_FLASH_READ:
1411 ep0_data = *(uint32_t *)(0xf000000);
1413 u16TxRxCounter = mDEV_REQ_LENGTH();
1414 pu8DescriptorEX = (uint16_t*)( (mDEV_REQ_VALUE()));
1416 // A_PRINTF("Get a flash_read (%x) request with lenght:%d, and offset %x...\n", cUSB_REQ_FLASH_READ, u16TxRxCounter, pu8DescriptorEX);
1418 // eUsbCxCommand = CMD_GET_CUSTOM_DATA;
1421 flash_read(u16TxRxCounter, (uint16_t)pu8DescriptorEX);
1423 eUsbCxCommand = CMD_GET_CUSTOM_DATA;
1424 USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, ep0_data);
1425 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF);
1426 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, BIT0);
1430 case cUSB_REQ_FLASH_READ_COMP:
1432 ep0_data = *(uint32_t *)(0xf000004);
1433 A_PRINTF("get a upload complete request...\n");
1435 //eUsbCxCommand = CMD_SET_DESCRIPTOR;
1436 // USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1);
1437 USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, ep0_data);
1438 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF);
1439 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, BIT0);
1441 //download_enable = TRUE;
1445 case cUSB_REQ_DOWNLOAD:
1446 //if( download_enable )
1448 u16TxRxCounter = mDEV_REQ_LENGTH();
1449 pu8DescriptorEX = (uint16_t*)( (mDEV_REQ_VALUE() << 8));
1450 A_PRINTF("\t[cUSB_REQ_DOWNLOAD]: 0x%08x, %02x\n\r", pu8DescriptorEX, u16TxRxCounter);
1452 eUsbCxCommand = CMD_SET_DESCRIPTOR;
1456 // A_PRINTF("firmware download deny!!\n\r");
1459 case cUSB_REQ_DOWNLOAD_COMP:
1461 text_addr = (uint16_t*)( (mDEV_REQ_VALUE() << 8));
1462 A_PRINTF("\t\n\r==>[cUSB_REQ_COMP]: 0x%08x\n\r", text_addr);
1464 if (fwCheckSum != 0)
1466 A_PRINTF("cksum=%x", fwCheckSum);
1469 DEBUG_SYSTEM_STATE |= BIT27;
1471 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1);
1472 USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, 1);
1473 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF);
1474 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, BIT0);
1480 //ZM_CX_CONFIG_STATUS_REG = 0x01;
1482 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1);
1483 USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, 0);
1484 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF);
1485 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, BIT0);
1487 A_PRINTF("VendorCmd: DownloadComplete!\n");
1489 DEBUG_SYSTEM_STATE &= ~BIT27;
1490 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x3f;
1492 // this value should be assign from host along with the DOWNLOAD_COMP in wValue
1493 if( text_addr != 0 )
1494 funcPtr = (void *)(text_addr);
1496 download_enable = TRUE;
1498 // only jump to text address in ROM version
1500 // funcPtr(); // jump to the firmware and never return
1505 // A_PRINTF("Integrity is not fine!\n\r");
1512 /***********************************************************************/
1515 // 1. Read 8-byte setup packet.
1516 // 2. Decode command as Standard, Class, Vendor or NOT support command
1519 /***********************************************************************/
1520 extern uint16_t u8HSConfigDescriptor01[];
1521 extern uint16_t u8FSConfigDescriptor01[];
1523 LOCAL void vUsb_ep0setup(void)
1525 register uint8_t ii;
1526 volatile uint32_t ep0_data;
1527 //BOOLEAN bStandardCommand(void);
1528 //BOOLEAN bClassCommand(void);
1529 //void VendorCommand(void);
1531 //zcPrint._printf("\t---> %s <---\n\r", __FUNCTION__);
1532 if (UsbChirpFinish != TRUE)
1534 UsbChirpFinish = TRUE;
1536 // Setup Descriptor pointer
1537 //vUsb_SetupDescriptor();
1540 u8OtherSpeedConfigDescriptorEX[0] = 0x0709;
1542 if (mUsbHighSpeedST()) // Judge HS or FS??
1544 u8ConfigDescriptorEX = u8HSConfigDescriptor01;
1546 // copy Device Qualifierdescriptors (from rom to sram)
1547 for (ii = 1; ii < 4; ii++)
1549 u8DeviceQualifierDescriptorEX[ii] = u8UsbDeviceDescriptor[ii];
1552 // Number of Other-speed Configurations
1553 // byte 9 Reserved for future use, must be zero
1554 u8DeviceQualifierDescriptorEX[4] = (u8UsbDeviceDescriptor[8] >> 8) & 0x00ff;
1556 // copy Other Speed Descriptor
1557 for (ii = 1; ii < (USB_TOTAL_DESC_LEN/2); ii++)
1559 u8OtherSpeedConfigDescriptorEX[ii] = u8FSConfigDescriptor01[ii];
1563 MaxPktSize = HS_C1_I0_A0_EP1_MAX_PACKET;
1564 // Device stays in High Speed
1565 u8DeviceDescriptorEX = u8HSDeviceDescriptor;
1567 // copy Device Qualifierdescriptors (from rom to sram)
1568 for (ii = mTABLE_WID(2) ; ii < mTABLE_WID(8); ii ++)
1569 u8DeviceQualifierDescriptorEX[ii] = u8FSDeviceDescriptor[ii];
1571 // Number of Other-speed Configurations
1572 // byte 9 Reserved for future use, must be zero
1573 u8DeviceQualifierDescriptorEX[mTABLE_IDX(8)]
1574 = mHIGH_BYTE(u8FSDeviceDescriptor[mTABLE_IDX(17)]);
1575 u8ConfigDescriptorEX = u8HSConfigDescriptor01;
1576 u8OtherSpeedConfigDescriptorEX = u8FSConfigDescriptor01;
1581 u8ConfigDescriptorEX = u8FSConfigDescriptor01;
1583 // copy Device Qualifierdescriptors (from rom to sram)
1584 for (ii = 1; ii < 4; ii++)
1586 u8DeviceQualifierDescriptorEX[ii] = u8UsbDeviceDescriptor[ii];
1589 // Number of Other-speed Configurations
1590 // byte 9 Reserved for future use, must be zero
1591 u8DeviceQualifierDescriptorEX[4] = (u8UsbDeviceDescriptor[8] >> 8) & 0x00ff;
1593 // copy Other Speed Descriptor
1594 for (ii = 1; ii < (USB_TOTAL_DESC_LEN/2); ii++)
1596 u8OtherSpeedConfigDescriptorEX[ii] = u8HSConfigDescriptor01[ii];
1600 MaxPktSize = FS_C1_I0_A0_EP1_MAX_PACKET;
1601 // Device stays in Full Speed
1602 u8DeviceDescriptorEX = u8FSDeviceDescriptor;
1604 // copy Device Qualifierdescriptors (from rom to sram)
1605 for (ii = mTABLE_WID(2) ; ii < mTABLE_WID(8); ii ++)
1606 u8DeviceQualifierDescriptorEX[ii] = u8HSDeviceDescriptor[ii];
1608 // Number of Other-speed Configurations
1609 // byte 9 Reserved for future use, must be zero
1610 u8DeviceQualifierDescriptorEX[mTABLE_IDX(8)]
1611 = mHIGH_BYTE(u8HSDeviceDescriptor[mTABLE_IDX(17)]);
1612 u8ConfigDescriptorEX = u8FSConfigDescriptor01;
1613 u8OtherSpeedConfigDescriptorEX = u8HSConfigDescriptor01;
1617 u8DeviceQualifierDescriptorEX[0] = 0x060A;
1620 if( USB_BYTE_REG_READ(ZM_CX_CONFIG_STATUS_OFFSET) & BIT5)
1625 //ep0_data = ZM_EP0_DATA_REG;
1626 ep0_data = USB_WORD_REG_READ(ZM_EP0_DATA_OFFSET);
1628 ii = mGetByte0(ep0_data);
1630 ControlCmd.Direction = (uint8_t)(ii & 0x80);// xfer Direction(IN, OUT)
1631 ControlCmd.Type = (uint8_t)(ii & 0x60); // type(Standard, Class, Vendor)
1632 ControlCmd.Object = (uint8_t)(ii & 0x03); // Device, Interface, Endpoint
1634 ControlCmd.Request = mGetByte1(ep0_data);
1635 ControlCmd.Value = mGetByte2(ep0_data) + (mGetByte3(ep0_data) << 8);
1637 //ep0_data = ZM_EP0_DATA_REG;
1638 ep0_data = USB_WORD_REG_READ(ZM_EP0_DATA_OFFSET);
1640 ControlCmd.Index = mGetByte0(ep0_data) + (mGetByte1(ep0_data) << 8);
1641 ControlCmd.Length = mGetByte2(ep0_data) + (mGetByte3(ep0_data) << 8);
1644 if (mDEV_REQ_REQ_TYPE() == (cUSB_REQTYPE_STD << bmREQ_TYPE))
1645 { // standard command
1646 //if (bStandardCommand() == FALSE)
1647 if (A_USB_STANDARD_CMD() == FALSE)
1649 eUsbCxFinishAction = ACT_STALL;
1652 else if (mDEV_REQ_REQ_TYPE() == (cUSB_REQTYPE_VENDOR << bmREQ_TYPE))
1659 // Invalid(bad) command, Return EP0_STALL flag
1660 A_PRINTF("request not support.. stall", __FUNCTION__);
1661 eUsbCxFinishAction = ACT_STALL;
1664 //zcPrint._printf("\t<--- %s --->\n\r", __FUNCTION__);
1671 LOCAL void cFUSB200Init(void)
1673 /* Clear USB reset interrupt */
1674 USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&0xfd));
1676 // Disable all fifo interrupt
1677 /* Clear all USB OUT FIFO */
1678 USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_1_OFFSET, 0xff);
1679 USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_2_OFFSET, 0xff);
1680 USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_3_OFFSET, 0xff);
1682 /* Clear all USB IN FIFO */
1683 USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_5_OFFSET, 0xff);
1684 USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, 0xff);
1687 //ZM_MAIN_CTRL_REG = 0x10;
1688 //ZM_MAIN_CTRL_REG &= ~0x10;
1691 USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, 0x10);
1692 USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, 0x0);
1695 USB_BYTE_REG_WRITE(ZM_TEST_OFFSET, BIT0); // will be cleared after one cycle.
1696 USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_0_OFFSET, 0); //BIT6); // Mask out INT status
1698 // reset the specific mode
1699 USB_BYTE_REG_WRITE(ZM_VDR_SPECIFIC_MODE_OFFSET, 0x0);
1701 // reset the zero-length fifo indication ? workaround...
1702 USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, 0x0);
1705 USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, (BIT5|BIT2));
1707 USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_1_OFFSET, 0x0);
1708 USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_2_OFFSET, 0x0);
1709 USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_3_OFFSET, 0x0);
1711 // USB_WORD_REG_WRITE(0x104, 0x000000C0);
1716 LOCAL void _usbfifo_enable_event_isr(void)
1718 mUSB_STATUS_IN_INT_ENABLE();
1721 LOCAL void _usbfifo_init(USB_FIFO_CONFIG *pConfig)
1723 usbFifoConf.get_command_buf = pConfig->get_command_buf;
1724 usbFifoConf.recv_command = pConfig->recv_command;
1725 usbFifoConf.get_event_buf = pConfig->get_event_buf;
1726 usbFifoConf.send_event_done = pConfig->send_event_done;
1729 LOCAL void vUsb_Reg_Out(void)
1731 uint16_t usbfifolen;
1733 volatile uint32_t *regaddr; // = (volatile uint32_t *) ZM_CMD_BUFFER;
1738 //mUSB_REG_OUT_INT_DISABLE();
1740 buf = usbFifoConf.get_command_buf();
1742 if ( buf != NULL ) // copy free
1743 regaddr = (uint32_t *)buf->desc_list->buf_addr;
1747 // read fifo size of the current packet.
1748 usbfifolen = USB_BYTE_REG_READ(ZM_EP4_BYTE_COUNT_LOW_OFFSET);
1750 cmdLen = usbfifolen;
1753 usbfifolen = (usbfifolen >> 2) + 1;
1755 usbfifolen = usbfifolen >> 2;
1757 for(ii = 0; ii < usbfifolen; ii++)
1759 ep4_data = USB_WORD_REG_READ(ZM_EP4_DATA_OFFSET); // read fifo data out
1760 *regaddr = ep4_data;
1766 // zfUartSendStrAndHex((u8_t *) "cmdLen=", cmdLen);
1767 // zfMemoryCopyInWord(buf->desc_list->buf_addr, ZM_CMD_BUFFER, usbfifolen*4);
1768 buf->desc_list->next_desc = NULL;
1769 buf->desc_list->data_offset = 0;
1770 buf->desc_list->data_size = cmdLen;
1771 buf->desc_list->control = 0;
1772 buf->next_buf = NULL;
1773 buf->buf_length = cmdLen;
1775 usbFifoConf.recv_command(buf);
1779 // we might get no command buffer here?
1780 // but if we return here, the ep4 fifo will be lock out,
1781 // so that we still read them out but just drop it ?
1782 for(ii = 0; ii < usbfifolen; ii++)
1784 ep4_data = USB_WORD_REG_READ(ZM_EP4_DATA_OFFSET); // read fifo data out
1788 //mUSB_STATUS_IN_INT_ENABLE();
1792 LOCAL void vUsb_Status_In(void)
1796 volatile u32_t *regaddr;
1798 VBUF *evntbuf = NULL;
1800 //regaddr = (volatile uint32_t *) ZM_CMD_BUFFER;
1802 //mUSB_STATUS_IN_INT_DISABLE();
1804 evntbuf = usbFifoConf.get_event_buf();
1805 if ( evntbuf != NULL )
1807 //zfUartSendStr((u8_t *) "#G1\r\n");
1808 // A_PRINTF("#G1\n\r");
1809 regaddr = VBUF_GET_DATA_ADDR(evntbuf);
1810 RegBufLen = evntbuf->buf_length;
1811 // A_PRINTF("RegBufLen=%d\n\r", RegBufLen);
1812 //zfUartSendStrAndHex((u8_t *) "RegBufLen=", RegBufLen);
1816 mUSB_STATUS_IN_INT_DISABLE();
1817 // A_PRINTF("#G2\n\r");
1822 for(count = 0; count < (RegBufLen / 4); count++)
1824 //zfUartSendStrAndHex((u8_t *) "data=", *regaddr);
1825 USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, *regaddr);
1829 remainder = RegBufLen % 4;
1836 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x7);
1839 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x3);
1842 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1);
1846 USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, *regaddr);
1849 // Restore CBus FIFO size to word size
1850 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF);
1852 mUSB_EP3_XFER_DONE();
1854 if ( evntbuf != NULL )
1856 usbFifoConf.send_event_done(evntbuf);
1860 //mUSB_REG_OUT_INT_ENABLE();
1863 /////////////////////////////////////////////////////////
1864 /***********************************************************************/
1867 // 1. Reset all the USB FIFO used for WLAN
1870 /***********************************************************************/
1871 LOCAL void zfResetUSBFIFO(void)
1873 A_PUTS("zfResetUSBFIFO\n\r");
1877 /***********************************************************************/
1880 // 1. Function to turn off ADDA/RF power, PLL
1883 /***********************************************************************/
1884 LOCAL void zfTurnOffPower(void)
1886 A_PUTS("zfTurnOffPower\n\r");
1887 #if defined(MAGPIE_ASIC)
1890 * 2. turn off CPU PLL
1891 * 3. turn off ETH PLL
1892 * 4. disable ETH PLL bypass and update
1893 * 5. set SUSPEND_ENABLE
1896 /*HAL_WORD_REG_WRITE(MAGPIE_REG_USB_DIVIDE_ADDR,((0x8<<8)|0x8)); */
1897 /* 1. */ HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_BYPASS_ADDR,
1898 (HAL_WORD_REG_READ(MAGPIE_REG_CPU_PLL_BYPASS_ADDR)|(BIT0|BIT4)));
1899 A_DELAY_USECS(100); // wait for stable
1901 /* 2. */ HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_ADDR,
1902 (HAL_WORD_REG_READ(MAGPIE_REG_CPU_PLL_ADDR)|(BIT16)));
1904 /* 3. */ HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_ADDR,
1905 (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_ADDR)|(BIT16)));
1907 /* 4. */ HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_BYPASS_ADDR,
1908 (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_BYPASS_ADDR)|(BIT16|BIT0)));
1910 /* 5. */ HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR,
1911 (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)|(BIT0)));
1917 LOCAL void zfGenWatchDogEvent(void)
1919 uint32_t event= 0x0000C600;
1921 mUSB_STATUS_IN_INT_DISABLE();
1923 //ZM_CBUS_FIFO_SIZE_REG = 0xf;
1924 USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x0f);
1926 //ZM_EP3_DATA_REG = event;
1927 USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, event);
1929 mUSB_EP3_XFER_DONE();
1932 LOCAL void zfJumpToBootCode(void)
1934 extern int _start(void);
1936 /* Jump to the boot code */
1940 LOCAL void _usb_rom_task(void)
1942 register uint8_t usb_interrupt_level1;
1943 register uint8_t usb_interrupt_level2;
1944 register uint8_t usb_ctrl_err_indication;
1946 usb_interrupt_level1 = USB_BYTE_REG_READ(ZM_INTR_GROUP_OFFSET);
1948 if (usb_interrupt_level1 & BIT6)
1951 A_PRINTF("Generate Event\n");
1954 if (usb_interrupt_level1 & BIT0) //Group Byte 0
1956 usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET);
1958 // refer to FUSB200, p 48, offset:21H, bit7 description, should clear the command abort interrupt first!?
1959 if (usb_interrupt_level2 & BIT7)
1961 USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_0_OFFSET, (USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET)& ~BIT7));
1964 if (usb_interrupt_level2 & BIT1)
1966 A_PRINTF("![USB] ep0 IN in \n\r");
1967 A_USB_EP0_TX(); // USB EP0 tx interrupt
1969 if (usb_interrupt_level2 & BIT2)
1971 //A_PRINTF("![USB] ep0 OUT in\n\r");
1972 A_USB_EP0_RX(); // USB EP0 rx interrupt
1974 if (usb_interrupt_level2 & BIT0)
1976 //A_PRINTF("![USB] ep0 SETUP in\n\r");
1980 if (eUsbCxFinishAction == ACT_STALL)
1982 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04);
1983 // A_PRINTF("![USB] ZM_CX_CONFIG_STATUS_REG = 0x04\n\r");
1985 else if (eUsbCxFinishAction == ACT_DONE)
1987 // set CX_DONE to indicate the transmistion of control frame
1988 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01);
1990 eUsbCxFinishAction = ACT_IDLE;
1993 if (usb_interrupt_level1 & BIT7) //Group Byte 7
1995 //usb_interrupt_level2 = ZM_INTR_SOURCE_7_REG;
1996 usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET);
1998 if (usb_interrupt_level2 & BIT1)
2002 if (usb_interrupt_level2 & BIT2)
2006 if (usb_interrupt_level2 & BIT3)
2015 LOCAL void _usb_fw_task(void)
2017 register uint8_t usb_interrupt_level1;
2018 register uint8_t usb_interrupt_level2;
2019 register uint8_t usb_ctrl_err_indication;
2021 usb_interrupt_level1 = USB_BYTE_REG_READ(ZM_INTR_GROUP_OFFSET);
2023 #if 0 // these endpoints are handled by DMA
2024 if (usb_interrupt_level1 & BIT5) //Group Byte 5
2029 if (usb_interrupt_level1 & BIT4)
2031 usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_4_OFFSET);
2032 if( usb_interrupt_level2 & BIT6)
2033 A_USB_REG_OUT();//vUsb_Reg_Out();
2036 if (usb_interrupt_level1 & BIT6)
2038 //zfGenWatchDogEvent();
2039 usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_6_OFFSET);
2040 if( usb_interrupt_level2 & BIT6)
2041 A_USB_STATUS_IN();//vUsb_Status_In();
2044 if (usb_interrupt_level1 & BIT0) //Group Byte 0
2046 //usb_interrupt_level2 = ZM_INTR_SOURCE_0_REG;
2047 usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET);
2049 // refer to FUSB200, p 48, offset:21H, bit7 description, should clear the command abort interrupt first!?
2050 if (usb_interrupt_level2 & BIT7)
2052 //ZM_INTR_SOURCE_0_REG &= 0x7f; // Handle command abort
2053 USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_0_OFFSET, (USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET)& ~BIT7));
2054 A_PRINTF("![SOURCE_0] bit7 on\n\r");
2057 if (usb_interrupt_level2 & BIT1)
2059 //A_PRINTF("![USB] ep0 IN in \n\r");
2060 A_USB_EP0_TX(); // USB EP0 tx interrupt
2062 if (usb_interrupt_level2 & BIT2)
2064 //A_PRINTF("![USB] ep0 OUT in\n\r");
2065 A_USB_EP0_RX(); // USB EP0 rx interrupt
2067 if (usb_interrupt_level2 & BIT0)
2069 //A_PRINTF("![USB] ep0 SETUP in\n\r");
2071 //vWriteUSBFakeData();
2073 // else if (usb_interrupt_level2 & BIT3)
2074 if (usb_interrupt_level2 & BIT3)
2077 // A_PRINTF("![SOURCE_0] ep0 CMD_END\n\r");
2079 if (usb_interrupt_level2 & BIT4)
2082 // A_PRINTF("![SOURCE_0] ep0 CMD_FAIL\n\r");
2084 if (eUsbCxFinishAction == ACT_STALL)
2086 // set CX_STL to stall Endpoint0 & will also clear FIFO0
2087 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04);
2088 // A_PRINTF("![USB] ZM_CX_CONFIG_STATUS_REG = 0x04\n\r");
2090 else if (eUsbCxFinishAction == ACT_DONE)
2092 // set CX_DONE to indicate the transmistion of control frame
2093 USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01);
2095 eUsbCxFinishAction = ACT_IDLE;
2098 if (usb_interrupt_level1 & BIT7) //Group Byte 7
2100 //usb_interrupt_level2 = ZM_INTR_SOURCE_7_REG;
2101 usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET);
2104 if (usb_interrupt_level2 & BIT7)
2106 vUsb_Data_Out0Byte();
2107 // A_PRINTF("![SOURCE_7] bit7 on, clear it\n\r");
2109 if (usb_interrupt_level2 & BIT6)
2111 vUsb_Data_In0Byte();
2112 // A_PRINTF("![SOURCE_7] bit6 on, clear it\n\r");
2116 if (usb_interrupt_level2 & BIT1)
2119 //USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_REG, (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~0x2));
2120 A_PRINTF("!USB reset\n\r");
2121 // A_PRINTF("![0x1012c]: %\n\r", USB_WORD_REG_READ(0x12c));
2123 if (usb_interrupt_level2 & BIT2)
2125 // TBD: the suspend resume code should put here, Ryan, 07/18
2127 // issue, jump back to rom code and what peripherals should we reset here?
2130 /* Set GO_TO_SUSPEND bit to USB main control register */
2132 A_PRINTF("!USB suspend\n\r");
2134 // keep the record of suspend
2135 #if defined(PROJECT_MAGPIE)
2136 *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR) = SUS_MAGIC_PATTERN;
2137 #elif defined(PROJECT_K2)
2138 HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, SUS_MAGIC_PATTERN);
2139 #endif /* #if defined(PROJECT_MAGPIE) */
2141 /* Reset USB FIFO */
2144 /* Turn off power */
2147 // DON'T restart when not in ASIC
2148 #if defined(MAGPIE_ASIC)
2149 /* Jump to boot code */
2154 if (usb_interrupt_level2 & BIT3)
2157 A_PRINTF("!USB resume\n\r");
2165 void _usb_init(void)
2169 // u16TxRxCounter = 0;
2170 // eUsbCxCommand = CMD_VOID;
2171 // u8UsbConfigValue = 0;
2172 u8UsbInterfaceValue = 0;
2173 u8UsbInterfaceAlternateSetting = 0;
2174 // bUsbEP0HaltSt = FALSE;
2175 // u16FirmwareComplete = 0;
2176 // eUsbCxFinishAction = ACT_IDLE;
2177 UsbStatus[0] = !fBUS_POWER;
2184 //ZM_PHY_TEST_SELECT_REG = 0; // Plug In
2185 USB_BYTE_REG_WRITE(ZM_PHY_TEST_SELECT_OFFSET, 0x0);
2187 // reset the address, just in case...
2188 //USB_BYTE_REG_WRITE(ZM_DEVICE_ADDRESS_OFFSET, 0x0);
2194 #if defined(PROJECT_MAGPIE)
2196 /* - spec, ch11, reset
2198 * 1. turn on ETH PLL and set ETH PLL to 384Mhz
2199 * 2. set "USB_DMA, USB_CORE, ETH_PLL, CPU_PLL, USB_POR reset" bit
2200 * 3. clear "ETH_PLL, CPU_PLL" reset bit
2201 * 4. set USB divider to 48, 192/16=12
2202 * 5. disable ETH PLL bypass
2204 * 7. clear USB_DMA, USB_CORE
2205 * 8. enable USB_AHB_ARB
2207 * note: don't know why bit3, bit4 should deassert? here especially bit4?
2208 * since if we don't deassert this, clk won't come up
2211 #if defined(MAGPIE_ASIC)
2212 #define RST_USB_COLD_INIT() \
2214 /********* number of PLLDIV_LOW and PLLDIV_HIGH ***********/ \
2215 /*HAL_WORD_REG_WRITE(MAGPIE_REG_USB_DIVIDE_ADDR,((0x8<<8)|0x8)); */ \
2216 /* 1. */ HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_ADDR, 0x305); \
2217 /* 2. */ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, \
2218 (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)|(BIT0|BIT1|BIT2|BIT3|BIT4))); \
2219 /* 3. */ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, \
2220 (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)&(~(BIT1|BIT2)))); \
2221 /* 4. */ HAL_WORD_REG_WRITE(MAGPIE_REG_USB_DIVIDE_ADDR, 0x1010); \
2222 /* 5. */ HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_BYPASS_ADDR, 0x0); \
2223 A_DELAY_USECS(100); /* wait for clock source stable */ \
2224 /* 6. */ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, \
2225 (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)&(~(BIT0)))); \
2226 /* 7. */ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, \
2227 (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)&(~(BIT3|BIT4)))); \
2228 /* 8. */ HAL_WORD_REG_WRITE(MAGPIE_REG_AHB_ARB_ADDR, \
2229 (HAL_WORD_REG_READ(MAGPIE_REG_AHB_ARB_ADDR)|BIT2)); \
2230 /* HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, ); */ \
2231 /* HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)|((BIT0|BIT3|BIT4)))); */ \
2232 /* HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)&(~(BIT0|BIT3|BIT4)))); */ \
2235 /* - back from suspend
2237 * 1. turn on ETH PLL , 0x5600c, ~bit0
2238 * 2. clear USB SUSPEND_ENABLE, 0x56030, ~bit0
2241 #define RST_USB_SUSP_INIT() \
2243 /* 1. */ HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_BYPASS_ADDR, \
2244 (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_BYPASS_ADDR)&(~BIT0))); \
2245 /* 2. */ HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR, \
2246 (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)&(~BIT0))); \
2249 /* - back from watchdog
2252 #define RST_USB_WDT_INIT()
2255 #elif defined(MAGPIE_FPGA)
2256 // fpag don't have PLL, skip 1~5
2257 #define RST_USB_COLD_INIT() \
2259 /* 6. */ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, \
2260 (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)&(~(BIT0)))); \
2261 /* 7. */ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, \
2262 (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)&(~(BIT3|BIT4)))); \
2263 /* 8. */ HAL_WORD_REG_WRITE(MAGPIE_REG_AHB_ARB_ADDR, \
2264 (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)|BIT2)); \
2265 A_DELAY_USECS(100); /* wait for clock source stable */ \
2268 /* - back from suspend
2271 #define RST_USB_SUSP_INIT()
2273 /* - back from watchdog
2276 #define RST_USB_WDT_INIT()
2282 #elif defined(PROJECT_K2)
2283 #define RST_USB_INIT() \
2285 HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, HAL_WORD_REG_READ(MAGPIE_REG_RST_PWDN_CTRL_ADDR)|BIT12); \
2286 A_DELAY_USECS(10); \
2287 HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, HAL_WORD_REG_READ(MAGPIE_REG_RST_PWDN_CTRL_ADDR)&(~BIT12)); \
2291 @ToDo: this is used to enable usb access internal memory, dma need this
2292 HAL_WORD_REG_WRITE(MAGPIE_REG_AHB_ARB_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_AHB_ARB_ADDR)&(~(BIT2)))); \
2293 A_DELAY_USECS(20); \
2294 HAL_WORD_REG_WRITE(MAGPIE_REG_AHB_ARB_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_AHB_ARB_ADDR)|(BIT2))); \
2295 A_DELAY_USECS(20); \
2299 LOCAL void _usb_clk_init(void)
2301 T_BOOT_TYPE mBootMode;
2303 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x31;
2305 mBootMode = A_WDT_LASTBOOT();
2307 #if defined(PROJECT_MAGPIE)
2309 if( mBootMode == ENUM_WDT_BOOT )
2313 else if ( mBootMode == ENUM_SUSP_BOOT )
2315 RST_USB_SUSP_INIT();
2319 RST_USB_COLD_INIT();
2322 #elif defined(PROJECT_K2)
2323 if( mBootMode == ENUM_COLD_BOOT )
2329 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x32;
2331 //A_DELAY_USECS(300); // delay 300 micro seconds, wait for clock stable!
2335 void _usb_init(void)
2339 // A_PUTS("\n - _usb_init - \n\r");
2341 #if defined(PROJECT_MAGPIE)
2342 //if ( *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR) == WDT_MAGIC_PATTERN || *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR) == SUS_MAGIC_PATTERN )
2343 if( A_WDT_LASTBOOT()!= ENUM_COLD_BOOT)
2344 #elif defined(PROJECT_K2)
2345 if (HAL_WORD_REG_READ(MAGPIE_REG_RST_STATUS_ADDR) == WDT_MAGIC_PATTERN || HAL_WORD_REG_READ(MAGPIE_REG_RST_STATUS_ADDR) == SUS_MAGIC_PATTERN)
2346 #endif /* #if defined(PROJECT_MAGPIE) */
2351 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x30;
2353 // u16TxRxCounter = 0;
2354 // eUsbCxCommand = CMD_VOID;
2355 // u8UsbConfigValue = 0;
2356 u8UsbInterfaceValue = 0;
2357 u8UsbInterfaceAlternateSetting = 0;
2358 // bUsbEP0HaltSt = FALSE;
2359 // u16FirmwareComplete = 0;
2360 // eUsbCxFinishAction = ACT_IDLE;
2361 UsbStatus[0] = !fBUS_POWER;
2365 * move the setting to A_USB_CLK_INIT(), so that we could patch these things
2372 #if defined(PROJECT_MAGPIE)
2374 //#if defined(MAGPIE_ASIC)
2376 // @Bug 36267 - wdt reset or other reset will reset usb phy, we need to init again here
2377 // - this won't work at FPGA, skip this checking if build for FPGA
2379 // @Bug 36947 - L3 fpga's reset behavior of usb is not as what I expect!, need to confirm
2381 // ToBeNote: if (Bug36947), skip the checking and reset usb anyway, but will see the connection broken
2385 #elif defined(PROJECT_K2)
2388 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x31;
2391 #endif /* #if defined(PROJECT_MAGPIE) */
2395 A_DELAY_USECS(300); // delay 300 usecs, wait for clock stable!
2400 * wait for USBSOC_HCLK_RDY tight high, indicate the 30Mhz is ready for use
2402 if(HAL_WORD_REG_READ(0x10128)& BIT8)
2405 //A_DELAY_USECS(200); // delay 200 micro seconds, wait for clock stable!
2408 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x33;
2409 A_PUTS("6. usb_hclk rdy\n\r");
2412 // @Bug 36267 - wdt reset or other reset will reset usb phy, we need to init again here
2414 // @Bug 36947 - L3 fpga's reset behavior of usb is not as what I expect!, need to confirm
2415 #if defined(PROJECT_MAGPIE)
2417 // in cold or suspend boot, we do reinit the USB_PHY, skip only when watchdog start
2420 #if defined(MAGPIE_ASIC)
2423 #elif defined(PROJECT_K2)
2425 #endif /* #if defined(PROJECT_MAGPIE) */
2427 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x34;
2430 DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x35;
2431 //ZM_PHY_TEST_SELECT_REG = 0; // Plug In
2432 USB_BYTE_REG_WRITE(ZM_PHY_TEST_SELECT_OFFSET, 0x0);
2434 // reset the address, just in case...
2435 //USB_BYTE_REG_WRITE(ZM_DEVICE_ADDRESS_OFFSET, 0x0);
2438 /* If watchdog reset happens, target needs to send a message to host through EP3 */
2439 if ( A_WDT_LASTBOOT() == ENUM_WDT_BOOT )
2440 mUSB_STATUS_IN_INT_ENABLE();
2442 mUSB_STATUS_IN_INT_DISABLE();
2448 ////////////////////////////////////////////////////////
2449 void usbfifo_module_install(struct usbfifo_api *apis)
2452 apis->_init = _usbfifo_init;
2453 apis->_enable_event_isr = _usbfifo_enable_event_isr;
2457 void cmnos_usb_module_install(struct usb_api *apis)
2459 apis->_usb_init = _usb_init;
2460 apis->_usb_rom_task = _usb_rom_task;
2461 apis->_usb_fw_task = _usb_fw_task;
2462 apis->_usb_init_phy = cFUSB200Init;
2464 apis->_usb_ep0_setup = vUsb_ep0setup;
2465 apis->_usb_ep0_tx_data = vUsbEP0TxData;
2466 apis->_usb_ep0_rx_data = vUsbEP0RxData;
2468 apis->_usb_get_configuration = bGet_configuration;
2469 apis->_usb_set_configuration = bSet_configuration;
2471 apis->_usb_get_interface = bGet_interface;
2472 apis->_usb_set_interface = bSet_interface;
2474 apis->_usb_standard_cmd = bStandardCommand;
2475 apis->_usb_vendor_cmd = VendorCommand;
2477 apis->_usb_reset_fifo= zfResetUSBFIFO;
2478 apis->_usb_power_off = zfTurnOffPower;
2479 apis->_usb_gen_wdt = zfGenWatchDogEvent;
2480 apis->_usb_jump_boot = zfJumpToBootCode;
2482 apis->_usb_get_descriptor = bGet_descriptor;
2483 apis->_usb_set_address = bSet_address;
2484 apis->_usb_set_feature = bSet_feature;
2485 apis->_usb_clr_feature = bClear_feature;
2487 apis->_usb_get_status = bGet_status;
2488 apis->_usb_setup_desc = vUsb_SetupDescriptor;
2490 apis->_usb_reg_out = vUsb_Reg_Out;
2491 apis->_usb_status_in = vUsb_Status_In;
2493 apis->_usb_ep0_tx = vUsb_ep0tx;
2494 apis->_usb_ep0_rx = vUsb_ep0rx;
2496 apis->_usb_clk_init = _usb_clk_init;