3 * Texas Instruments AM35x "glue layer"
5 * Copyright (c) 2010, by Texas Instruments
7 * Based on the DA8xx "glue layer" code.
8 * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
10 * This file is part of the Inventra Controller Driver for Linux.
12 * The Inventra Controller Driver for Linux is free software; you
13 * can redistribute it and/or modify it under the terms of the GNU
14 * General Public License version 2 as published by the Free Software
17 * The Inventra Controller Driver for Linux is distributed in
18 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
19 * without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
21 * License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with The Inventra Controller Driver for Linux ; if not,
25 * write to the Free Software Foundation, Inc., 59 Temple Place,
26 * Suite 330, Boston, MA 02111-1307 USA
30 #include <linux/module.h>
31 #include <linux/clk.h>
32 #include <linux/err.h>
34 #include <linux/platform_device.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/usb/usb_phy_generic.h>
37 #include <linux/platform_data/usb-omap.h>
39 #include "musb_core.h"
42 * AM35x specific definitions
44 /* USB 2.0 OTG module registers */
45 #define USB_REVISION_REG 0x00
46 #define USB_CTRL_REG 0x04
47 #define USB_STAT_REG 0x08
48 #define USB_EMULATION_REG 0x0c
50 #define USB_AUTOREQ_REG 0x14
51 #define USB_SRP_FIX_TIME_REG 0x18
52 #define USB_TEARDOWN_REG 0x1c
53 #define EP_INTR_SRC_REG 0x20
54 #define EP_INTR_SRC_SET_REG 0x24
55 #define EP_INTR_SRC_CLEAR_REG 0x28
56 #define EP_INTR_MASK_REG 0x2c
57 #define EP_INTR_MASK_SET_REG 0x30
58 #define EP_INTR_MASK_CLEAR_REG 0x34
59 #define EP_INTR_SRC_MASKED_REG 0x38
60 #define CORE_INTR_SRC_REG 0x40
61 #define CORE_INTR_SRC_SET_REG 0x44
62 #define CORE_INTR_SRC_CLEAR_REG 0x48
63 #define CORE_INTR_MASK_REG 0x4c
64 #define CORE_INTR_MASK_SET_REG 0x50
65 #define CORE_INTR_MASK_CLEAR_REG 0x54
66 #define CORE_INTR_SRC_MASKED_REG 0x58
68 #define USB_END_OF_INTR_REG 0x60
70 /* Control register bits */
71 #define AM35X_SOFT_RESET_MASK 1
73 /* USB interrupt register bits */
74 #define AM35X_INTR_USB_SHIFT 16
75 #define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT)
76 #define AM35X_INTR_DRVVBUS 0x100
77 #define AM35X_INTR_RX_SHIFT 16
78 #define AM35X_INTR_TX_SHIFT 0
79 #define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */
80 #define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */
81 #define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
82 #define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
84 #define USB_MENTOR_CORE_OFFSET 0x400
88 struct platform_device *musb;
89 struct platform_device *phy;
95 * am35x_musb_enable - enable interrupts
97 static void am35x_musb_enable(struct musb *musb)
99 void __iomem *reg_base = musb->ctrl_base;
102 /* Workaround: setup IRQs through both register sets. */
103 epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
104 ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
106 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
107 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
109 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
110 musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
111 AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
115 * am35x_musb_disable - disable HDRC and flush interrupts
117 static void am35x_musb_disable(struct musb *musb)
119 void __iomem *reg_base = musb->ctrl_base;
121 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
122 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
123 AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
124 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
127 #define portstate(stmt) stmt
129 static void am35x_musb_set_vbus(struct musb *musb, int is_on)
131 WARN_ON(is_on && is_peripheral_active(musb));
134 #define POLL_SECONDS 2
136 static struct timer_list otg_workaround;
138 static void otg_timer(unsigned long _musb)
140 struct musb *musb = (void *)_musb;
141 void __iomem *mregs = musb->mregs;
146 * We poll because AM35x's won't expose several OTG-critical
147 * status change events (from the transceiver) otherwise.
149 devctl = musb_readb(mregs, MUSB_DEVCTL);
150 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
151 usb_otg_state_string(musb->xceiv->otg->state));
153 spin_lock_irqsave(&musb->lock, flags);
154 switch (musb->xceiv->otg->state) {
155 case OTG_STATE_A_WAIT_BCON:
156 devctl &= ~MUSB_DEVCTL_SESSION;
157 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
159 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
160 if (devctl & MUSB_DEVCTL_BDEVICE) {
161 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
164 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
168 case OTG_STATE_A_WAIT_VFALL:
169 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
170 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
171 MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
173 case OTG_STATE_B_IDLE:
174 devctl = musb_readb(mregs, MUSB_DEVCTL);
175 if (devctl & MUSB_DEVCTL_BDEVICE)
176 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
178 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
183 spin_unlock_irqrestore(&musb->lock, flags);
186 static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
188 static unsigned long last_timer;
191 timeout = jiffies + msecs_to_jiffies(3);
193 /* Never idle if active, or when VBUS timeout is not set as host */
194 if (musb->is_active || (musb->a_wait_bcon == 0 &&
195 musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)) {
196 dev_dbg(musb->controller, "%s active, deleting timer\n",
197 usb_otg_state_string(musb->xceiv->otg->state));
198 del_timer(&otg_workaround);
199 last_timer = jiffies;
203 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
204 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
207 last_timer = timeout;
209 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
210 usb_otg_state_string(musb->xceiv->otg->state),
211 jiffies_to_msecs(timeout - jiffies));
212 mod_timer(&otg_workaround, timeout);
215 static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
217 struct musb *musb = hci;
218 void __iomem *reg_base = musb->ctrl_base;
219 struct device *dev = musb->controller;
220 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
221 struct omap_musb_board_data *data = plat->board_data;
222 struct usb_otg *otg = musb->xceiv->otg;
224 irqreturn_t ret = IRQ_NONE;
227 spin_lock_irqsave(&musb->lock, flags);
229 /* Get endpoint interrupts */
230 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
233 musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
236 (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
238 (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
241 /* Get usb core interrupts */
242 usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
243 if (!usbintr && !epintr)
247 musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
250 (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
253 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
254 * AM35x's missing ID change IRQ. We need an ID change IRQ to
255 * switch appropriately between halves of the OTG state machine.
256 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
257 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
258 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
260 if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
261 int drvvbus = musb_readl(reg_base, USB_STAT_REG);
262 void __iomem *mregs = musb->mregs;
263 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
266 err = musb->int_usb & MUSB_INTR_VBUSERROR;
269 * The Mentor core doesn't debounce VBUS as needed
270 * to cope with device connect current spikes. This
271 * means it's not uncommon for bus-powered devices
272 * to get VBUS errors during enumeration.
274 * This is a workaround, but newer RTL from Mentor
275 * seems to allow a better one: "re"-starting sessions
276 * without waiting for VBUS to stop registering in
279 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
280 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
281 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
282 WARNING("VBUS error workaround (delay coming)\n");
283 } else if (drvvbus) {
286 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
287 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
288 del_timer(&otg_workaround);
293 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
294 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
297 /* NOTE: this must complete power-on within 100 ms. */
298 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
299 drvvbus ? "on" : "off",
300 usb_otg_state_string(musb->xceiv->otg->state),
306 /* Drop spurious RX and TX if device is disconnected */
307 if (musb->int_usb & MUSB_INTR_DISCONNECT) {
312 if (musb->int_tx || musb->int_rx || musb->int_usb)
313 ret |= musb_interrupt(musb);
316 /* EOI needs to be written for the IRQ to be re-asserted. */
317 if (ret == IRQ_HANDLED || epintr || usbintr) {
318 /* clear level interrupt */
322 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
325 /* Poll for ID change */
326 if (musb->xceiv->otg->state == OTG_STATE_B_IDLE)
327 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
329 spin_unlock_irqrestore(&musb->lock, flags);
334 static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
336 struct device *dev = musb->controller;
337 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
338 struct omap_musb_board_data *data = plat->board_data;
342 data->set_mode(musb_mode);
349 static int am35x_musb_init(struct musb *musb)
351 struct device *dev = musb->controller;
352 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
353 struct omap_musb_board_data *data = plat->board_data;
354 void __iomem *reg_base = musb->ctrl_base;
357 musb->mregs += USB_MENTOR_CORE_OFFSET;
359 /* Returns zero if e.g. not clocked */
360 rev = musb_readl(reg_base, USB_REVISION_REG);
364 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
365 if (IS_ERR_OR_NULL(musb->xceiv))
366 return -EPROBE_DEFER;
368 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
374 /* Reset the controller */
375 musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
377 /* Start the on-chip PHY and its PLL. */
378 if (data->set_phy_power)
379 data->set_phy_power(1);
383 musb->isr = am35x_musb_interrupt;
385 /* clear level interrupt */
392 static int am35x_musb_exit(struct musb *musb)
394 struct device *dev = musb->controller;
395 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
396 struct omap_musb_board_data *data = plat->board_data;
398 del_timer_sync(&otg_workaround);
400 /* Shutdown the on-chip PHY and its PLL. */
401 if (data->set_phy_power)
402 data->set_phy_power(0);
404 usb_put_phy(musb->xceiv);
409 /* AM35x supports only 32bit read operation */
410 static void am35x_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
412 void __iomem *fifo = hw_ep->fifo;
416 /* Read for 32bit-aligned destination address */
417 if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
418 readsl(fifo, dst, len >> 2);
423 * Now read the remaining 1 to 3 byte or complete length if
427 for (i = 0; i < (len >> 2); i++) {
428 *(u32 *) dst = musb_readl(fifo, 0);
434 val = musb_readl(fifo, 0);
435 memcpy(dst, &val, len);
439 static const struct musb_platform_ops am35x_ops = {
440 .quirks = MUSB_DMA_INVENTRA | MUSB_INDEXED_EP,
441 .init = am35x_musb_init,
442 .exit = am35x_musb_exit,
444 .read_fifo = am35x_read_fifo,
445 #ifdef CONFIG_USB_INVENTRA_DMA
446 .dma_init = musbhs_dma_controller_create,
447 .dma_exit = musbhs_dma_controller_destroy,
449 .enable = am35x_musb_enable,
450 .disable = am35x_musb_disable,
452 .set_mode = am35x_musb_set_mode,
453 .try_idle = am35x_musb_try_idle,
455 .set_vbus = am35x_musb_set_vbus,
458 static const struct platform_device_info am35x_dev_info = {
460 .id = PLATFORM_DEVID_AUTO,
461 .dma_mask = DMA_BIT_MASK(32),
464 static int am35x_probe(struct platform_device *pdev)
466 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
467 struct platform_device *musb;
468 struct am35x_glue *glue;
469 struct platform_device_info pinfo;
475 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
479 phy_clk = clk_get(&pdev->dev, "fck");
480 if (IS_ERR(phy_clk)) {
481 dev_err(&pdev->dev, "failed to get PHY clock\n");
482 ret = PTR_ERR(phy_clk);
486 clk = clk_get(&pdev->dev, "ick");
488 dev_err(&pdev->dev, "failed to get clock\n");
493 ret = clk_enable(phy_clk);
495 dev_err(&pdev->dev, "failed to enable PHY clock\n");
499 ret = clk_enable(clk);
501 dev_err(&pdev->dev, "failed to enable clock\n");
505 glue->dev = &pdev->dev;
506 glue->phy_clk = phy_clk;
509 pdata->platform_ops = &am35x_ops;
511 glue->phy = usb_phy_generic_register();
512 if (IS_ERR(glue->phy)) {
513 ret = PTR_ERR(glue->phy);
516 platform_set_drvdata(pdev, glue);
518 pinfo = am35x_dev_info;
519 pinfo.parent = &pdev->dev;
520 pinfo.res = pdev->resource;
521 pinfo.num_res = pdev->num_resources;
523 pinfo.size_data = sizeof(*pdata);
525 glue->musb = musb = platform_device_register_full(&pinfo);
528 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
535 usb_phy_generic_unregister(glue->phy);
541 clk_disable(phy_clk);
556 static int am35x_remove(struct platform_device *pdev)
558 struct am35x_glue *glue = platform_get_drvdata(pdev);
560 platform_device_unregister(glue->musb);
561 usb_phy_generic_unregister(glue->phy);
562 clk_disable(glue->clk);
563 clk_disable(glue->phy_clk);
565 clk_put(glue->phy_clk);
571 #ifdef CONFIG_PM_SLEEP
572 static int am35x_suspend(struct device *dev)
574 struct am35x_glue *glue = dev_get_drvdata(dev);
575 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
576 struct omap_musb_board_data *data = plat->board_data;
578 /* Shutdown the on-chip PHY and its PLL. */
579 if (data->set_phy_power)
580 data->set_phy_power(0);
582 clk_disable(glue->phy_clk);
583 clk_disable(glue->clk);
588 static int am35x_resume(struct device *dev)
590 struct am35x_glue *glue = dev_get_drvdata(dev);
591 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
592 struct omap_musb_board_data *data = plat->board_data;
595 /* Start the on-chip PHY and its PLL. */
596 if (data->set_phy_power)
597 data->set_phy_power(1);
599 ret = clk_enable(glue->phy_clk);
601 dev_err(dev, "failed to enable PHY clock\n");
605 ret = clk_enable(glue->clk);
607 dev_err(dev, "failed to enable clock\n");
615 static SIMPLE_DEV_PM_OPS(am35x_pm_ops, am35x_suspend, am35x_resume);
617 static struct platform_driver am35x_driver = {
618 .probe = am35x_probe,
619 .remove = am35x_remove,
621 .name = "musb-am35x",
626 MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
627 MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
628 MODULE_LICENSE("GPL v2");
629 module_platform_driver(am35x_driver);