2 * hcd.h - DesignWare HS OTG Controller host-mode declarations
4 * Copyright (C) 2004-2013 Synopsys, Inc.
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36 #ifndef __DWC2_HCD_H__
37 #define __DWC2_HCD_H__
40 * This file contains the structures, constants, and interfaces for the
41 * Host Contoller Driver (HCD)
43 * The Host Controller Driver (HCD) is responsible for translating requests
44 * from the USB Driver into the appropriate actions on the DWC_otg controller.
45 * It isolates the USBD from the specifics of the controller by providing an
52 * struct dwc2_host_chan - Software host channel descriptor
54 * @hc_num: Host channel number, used for register address lookup
55 * @dev_addr: Address of the device
56 * @ep_num: Endpoint of the device
57 * @ep_is_in: Endpoint direction
58 * @speed: Device speed. One of the following values:
62 * @ep_type: Endpoint type. One of the following values:
63 * - USB_ENDPOINT_XFER_CONTROL: 0
64 * - USB_ENDPOINT_XFER_ISOC: 1
65 * - USB_ENDPOINT_XFER_BULK: 2
66 * - USB_ENDPOINT_XFER_INTR: 3
67 * @max_packet: Max packet size in bytes
68 * @data_pid_start: PID for initial transaction.
72 * 3: MDATA (non-Control EP),
74 * @multi_count: Number of additional periodic transactions per
76 * @xfer_buf: Pointer to current transfer buffer position
77 * @xfer_dma: DMA address of xfer_buf
78 * @align_buf: In Buffer DMA mode this will be used if xfer_buf is not
80 * @xfer_len: Total number of bytes to transfer
81 * @xfer_count: Number of bytes transferred so far
82 * @start_pkt_count: Packet count at start of transfer
83 * @xfer_started: True if the transfer has been started
84 * @ping: True if a PING request should be issued on this channel
85 * @error_state: True if the error count for this transaction is non-zero
86 * @halt_on_queue: True if this channel should be halted the next time a
87 * request is queued for the channel. This is necessary in
88 * slave mode if no request queue space is available when
89 * an attempt is made to halt the channel.
90 * @halt_pending: True if the host channel has been halted, but the core
91 * is not finished flushing queued requests
92 * @do_split: Enable split for the channel
93 * @complete_split: Enable complete split
94 * @hub_addr: Address of high speed hub for the split
95 * @hub_port: Port of the low/full speed device for the split
96 * @xact_pos: Split transaction position. One of the following values:
97 * - DWC2_HCSPLT_XACTPOS_MID
98 * - DWC2_HCSPLT_XACTPOS_BEGIN
99 * - DWC2_HCSPLT_XACTPOS_END
100 * - DWC2_HCSPLT_XACTPOS_ALL
101 * @requests: Number of requests issued for this channel since it was
102 * assigned to the current transfer (not counting PINGs)
103 * @schinfo: Scheduling micro-frame bitmap
104 * @ntd: Number of transfer descriptors for the transfer
105 * @halt_status: Reason for halting the host channel
106 * @hcint Contents of the HCINT register when the interrupt came
107 * @qh: QH for the transfer being processed by this channel
108 * @hc_list_entry: For linking to list of host channels
109 * @desc_list_addr: Current QH's descriptor list DMA address
110 * @desc_list_sz: Current QH's descriptor list size
111 * @split_order_list_entry: List entry for keeping track of the order of splits
113 * This structure represents the state of a single host channel when acting in
114 * host mode. It contains the data items needed to transfer packets to an
115 * endpoint via a host channel.
117 struct dwc2_host_chan {
125 unsigned max_packet:11;
126 unsigned data_pid_start:2;
127 #define DWC2_HC_PID_DATA0 TSIZ_SC_MC_PID_DATA0
128 #define DWC2_HC_PID_DATA2 TSIZ_SC_MC_PID_DATA2
129 #define DWC2_HC_PID_DATA1 TSIZ_SC_MC_PID_DATA1
130 #define DWC2_HC_PID_MDATA TSIZ_SC_MC_PID_MDATA
131 #define DWC2_HC_PID_SETUP TSIZ_SC_MC_PID_SETUP
133 unsigned multi_count:2;
137 dma_addr_t align_buf;
151 #define DWC2_HCSPLT_XACTPOS_MID HCSPLT_XACTPOS_MID
152 #define DWC2_HCSPLT_XACTPOS_END HCSPLT_XACTPOS_END
153 #define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN
154 #define DWC2_HCSPLT_XACTPOS_ALL HCSPLT_XACTPOS_ALL
159 enum dwc2_halt_status halt_status;
162 struct list_head hc_list_entry;
163 dma_addr_t desc_list_addr;
165 struct list_head split_order_list_entry;
168 struct dwc2_hcd_pipe_info {
177 struct dwc2_hcd_iso_packet_desc {
186 struct dwc2_hcd_urb {
188 struct dwc2_qtd *qtd;
192 dma_addr_t setup_dma;
200 struct dwc2_hcd_pipe_info pipe_info;
201 struct dwc2_hcd_iso_packet_desc iso_descs[0];
204 /* Phases for control transfers */
205 enum dwc2_control_phase {
211 /* Transaction types */
212 enum dwc2_transaction_type {
213 DWC2_TRANSACTION_NONE,
214 DWC2_TRANSACTION_PERIODIC,
215 DWC2_TRANSACTION_NON_PERIODIC,
216 DWC2_TRANSACTION_ALL,
219 /* The number of elements per LS bitmap (per port on multi_tt) */
220 #define DWC2_ELEMENTS_PER_LS_BITMAP DIV_ROUND_UP(DWC2_LS_SCHEDULE_SLICES, \
224 * struct dwc2_tt - dwc2 data associated with a usb_tt
226 * @refcount: Number of Queue Heads (QHs) holding a reference.
227 * @usb_tt: Pointer back to the official usb_tt.
228 * @periodic_bitmaps: Bitmap for which parts of the 1ms frame are accounted
229 * for already. Each is DWC2_ELEMENTS_PER_LS_BITMAP
230 * elements (so sizeof(long) times that in bytes).
232 * This structure is stored in the hcpriv of the official usb_tt.
236 struct usb_tt *usb_tt;
237 unsigned long periodic_bitmaps[];
241 * struct dwc2_hs_transfer_time - Info about a transfer on the high speed bus.
243 * @start_schedule_usecs: The start time on the main bus schedule. Note that
244 * the main bus schedule is tightly packed and this
245 * time should be interpreted as tightly packed (so
246 * uFrame 0 starts at 0 us, uFrame 1 starts at 100 us
247 * instead of 125 us).
248 * @duration_us: How long this transfer goes.
251 struct dwc2_hs_transfer_time {
252 u32 start_schedule_us;
257 * struct dwc2_qh - Software queue head structure
259 * @hsotg: The HCD state structure for the DWC OTG controller
260 * @ep_type: Endpoint type. One of the following values:
261 * - USB_ENDPOINT_XFER_CONTROL
262 * - USB_ENDPOINT_XFER_BULK
263 * - USB_ENDPOINT_XFER_INT
264 * - USB_ENDPOINT_XFER_ISOC
265 * @ep_is_in: Endpoint direction
266 * @maxp: Value from wMaxPacketSize field of Endpoint Descriptor
267 * @maxp_mult: Multiplier for maxp
268 * @dev_speed: Device speed. One of the following values:
272 * @data_toggle: Determines the PID of the next data packet for
273 * non-controltransfers. Ignored for control transfers.
274 * One of the following values:
275 * - DWC2_HC_PID_DATA0
276 * - DWC2_HC_PID_DATA1
277 * @ping_state: Ping state
278 * @do_split: Full/low speed endpoint on high-speed hub requires split
279 * @td_first: Index of first activated isochronous transfer descriptor
280 * @td_last: Index of last activated isochronous transfer descriptor
281 * @host_us: Bandwidth in microseconds per transfer as seen by host
282 * @device_us: Bandwidth in microseconds per transfer as seen by device
283 * @host_interval: Interval between transfers as seen by the host. If
284 * the host is high speed and the device is low speed this
285 * will be 8 times device interval.
286 * @device_interval: Interval between transfers as seen by the device.
288 * @next_active_frame: (Micro)frame _before_ we next need to put something on
289 * the bus. We'll move the qh to active here. If the
290 * host is in high speed mode this will be a uframe. If
291 * the host is in low speed mode this will be a full frame.
292 * @start_active_frame: If we are partway through a split transfer, this will be
293 * what next_active_frame was when we started. Otherwise
294 * it should always be the same as next_active_frame.
295 * @num_hs_transfers: Number of transfers in hs_transfers.
296 * Normally this is 1 but can be more than one for splits.
297 * Always >= 1 unless the host is in low/full speed mode.
298 * @hs_transfers: Transfers that are scheduled as seen by the high speed
299 * bus. Not used if host is in low or full speed mode (but
300 * note that it IS USED if the device is low or full speed
301 * as long as the HOST is in high speed mode).
302 * @ls_start_schedule_slice: Start time (in slices) on the low speed bus
303 * schedule that's being used by this device. This
304 * will be on the periodic_bitmap in a
305 * "struct dwc2_tt". Not used if this device is high
306 * speed. Note that this is in "schedule slice" which
308 * @ls_duration_us: Duration on the low speed bus schedule.
309 * @ntd: Actual number of transfer descriptors in a list
310 * @dw_align_buf: Used instead of original buffer if its physical address
311 * is not dword-aligned
312 * @dw_align_buf_dma: DMA address for dw_align_buf
313 * @qtd_list: List of QTDs for this QH
314 * @channel: Host channel currently processing transfers for this QH
315 * @qh_list_entry: Entry for QH in either the periodic or non-periodic
317 * @desc_list: List of transfer descriptors
318 * @desc_list_dma: Physical address of desc_list
319 * @desc_list_sz: Size of descriptors list
320 * @n_bytes: Xfer Bytes array. Each element corresponds to a transfer
321 * descriptor and indicates original XferSize value for the
323 * @unreserve_timer: Timer for releasing periodic reservation.
324 * @dwc2_tt: Pointer to our tt info (or NULL if no tt).
325 * @ttport: Port number within our tt.
326 * @tt_buffer_dirty True if clear_tt_buffer_complete is pending
327 * @unreserve_pending: True if we planned to unreserve but haven't yet.
328 * @schedule_low_speed: True if we have a low/full speed component (either the
329 * host is in low/full speed mode or do_split).
331 * A Queue Head (QH) holds the static characteristics of an endpoint and
332 * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
333 * be entered in either the non-periodic or periodic schedule.
336 struct dwc2_hsotg *hsotg;
351 u16 next_active_frame;
352 u16 start_active_frame;
353 s16 num_hs_transfers;
354 struct dwc2_hs_transfer_time hs_transfers[DWC2_HS_SCHEDULE_UFRAMES];
355 u32 ls_start_schedule_slice;
358 dma_addr_t dw_align_buf_dma;
359 struct list_head qtd_list;
360 struct dwc2_host_chan *channel;
361 struct list_head qh_list_entry;
362 struct dwc2_dma_desc *desc_list;
363 dma_addr_t desc_list_dma;
366 struct timer_list unreserve_timer;
367 struct dwc2_tt *dwc_tt;
369 unsigned tt_buffer_dirty:1;
370 unsigned unreserve_pending:1;
371 unsigned schedule_low_speed:1;
375 * struct dwc2_qtd - Software queue transfer descriptor (QTD)
377 * @control_phase: Current phase for control transfers (Setup, Data, or
379 * @in_process: Indicates if this QTD is currently processed by HW
380 * @data_toggle: Determines the PID of the next data packet for the
381 * data phase of control transfers. Ignored for other
382 * transfer types. One of the following values:
383 * - DWC2_HC_PID_DATA0
384 * - DWC2_HC_PID_DATA1
385 * @complete_split: Keeps track of the current split type for FS/LS
386 * endpoints on a HS Hub
387 * @isoc_split_pos: Position of the ISOC split in full/low speed
388 * @isoc_frame_index: Index of the next frame descriptor for an isochronous
389 * transfer. A frame descriptor describes the buffer
390 * position and length of the data to be transferred in the
391 * next scheduled (micro)frame of an isochronous transfer.
392 * It also holds status for that transaction. The frame
394 * @isoc_split_offset: Position of the ISOC split in the buffer for the
396 * @ssplit_out_xfer_count: How many bytes transferred during SSPLIT OUT
397 * @error_count: Holds the number of bus errors that have occurred for
398 * a transaction within this transfer
399 * @n_desc: Number of DMA descriptors for this QTD
400 * @isoc_frame_index_last: Last activated frame (packet) index, used in
401 * descriptor DMA mode only
402 * @urb: URB for this transfer
403 * @qh: Queue head for this QTD
404 * @qtd_list_entry: For linking to the QH's list of QTDs
406 * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
407 * interrupt, or isochronous transfer. A single QTD is created for each URB
408 * (of one of these types) submitted to the HCD. The transfer associated with
409 * a QTD may require one or multiple transactions.
411 * A QTD is linked to a Queue Head, which is entered in either the
412 * non-periodic or periodic schedule for execution. When a QTD is chosen for
413 * execution, some or all of its transactions may be executed. After
414 * execution, the state of the QTD is updated. The QTD may be retired if all
415 * its transactions are complete or if an error occurred. Otherwise, it
416 * remains in the schedule so more transactions can be executed later.
419 enum dwc2_control_phase control_phase;
424 u16 isoc_frame_index;
425 u16 isoc_split_offset;
428 u32 ssplit_out_xfer_count;
431 u16 isoc_frame_index_last;
432 struct dwc2_hcd_urb *urb;
434 struct list_head qtd_list_entry;
438 struct hc_xfer_info {
439 struct dwc2_hsotg *hsotg;
440 struct dwc2_host_chan *chan;
444 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg);
446 /* Gets the struct usb_hcd that contains a struct dwc2_hsotg */
447 static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg)
449 return (struct usb_hcd *)hsotg->priv;
453 * Inline used to disable one channel interrupt. Channel interrupts are
454 * disabled when the channel is halted or released by the interrupt handler.
455 * There is no need to handle further interrupts of that type until the
456 * channel is re-assigned. In fact, subsequent handling may cause crashes
457 * because the channel structures are cleaned up when the channel is released.
459 static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr)
461 u32 mask = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
464 dwc2_writel(mask, hsotg->regs + HCINTMSK(chnum));
467 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan);
468 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
469 enum dwc2_halt_status halt_status);
470 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
471 struct dwc2_host_chan *chan);
474 * Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they
475 * are read as 1, they won't clear when written back.
477 static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg)
479 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
481 hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG);
485 static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe)
490 static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe)
492 return pipe->pipe_type;
495 static inline u16 dwc2_hcd_get_maxp(struct dwc2_hcd_pipe_info *pipe)
500 static inline u16 dwc2_hcd_get_maxp_mult(struct dwc2_hcd_pipe_info *pipe)
502 return pipe->maxp_mult;
505 static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe)
507 return pipe->dev_addr;
510 static inline u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe)
512 return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC;
515 static inline u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe)
517 return pipe->pipe_type == USB_ENDPOINT_XFER_INT;
520 static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe)
522 return pipe->pipe_type == USB_ENDPOINT_XFER_BULK;
525 static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe)
527 return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL;
530 static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe)
532 return pipe->pipe_dir == USB_DIR_IN;
535 static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe)
537 return !dwc2_hcd_is_pipe_in(pipe);
540 int dwc2_hcd_init(struct dwc2_hsotg *hsotg);
541 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg);
543 /* Transaction Execution Functions */
544 enum dwc2_transaction_type dwc2_hcd_select_transactions(
545 struct dwc2_hsotg *hsotg);
546 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
547 enum dwc2_transaction_type tr_type);
549 /* Schedule Queue Functions */
550 /* Implemented in hcd_queue.c */
551 struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
552 struct dwc2_hcd_urb *urb,
554 void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
555 int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
556 void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
557 void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
560 void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb);
561 int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
564 /* Unlinks and frees a QTD */
565 static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg,
566 struct dwc2_qtd *qtd,
569 list_del(&qtd->qtd_list_entry);
574 /* Descriptor DMA support functions */
575 void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg,
577 void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg,
578 struct dwc2_host_chan *chan, int chnum,
579 enum dwc2_halt_status halt_status);
581 int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
583 void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
585 /* Check if QH is non-periodic */
586 #define dwc2_qh_is_non_per(_qh_ptr_) \
587 ((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \
588 (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL)
590 #ifdef CONFIG_USB_DWC2_DEBUG_PERIODIC
591 static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; }
592 static inline bool dbg_qh(struct dwc2_qh *qh) { return true; }
593 static inline bool dbg_urb(struct urb *urb) { return true; }
594 static inline bool dbg_perio(void) { return true; }
595 #else /* !CONFIG_USB_DWC2_DEBUG_PERIODIC */
596 static inline bool dbg_hc(struct dwc2_host_chan *hc)
598 return hc->ep_type == USB_ENDPOINT_XFER_BULK ||
599 hc->ep_type == USB_ENDPOINT_XFER_CONTROL;
602 static inline bool dbg_qh(struct dwc2_qh *qh)
604 return qh->ep_type == USB_ENDPOINT_XFER_BULK ||
605 qh->ep_type == USB_ENDPOINT_XFER_CONTROL;
608 static inline bool dbg_urb(struct urb *urb)
610 return usb_pipetype(urb->pipe) == PIPE_BULK ||
611 usb_pipetype(urb->pipe) == PIPE_CONTROL;
614 static inline bool dbg_perio(void) { return false; }
618 * Returns true if frame1 index is greater than frame2 index. The comparison
619 * is done modulo FRLISTEN_64_SIZE. This accounts for the rollover of the
620 * frame number when the max index frame number is reached.
622 static inline bool dwc2_frame_idx_num_gt(u16 fr_idx1, u16 fr_idx2)
624 u16 diff = fr_idx1 - fr_idx2;
625 u16 sign = diff & (FRLISTEN_64_SIZE >> 1);
627 return diff && !sign;
631 * Returns true if frame1 is less than or equal to frame2. The comparison is
632 * done modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the
633 * frame number when the max frame number is reached.
635 static inline int dwc2_frame_num_le(u16 frame1, u16 frame2)
637 return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1);
641 * Returns true if frame1 is greater than frame2. The comparison is done
642 * modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
643 * number when the max frame number is reached.
645 static inline int dwc2_frame_num_gt(u16 frame1, u16 frame2)
647 return (frame1 != frame2) &&
648 ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1);
652 * Increments frame by the amount specified by inc. The addition is done
653 * modulo HFNUM_MAX_FRNUM. Returns the incremented value.
655 static inline u16 dwc2_frame_num_inc(u16 frame, u16 inc)
657 return (frame + inc) & HFNUM_MAX_FRNUM;
660 static inline u16 dwc2_frame_num_dec(u16 frame, u16 dec)
662 return (frame + HFNUM_MAX_FRNUM + 1 - dec) & HFNUM_MAX_FRNUM;
665 static inline u16 dwc2_full_frame_num(u16 frame)
667 return (frame & HFNUM_MAX_FRNUM) >> 3;
670 static inline u16 dwc2_micro_frame_num(u16 frame)
676 * Returns the Core Interrupt Status register contents, ANDed with the Core
677 * Interrupt Mask register contents
679 static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg)
681 return dwc2_readl(hsotg->regs + GINTSTS) &
682 dwc2_readl(hsotg->regs + GINTMSK);
685 static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb)
687 return dwc2_urb->status;
690 static inline u32 dwc2_hcd_urb_get_actual_length(
691 struct dwc2_hcd_urb *dwc2_urb)
693 return dwc2_urb->actual_length;
696 static inline u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb)
698 return dwc2_urb->error_count;
701 static inline void dwc2_hcd_urb_set_iso_desc_params(
702 struct dwc2_hcd_urb *dwc2_urb, int desc_num, u32 offset,
705 dwc2_urb->iso_descs[desc_num].offset = offset;
706 dwc2_urb->iso_descs[desc_num].length = length;
709 static inline u32 dwc2_hcd_urb_get_iso_desc_status(
710 struct dwc2_hcd_urb *dwc2_urb, int desc_num)
712 return dwc2_urb->iso_descs[desc_num].status;
715 static inline u32 dwc2_hcd_urb_get_iso_desc_actual_length(
716 struct dwc2_hcd_urb *dwc2_urb, int desc_num)
718 return dwc2_urb->iso_descs[desc_num].actual_length;
721 static inline int dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg *hsotg,
722 struct usb_host_endpoint *ep)
724 struct dwc2_qh *qh = ep->hcpriv;
726 if (qh && !list_empty(&qh->qh_list_entry))
732 static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg,
733 struct usb_host_endpoint *ep)
735 struct dwc2_qh *qh = ep->hcpriv;
745 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
746 struct dwc2_host_chan *chan, int chnum,
747 struct dwc2_qtd *qtd);
752 * dwc2_handle_hcd_intr() - Called on every hardware interrupt
754 * @hsotg: The DWC2 HCD
756 * Returns IRQ_HANDLED if interrupt is handled
757 * Return IRQ_NONE if interrupt is not handled
759 irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg);
762 * dwc2_hcd_stop() - Halts the DWC_otg host mode operation
764 * @hsotg: The DWC2 HCD
766 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg);
769 * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host,
772 * @hsotg: The DWC2 HCD
774 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg);
777 * dwc2_hcd_dump_state() - Dumps hsotg state
779 * @hsotg: The DWC2 HCD
781 * NOTE: This function will be removed once the peripheral controller code
782 * is integrated and the driver is stable
784 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg);
787 * dwc2_hcd_dump_frrem() - Dumps the average frame remaining at SOF
789 * @hsotg: The DWC2 HCD
791 * This can be used to determine average interrupt latency. Frame remaining is
792 * also shown for start transfer and two additional sample points.
794 * NOTE: This function will be removed once the peripheral controller code
795 * is integrated and the driver is stable
797 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg);
802 #define URB_GIVEBACK_ASAP 0x1
803 #define URB_SEND_ZERO_PACKET 0x2
805 /* Host driver callbacks */
806 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg,
807 void *context, gfp_t mem_flags,
810 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg,
811 struct dwc2_tt *dwc_tt);
812 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context);
813 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
818 * Macro to sample the remaining PHY clocks left in the current frame. This
819 * may be used during debugging to determine the average time it takes to
820 * execute sections of code. There are two possible sample points, "a" and
821 * "b", so the _letter_ argument must be one of these values.
823 * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
824 * example, "cat /sys/devices/lm0/hcd_frrem".
826 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) \
828 struct hfnum_data _hfnum_; \
829 struct dwc2_qtd *_qtd_; \
831 _qtd_ = list_entry((_qh_)->qtd_list.next, struct dwc2_qtd, \
833 if (usb_pipeint(_qtd_->urb->pipe) && \
834 (_qh_)->start_active_frame != 0 && !_qtd_->complete_split) { \
835 _hfnum_.d32 = dwc2_readl((_hcd_)->regs + HFNUM); \
836 switch (_hfnum_.b.frnum & 0x7) { \
838 (_hcd_)->hfnum_7_samples_##_letter_++; \
839 (_hcd_)->hfnum_7_frrem_accum_##_letter_ += \
843 (_hcd_)->hfnum_0_samples_##_letter_++; \
844 (_hcd_)->hfnum_0_frrem_accum_##_letter_ += \
848 (_hcd_)->hfnum_other_samples_##_letter_++; \
849 (_hcd_)->hfnum_other_frrem_accum_##_letter_ += \
856 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) do {} while (0)
859 #endif /* __DWC2_HCD_H__ */