ufshci.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Universal Flash Storage Host controller driver
   4  * Copyright (C) 2011-2013 Samsung India Software Operations
   5  *
   6  * Authors:
   7  *      Santosh Yaraganavi <santosh.sy@samsung.com>
   8  *      Vinayak Holikatti <h.vinayak@samsung.com>
   9  */
  10
  11 #ifndef _UFSHCI_H
  12 #define _UFSHCI_H
  13
  14 #include <linux/types.h>
  15 #include <ufs/ufs.h>
  16
  17 enum {
  18         TASK_REQ_UPIU_SIZE_DWORDS       = 8,
  19         TASK_RSP_UPIU_SIZE_DWORDS       = 8,
  20         ALIGNED_UPIU_SIZE               = 512,
  21 };
  22
  23 /* UFSHCI Registers */
  24 enum {
  25         REG_CONTROLLER_CAPABILITIES             = 0x00,
  26         REG_MCQCAP                              = 0x04,
  27         REG_UFS_VERSION                         = 0x08,
  28         REG_CONTROLLER_DEV_ID                   = 0x10,
  29         REG_CONTROLLER_PROD_ID                  = 0x14,
  30         REG_AUTO_HIBERNATE_IDLE_TIMER           = 0x18,
  31         REG_INTERRUPT_STATUS                    = 0x20,
  32         REG_INTERRUPT_ENABLE                    = 0x24,
  33         REG_CONTROLLER_STATUS                   = 0x30,
  34         REG_CONTROLLER_ENABLE                   = 0x34,
  35         REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER    = 0x38,
  36         REG_UIC_ERROR_CODE_DATA_LINK_LAYER      = 0x3C,
  37         REG_UIC_ERROR_CODE_NETWORK_LAYER        = 0x40,
  38         REG_UIC_ERROR_CODE_TRANSPORT_LAYER      = 0x44,
  39         REG_UIC_ERROR_CODE_DME                  = 0x48,
  40         REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL    = 0x4C,
  41         REG_UTP_TRANSFER_REQ_LIST_BASE_L        = 0x50,
  42         REG_UTP_TRANSFER_REQ_LIST_BASE_H        = 0x54,
  43         REG_UTP_TRANSFER_REQ_DOOR_BELL          = 0x58,
  44         REG_UTP_TRANSFER_REQ_LIST_CLEAR         = 0x5C,
  45         REG_UTP_TRANSFER_REQ_LIST_RUN_STOP      = 0x60,
  46         REG_UTP_TASK_REQ_LIST_BASE_L            = 0x70,
  47         REG_UTP_TASK_REQ_LIST_BASE_H            = 0x74,
  48         REG_UTP_TASK_REQ_DOOR_BELL              = 0x78,
  49         REG_UTP_TASK_REQ_LIST_CLEAR             = 0x7C,
  50         REG_UTP_TASK_REQ_LIST_RUN_STOP          = 0x80,
  51         REG_UIC_COMMAND                         = 0x90,
  52         REG_UIC_COMMAND_ARG_1                   = 0x94,
  53         REG_UIC_COMMAND_ARG_2                   = 0x98,
  54         REG_UIC_COMMAND_ARG_3                   = 0x9C,
  55
  56         UFSHCI_REG_SPACE_SIZE                   = 0xA0,
  57
  58         REG_UFS_CCAP                            = 0x100,
  59         REG_UFS_CRYPTOCAP                       = 0x104,
  60
  61         REG_UFS_MEM_CFG                         = 0x300,
  62         REG_UFS_MCQ_CFG                         = 0x380,
  63         REG_UFS_ESILBA                          = 0x384,
  64         REG_UFS_ESIUBA                          = 0x388,
  65         UFSHCI_CRYPTO_REG_SPACE_SIZE            = 0x400,
  66 };
  67
  68 /* Controller capability masks */
  69 enum {
  70         MASK_TRANSFER_REQUESTS_SLOTS            = 0x0000001F,
  71         MASK_TASK_MANAGEMENT_REQUEST_SLOTS      = 0x00070000,
  72         MASK_EHSLUTRD_SUPPORTED                 = 0x00400000,
  73         MASK_AUTO_HIBERN8_SUPPORT               = 0x00800000,
  74         MASK_64_ADDRESSING_SUPPORT              = 0x01000000,
  75         MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
  76         MASK_UIC_DME_TEST_MODE_SUPPORT          = 0x04000000,
  77         MASK_CRYPTO_SUPPORT                     = 0x10000000,
  78         MASK_MCQ_SUPPORT                        = 0x40000000,
  79 };
  80
  81 /* MCQ capability mask */
  82 enum {
  83         MASK_EXT_IID_SUPPORT = 0x00000400,
  84 };
  85
  86 enum {
  87         REG_SQATTR              = 0x0,
  88         REG_SQLBA               = 0x4,
  89         REG_SQUBA               = 0x8,
  90         REG_SQDAO               = 0xC,
  91         REG_SQISAO              = 0x10,
  92
  93         REG_CQATTR              = 0x20,
  94         REG_CQLBA               = 0x24,
  95         REG_CQUBA               = 0x28,
  96         REG_CQDAO               = 0x2C,
  97         REG_CQISAO              = 0x30,
  98 };
  99
 100 enum {
 101         REG_SQHP                = 0x0,
 102         REG_SQTP                = 0x4,
 103         REG_SQRTC               = 0x8,
 104         REG_SQCTI               = 0xC,
 105         REG_SQRTS               = 0x10,
 106 };
 107
 108 enum {
 109         REG_CQHP                = 0x0,
 110         REG_CQTP                = 0x4,
 111 };
 112
 113 enum {
 114         REG_CQIS                = 0x0,
 115         REG_CQIE                = 0x4,
 116 };
 117
 118 enum {
 119         SQ_START                = 0x0,
 120         SQ_STOP                 = 0x1,
 121         SQ_ICU                  = 0x2,
 122 };
 123
 124 enum {
 125         SQ_STS                  = 0x1,
 126         SQ_CUS                  = 0x2,
 127 };
 128
 129 #define SQ_ICU_ERR_CODE_MASK            GENMASK(7, 4)
 130 #define UFS_MASK(mask, offset)          ((mask) << (offset))
 131
 132 /* UFS Version 08h */
 133 #define MINOR_VERSION_NUM_MASK          UFS_MASK(0xFFFF, 0)
 134 #define MAJOR_VERSION_NUM_MASK          UFS_MASK(0xFFFF, 16)
 135
 136 #define UFSHCD_NUM_RESERVED     1
 137 /*
 138  * Controller UFSHCI version
 139  * - 2.x and newer use the following scheme:
 140  *   major << 8 + minor << 4
 141  * - 1.x has been converted to match this in
 142  *   ufshcd_get_ufs_version()
 143  */
 144 static inline u32 ufshci_version(u32 major, u32 minor)
 145 {
 146         return (major << 8) + (minor << 4);
 147 }
 148
 149 /*
 150  * HCDDID - Host Controller Identification Descriptor
 151  *        - Device ID and Device Class 10h
 152  */
 153 #define DEVICE_CLASS    UFS_MASK(0xFFFF, 0)
 154 #define DEVICE_ID       UFS_MASK(0xFF, 24)
 155
 156 /*
 157  * HCPMID - Host Controller Identification Descriptor
 158  *        - Product/Manufacturer ID  14h
 159  */
 160 #define MANUFACTURE_ID_MASK     UFS_MASK(0xFFFF, 0)
 161 #define PRODUCT_ID_MASK         UFS_MASK(0xFFFF, 16)
 162
 163 /* AHIT - Auto-Hibernate Idle Timer */
 164 #define UFSHCI_AHIBERN8_TIMER_MASK              GENMASK(9, 0)
 165 #define UFSHCI_AHIBERN8_SCALE_MASK              GENMASK(12, 10)
 166 #define UFSHCI_AHIBERN8_SCALE_FACTOR            10
 167 #define UFSHCI_AHIBERN8_MAX                     (1023 * 100000)
 168
 169 /*
 170  * IS - Interrupt Status - 20h
 171  */
 172 #define UTP_TRANSFER_REQ_COMPL                  0x1
 173 #define UIC_DME_END_PT_RESET                    0x2
 174 #define UIC_ERROR                               0x4
 175 #define UIC_TEST_MODE                           0x8
 176 #define UIC_POWER_MODE                          0x10
 177 #define UIC_HIBERNATE_EXIT                      0x20
 178 #define UIC_HIBERNATE_ENTER                     0x40
 179 #define UIC_LINK_LOST                           0x80
 180 #define UIC_LINK_STARTUP                        0x100
 181 #define UTP_TASK_REQ_COMPL                      0x200
 182 #define UIC_COMMAND_COMPL                       0x400
 183 #define DEVICE_FATAL_ERROR                      0x800
 184 #define CONTROLLER_FATAL_ERROR                  0x10000
 185 #define SYSTEM_BUS_FATAL_ERROR                  0x20000
 186 #define CRYPTO_ENGINE_FATAL_ERROR               0x40000
 187 #define MCQ_CQ_EVENT_STATUS                     0x100000
 188
 189 #define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\
 190                                 UIC_HIBERNATE_EXIT)
 191
 192 #define UFSHCD_UIC_PWR_MASK     (UFSHCD_UIC_HIBERN8_MASK |\
 193                                 UIC_POWER_MODE)
 194
 195 #define UFSHCD_UIC_MASK         (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
 196
 197 #define UFSHCD_ERROR_MASK       (UIC_ERROR | INT_FATAL_ERRORS)
 198
 199 #define INT_FATAL_ERRORS        (DEVICE_FATAL_ERROR |\
 200                                 CONTROLLER_FATAL_ERROR |\
 201                                 SYSTEM_BUS_FATAL_ERROR |\
 202                                 CRYPTO_ENGINE_FATAL_ERROR |\
 203                                 UIC_LINK_LOST)
 204
 205 /* HCS - Host Controller Status 30h */
 206 #define DEVICE_PRESENT                          0x1
 207 #define UTP_TRANSFER_REQ_LIST_READY             0x2
 208 #define UTP_TASK_REQ_LIST_READY                 0x4
 209 #define UIC_COMMAND_READY                       0x8
 210 #define HOST_ERROR_INDICATOR                    0x10
 211 #define DEVICE_ERROR_INDICATOR                  0x20
 212 #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK   UFS_MASK(0x7, 8)
 213
 214 #define UFSHCD_STATUS_READY     (UTP_TRANSFER_REQ_LIST_READY |\
 215                                 UTP_TASK_REQ_LIST_READY |\
 216                                 UIC_COMMAND_READY)
 217
 218 enum {
 219         PWR_OK          = 0x0,
 220         PWR_LOCAL       = 0x01,
 221         PWR_REMOTE      = 0x02,
 222         PWR_BUSY        = 0x03,
 223         PWR_ERROR_CAP   = 0x04,
 224         PWR_FATAL_ERROR = 0x05,
 225 };
 226
 227 /* HCE - Host Controller Enable 34h */
 228 #define CONTROLLER_ENABLE       0x1
 229 #define CONTROLLER_DISABLE      0x0
 230 #define CRYPTO_GENERAL_ENABLE   0x2
 231
 232 /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
 233 #define UIC_PHY_ADAPTER_LAYER_ERROR                     0x80000000
 234 #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK           0x1F
 235 #define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK             0xF
 236 #define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR             0x10
 237
 238 /* UECDL - Host UIC Error Code Data Link Layer 3Ch */
 239 #define UIC_DATA_LINK_LAYER_ERROR               0x80000000
 240 #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK     0xFFFF
 241 #define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP     0x2
 242 #define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP    0x4
 243 #define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP     0x8
 244 #define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF     0x20
 245 #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT       0x2000
 246 #define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED  0x0001
 247 #define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
 248
 249 /* UECN - Host UIC Error Code Network Layer 40h */
 250 #define UIC_NETWORK_LAYER_ERROR                 0x80000000
 251 #define UIC_NETWORK_LAYER_ERROR_CODE_MASK       0x7
 252 #define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE     0x1
 253 #define UIC_NETWORK_BAD_DEVICEID_ENC            0x2
 254 #define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING   0x4
 255
 256 /* UECT - Host UIC Error Code Transport Layer 44h */
 257 #define UIC_TRANSPORT_LAYER_ERROR               0x80000000
 258 #define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK     0x7F
 259 #define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE   0x1
 260 #define UIC_TRANSPORT_UNKNOWN_CPORTID           0x2
 261 #define UIC_TRANSPORT_NO_CONNECTION_RX          0x4
 262 #define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING       0x8
 263 #define UIC_TRANSPORT_BAD_TC                    0x10
 264 #define UIC_TRANSPORT_E2E_CREDIT_OVERFOW        0x20
 265 #define UIC_TRANSPORT_SAFETY_VALUE_DROPPING     0x40
 266
 267 /* UECDME - Host UIC Error Code DME 48h */
 268 #define UIC_DME_ERROR                   0x80000000
 269 #define UIC_DME_ERROR_CODE_MASK         0x1
 270
 271 /* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
 272 #define INT_AGGR_TIMEOUT_VAL_MASK               0xFF
 273 #define INT_AGGR_COUNTER_THRESHOLD_MASK         UFS_MASK(0x1F, 8)
 274 #define INT_AGGR_COUNTER_AND_TIMER_RESET        0x10000
 275 #define INT_AGGR_STATUS_BIT                     0x100000
 276 #define INT_AGGR_PARAM_WRITE                    0x1000000
 277 #define INT_AGGR_ENABLE                         0x80000000
 278
 279 /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
 280 #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT      0x1
 281
 282 /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
 283 #define UTP_TASK_REQ_LIST_RUN_STOP_BIT          0x1
 284
 285 /* CQISy - CQ y Interrupt Status Register  */
 286 #define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS       0x1
 287
 288 /* UICCMD - UIC Command */
 289 #define COMMAND_OPCODE_MASK             0xFF
 290 #define GEN_SELECTOR_INDEX_MASK         0xFFFF
 291
 292 #define MIB_ATTRIBUTE_MASK              UFS_MASK(0xFFFF, 16)
 293 #define RESET_LEVEL                     0xFF
 294
 295 #define ATTR_SET_TYPE_MASK              UFS_MASK(0xFF, 16)
 296 #define CONFIG_RESULT_CODE_MASK         0xFF
 297 #define GENERIC_ERROR_CODE_MASK         0xFF
 298
 299 /* GenSelectorIndex calculation macros for M-PHY attributes */
 300 #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
 301 #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
 302
 303 #define UIC_ARG_MIB_SEL(attr, sel)      ((((attr) & 0xFFFF) << 16) |\
 304                                          ((sel) & 0xFFFF))
 305 #define UIC_ARG_MIB(attr)               UIC_ARG_MIB_SEL(attr, 0)
 306 #define UIC_ARG_ATTR_TYPE(t)            (((t) & 0xFF) << 16)
 307 #define UIC_GET_ATTR_ID(v)              (((v) >> 16) & 0xFFFF)
 308
 309 /* Link Status*/
 310 enum link_status {
 311         UFSHCD_LINK_IS_DOWN     = 1,
 312         UFSHCD_LINK_IS_UP       = 2,
 313 };
 314
 315 /* UIC Commands */
 316 enum uic_cmd_dme {
 317         UIC_CMD_DME_GET                 = 0x01,
 318         UIC_CMD_DME_SET                 = 0x02,
 319         UIC_CMD_DME_PEER_GET            = 0x03,
 320         UIC_CMD_DME_PEER_SET            = 0x04,
 321         UIC_CMD_DME_POWERON             = 0x10,
 322         UIC_CMD_DME_POWEROFF            = 0x11,
 323         UIC_CMD_DME_ENABLE              = 0x12,
 324         UIC_CMD_DME_RESET               = 0x14,
 325         UIC_CMD_DME_END_PT_RST          = 0x15,
 326         UIC_CMD_DME_LINK_STARTUP        = 0x16,
 327         UIC_CMD_DME_HIBER_ENTER         = 0x17,
 328         UIC_CMD_DME_HIBER_EXIT          = 0x18,
 329         UIC_CMD_DME_TEST_MODE           = 0x1A,
 330 };
 331
 332 /* UIC Config result code / Generic error code */
 333 enum {
 334         UIC_CMD_RESULT_SUCCESS                  = 0x00,
 335         UIC_CMD_RESULT_INVALID_ATTR             = 0x01,
 336         UIC_CMD_RESULT_FAILURE                  = 0x01,
 337         UIC_CMD_RESULT_INVALID_ATTR_VALUE       = 0x02,
 338         UIC_CMD_RESULT_READ_ONLY_ATTR           = 0x03,
 339         UIC_CMD_RESULT_WRITE_ONLY_ATTR          = 0x04,
 340         UIC_CMD_RESULT_BAD_INDEX                = 0x05,
 341         UIC_CMD_RESULT_LOCKED_ATTR              = 0x06,
 342         UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX   = 0x07,
 343         UIC_CMD_RESULT_PEER_COMM_FAILURE        = 0x08,
 344         UIC_CMD_RESULT_BUSY                     = 0x09,
 345         UIC_CMD_RESULT_DME_FAILURE              = 0x0A,
 346 };
 347
 348 #define MASK_UIC_COMMAND_RESULT                 0xFF
 349
 350 #define INT_AGGR_COUNTER_THLD_VAL(c)    (((c) & 0x1F) << 8)
 351 #define INT_AGGR_TIMEOUT_VAL(t)         (((t) & 0xFF) << 0)
 352
 353 /* Interrupt disable masks */
 354 enum {
 355         /* Interrupt disable mask for UFSHCI v1.0 */
 356         INTERRUPT_MASK_ALL_VER_10       = 0x30FFF,
 357         INTERRUPT_MASK_RW_VER_10        = 0x30000,
 358
 359         /* Interrupt disable mask for UFSHCI v1.1 */
 360         INTERRUPT_MASK_ALL_VER_11       = 0x31FFF,
 361
 362         /* Interrupt disable mask for UFSHCI v2.1 */
 363         INTERRUPT_MASK_ALL_VER_21       = 0x71FFF,
 364 };
 365
 366 /* CCAP - Crypto Capability 100h */
 367 union ufs_crypto_capabilities {
 368         __le32 reg_val;
 369         struct {
 370                 u8 num_crypto_cap;
 371                 u8 config_count;
 372                 u8 reserved;
 373                 u8 config_array_ptr;
 374         };
 375 };
 376
 377 enum ufs_crypto_key_size {
 378         UFS_CRYPTO_KEY_SIZE_INVALID     = 0x0,
 379         UFS_CRYPTO_KEY_SIZE_128         = 0x1,
 380         UFS_CRYPTO_KEY_SIZE_192         = 0x2,
 381         UFS_CRYPTO_KEY_SIZE_256         = 0x3,
 382         UFS_CRYPTO_KEY_SIZE_512         = 0x4,
 383 };
 384
 385 enum ufs_crypto_alg {
 386         UFS_CRYPTO_ALG_AES_XTS                  = 0x0,
 387         UFS_CRYPTO_ALG_BITLOCKER_AES_CBC        = 0x1,
 388         UFS_CRYPTO_ALG_AES_ECB                  = 0x2,
 389         UFS_CRYPTO_ALG_ESSIV_AES_CBC            = 0x3,
 390 };
 391
 392 /* x-CRYPTOCAP - Crypto Capability X */
 393 union ufs_crypto_cap_entry {
 394         __le32 reg_val;
 395         struct {
 396                 u8 algorithm_id;
 397                 u8 sdus_mask; /* Supported data unit size mask */
 398                 u8 key_size;
 399                 u8 reserved;
 400         };
 401 };
 402
 403 #define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
 404 #define UFS_CRYPTO_KEY_MAX_SIZE 64
 405 /* x-CRYPTOCFG - Crypto Configuration X */
 406 union ufs_crypto_cfg_entry {
 407         __le32 reg_val[32];
 408         struct {
 409                 u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE];
 410                 u8 data_unit_size;
 411                 u8 crypto_cap_idx;
 412                 u8 reserved_1;
 413                 u8 config_enable;
 414                 u8 reserved_multi_host;
 415                 u8 reserved_2;
 416                 u8 vsb[2];
 417                 u8 reserved_3[56];
 418         };
 419 };
 420
 421 /*
 422  * Request Descriptor Definitions
 423  */
 424
 425 /* Transfer request command type */
 426 enum {
 427         UTP_CMD_TYPE_SCSI               = 0x0,
 428         UTP_CMD_TYPE_UFS                = 0x1,
 429         UTP_CMD_TYPE_DEV_MANAGE         = 0x2,
 430 };
 431
 432 /* To accommodate UFS2.0 required Command type */
 433 enum {
 434         UTP_CMD_TYPE_UFS_STORAGE        = 0x1,
 435 };
 436
 437 enum {
 438         UTP_SCSI_COMMAND                = 0x00000000,
 439         UTP_NATIVE_UFS_COMMAND          = 0x10000000,
 440         UTP_DEVICE_MANAGEMENT_FUNCTION  = 0x20000000,
 441 };
 442
 443 /* UTP Transfer Request Data Direction (DD) */
 444 enum utp_data_direction {
 445         UTP_NO_DATA_TRANSFER    = 0,
 446         UTP_HOST_TO_DEVICE      = 1,
 447         UTP_DEVICE_TO_HOST      = 2,
 448 };
 449
 450 /* Overall command status values */
 451 enum utp_ocs {
 452         OCS_SUCCESS                     = 0x0,
 453         OCS_INVALID_CMD_TABLE_ATTR      = 0x1,
 454         OCS_INVALID_PRDT_ATTR           = 0x2,
 455         OCS_MISMATCH_DATA_BUF_SIZE      = 0x3,
 456         OCS_MISMATCH_RESP_UPIU_SIZE     = 0x4,
 457         OCS_PEER_COMM_FAILURE           = 0x5,
 458         OCS_ABORTED                     = 0x6,
 459         OCS_FATAL_ERROR                 = 0x7,
 460         OCS_DEVICE_FATAL_ERROR          = 0x8,
 461         OCS_INVALID_CRYPTO_CONFIG       = 0x9,
 462         OCS_GENERAL_CRYPTO_ERROR        = 0xA,
 463         OCS_INVALID_COMMAND_STATUS      = 0x0F,
 464 };
 465
 466 enum {
 467         MASK_OCS                        = 0x0F,
 468 };
 469
 470 /* The maximum length of the data byte count field in the PRDT is 256KB */
 471 #define PRDT_DATA_BYTE_COUNT_MAX        SZ_256K
 472 /* The granularity of the data byte count field in the PRDT is 32-bit */
 473 #define PRDT_DATA_BYTE_COUNT_PAD        4
 474
 475 /**
 476  * struct ufshcd_sg_entry - UFSHCI PRD Entry
 477  * @addr: Physical address; DW-0 and DW-1.
 478  * @reserved: Reserved for future use DW-2
 479  * @size: size of physical segment DW-3
 480  */
 481 struct ufshcd_sg_entry {
 482         __le64    addr;
 483         __le32    reserved;
 484         __le32    size;
 485         /*
 486          * followed by variant-specific fields if
 487          * CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE has been defined.
 488          */
 489 };
 490
 491 /**
 492  * struct utp_transfer_cmd_desc - UTP Command Descriptor (UCD)
 493  * @command_upiu: Command UPIU Frame address
 494  * @response_upiu: Response UPIU Frame address
 495  * @prd_table: Physical Region Descriptor: an array of SG_ALL struct
 496  *      ufshcd_sg_entry's.  Variant-specific fields may be present after each.
 497  */
 498 struct utp_transfer_cmd_desc {
 499         u8 command_upiu[ALIGNED_UPIU_SIZE];
 500         u8 response_upiu[ALIGNED_UPIU_SIZE];
 501         u8 prd_table[];
 502 };
 503
 504 /**
 505  * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
 506  */
 507 struct request_desc_header {
 508         u8 cci;
 509         u8 ehs_length;
 510 #if defined(__BIG_ENDIAN)
 511         u8 enable_crypto:1;
 512         u8 reserved2:7;
 513
 514         u8 command_type:4;
 515         u8 reserved1:1;
 516         u8 data_direction:2;
 517         u8 interrupt:1;
 518 #elif defined(__LITTLE_ENDIAN)
 519         u8 reserved2:7;
 520         u8 enable_crypto:1;
 521
 522         u8 interrupt:1;
 523         u8 data_direction:2;
 524         u8 reserved1:1;
 525         u8 command_type:4;
 526 #else
 527 #error
 528 #endif
 529
 530         __le32 dunl;
 531         u8 ocs;
 532         u8 cds;
 533         __le16 ldbc;
 534         __le32 dunu;
 535 };
 536
 537 static_assert(sizeof(struct request_desc_header) == 16);
 538
 539 /**
 540  * struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD)
 541  * @header: UTRD header DW-0 to DW-3
 542  * @command_desc_base_addr: UCD base address DW 4-5
 543  * @response_upiu_length: response UPIU length DW-6
 544  * @response_upiu_offset: response UPIU offset DW-6
 545  * @prd_table_length: Physical region descriptor length DW-7
 546  * @prd_table_offset: Physical region descriptor offset DW-7
 547  */
 548 struct utp_transfer_req_desc {
 549
 550         /* DW 0-3 */
 551         struct request_desc_header header;
 552
 553         /* DW 4-5*/
 554         __le64  command_desc_base_addr;
 555
 556         /* DW 6 */
 557         __le16  response_upiu_length;
 558         __le16  response_upiu_offset;
 559
 560         /* DW 7 */
 561         __le16  prd_table_length;
 562         __le16  prd_table_offset;
 563 };
 564
 565 /* MCQ Completion Queue Entry */
 566 struct cq_entry {
 567         /* DW 0-1 */
 568         __le64 command_desc_base_addr;
 569
 570         /* DW 2 */
 571         __le16  response_upiu_length;
 572         __le16  response_upiu_offset;
 573
 574         /* DW 3 */
 575         __le16  prd_table_length;
 576         __le16  prd_table_offset;
 577
 578         /* DW 4 */
 579         __le32 status;
 580
 581         /* DW 5-7 */
 582         __le32 reserved[3];
 583 };
 584
 585 static_assert(sizeof(struct cq_entry) == 32);
 586
 587 /*
 588  * UTMRD structure.
 589  */
 590 struct utp_task_req_desc {
 591         /* DW 0-3 */
 592         struct request_desc_header header;
 593
 594         /* DW 4-11 - Task request UPIU structure */
 595         struct {
 596                 struct utp_upiu_header  req_header;
 597                 __be32                  input_param1;
 598                 __be32                  input_param2;
 599                 __be32                  input_param3;
 600                 __be32                  __reserved1[2];
 601         } upiu_req;
 602
 603         /* DW 12-19 - Task Management Response UPIU structure */
 604         struct {
 605                 struct utp_upiu_header  rsp_header;
 606                 __be32                  output_param1;
 607                 __be32                  output_param2;
 608                 __be32                  __reserved2[3];
 609         } upiu_rsp;
 610 };
 611
 612 #endif /* End of Header */