2 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
15 #include <linux/time.h>
17 #include <linux/platform_device.h>
18 #include <linux/phy/phy.h>
19 #include <linux/phy/phy-qcom-ufs.h>
22 #include "ufshcd-pltfrm.h"
26 #include "ufs_quirks.h"
27 #define UFS_QCOM_DEFAULT_DBG_PRINT_EN \
28 (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
46 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS];
48 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote);
49 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
50 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
53 static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len,
54 const char *prefix, void *priv)
56 ufshcd_dump_regs(hba, offset, len * 4, prefix);
59 static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes)
63 err = ufshcd_dme_get(hba,
64 UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), tx_lanes);
66 dev_err(hba->dev, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n",
72 static int ufs_qcom_host_clk_get(struct device *dev,
73 const char *name, struct clk **clk_out)
78 clk = devm_clk_get(dev, name);
81 dev_err(dev, "%s: failed to get %s err %d",
90 static int ufs_qcom_host_clk_enable(struct device *dev,
91 const char *name, struct clk *clk)
95 err = clk_prepare_enable(clk);
97 dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err);
102 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
104 if (!host->is_lane_clks_enabled)
107 if (host->hba->lanes_per_direction > 1)
108 clk_disable_unprepare(host->tx_l1_sync_clk);
109 clk_disable_unprepare(host->tx_l0_sync_clk);
110 if (host->hba->lanes_per_direction > 1)
111 clk_disable_unprepare(host->rx_l1_sync_clk);
112 clk_disable_unprepare(host->rx_l0_sync_clk);
114 host->is_lane_clks_enabled = false;
117 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
120 struct device *dev = host->hba->dev;
122 if (host->is_lane_clks_enabled)
125 err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk",
126 host->rx_l0_sync_clk);
130 err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk",
131 host->tx_l0_sync_clk);
135 if (host->hba->lanes_per_direction > 1) {
136 err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk",
137 host->rx_l1_sync_clk);
141 err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk",
142 host->tx_l1_sync_clk);
147 host->is_lane_clks_enabled = true;
151 if (host->hba->lanes_per_direction > 1)
152 clk_disable_unprepare(host->rx_l1_sync_clk);
154 clk_disable_unprepare(host->tx_l0_sync_clk);
156 clk_disable_unprepare(host->rx_l0_sync_clk);
161 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
164 struct device *dev = host->hba->dev;
166 err = ufs_qcom_host_clk_get(dev,
167 "rx_lane0_sync_clk", &host->rx_l0_sync_clk);
171 err = ufs_qcom_host_clk_get(dev,
172 "tx_lane0_sync_clk", &host->tx_l0_sync_clk);
176 /* In case of single lane per direction, don't read lane1 clocks */
177 if (host->hba->lanes_per_direction > 1) {
178 err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
179 &host->rx_l1_sync_clk);
183 err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
184 &host->tx_l1_sync_clk);
190 static int ufs_qcom_link_startup_post_change(struct ufs_hba *hba)
192 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
193 struct phy *phy = host->generic_phy;
197 err = ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes);
201 err = ufs_qcom_phy_set_tx_lane_enable(phy, tx_lanes);
203 dev_err(hba->dev, "%s: ufs_qcom_phy_set_tx_lane_enable failed\n",
210 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
214 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
217 err = ufshcd_dme_get(hba,
218 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
219 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
221 if (err || tx_fsm_val == TX_FSM_HIBERN8)
224 /* sleep for max. 200us */
225 usleep_range(100, 200);
226 } while (time_before(jiffies, timeout));
229 * we might have scheduled out for long during polling so
230 * check the state again.
232 if (time_after(jiffies, timeout))
233 err = ufshcd_dme_get(hba,
234 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
235 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
239 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
241 } else if (tx_fsm_val != TX_FSM_HIBERN8) {
243 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
250 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
252 ufshcd_rmwl(host->hba, QUNIPRO_SEL,
253 ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0,
255 /* make sure above configuration is applied before we return */
259 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
261 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
262 struct phy *phy = host->generic_phy;
264 bool is_rate_B = (UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B)
268 phy_set_mode(phy, PHY_MODE_UFS_HS_B);
270 /* Assert PHY reset and apply PHY calibration values */
271 ufs_qcom_assert_reset(hba);
272 /* provide 1ms delay to let the reset pulse propagate */
273 usleep_range(1000, 1100);
275 /* phy initialization - calibrate the phy */
278 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
283 /* De-assert PHY reset and start serdes */
284 ufs_qcom_deassert_reset(hba);
287 * after reset deassertion, phy will need all ref clocks,
288 * voltage, current to settle down before starting serdes.
290 usleep_range(1000, 1100);
292 /* power on phy - start serdes and phy's power and clocks */
293 ret = phy_power_on(phy);
295 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
297 goto out_disable_phy;
300 ufs_qcom_select_unipro_mode(host);
305 ufs_qcom_assert_reset(hba);
312 * The UTP controller has a number of internal clock gating cells (CGCs).
313 * Internal hardware sub-modules within the UTP controller control the CGCs.
314 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
315 * in a specific operation, UTP controller CGCs are by default disabled and
316 * this function enables them (after every UFS link startup) to save some power
319 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
322 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL,
325 /* Ensure that HW clock gating is enabled before next operations */
329 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
330 enum ufs_notify_change_status status)
332 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
337 ufs_qcom_power_up_sequence(hba);
339 * The PHY PLL output is the source of tx/rx lane symbol
340 * clocks, hence, enable the lane clocks only after PHY
343 err = ufs_qcom_enable_lane_clks(host);
346 /* check if UFS PHY moved from DISABLED to HIBERN8 */
347 err = ufs_qcom_check_hibern8(hba);
348 ufs_qcom_enable_hw_clk_gating(hba);
352 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
360 * Returns zero for success and non-zero in case of a failure
362 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
363 u32 hs, u32 rate, bool update_link_startup_timer)
366 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
367 struct ufs_clk_info *clki;
368 u32 core_clk_period_in_ns;
369 u32 tx_clk_cycles_per_us = 0;
370 unsigned long core_clk_rate = 0;
371 u32 core_clk_cycles_per_us = 0;
373 static u32 pwm_fr_table[][2] = {
380 static u32 hs_fr_table_rA[][2] = {
386 static u32 hs_fr_table_rB[][2] = {
393 * The Qunipro controller does not use following registers:
394 * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG &
395 * UFS_REG_PA_LINK_STARTUP_TIMER
396 * But UTP controller uses SYS1CLK_1US_REG register for Interrupt
399 if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))
403 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
407 list_for_each_entry(clki, &hba->clk_list_head, list) {
408 if (!strcmp(clki->name, "core_clk"))
409 core_clk_rate = clk_get_rate(clki->clk);
412 /* If frequency is smaller than 1MHz, set to 1MHz */
413 if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
414 core_clk_rate = DEFAULT_CLK_RATE_HZ;
416 core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
417 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
418 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
420 * make sure above write gets applied before we return from
426 if (ufs_qcom_cap_qunipro(host))
429 core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
430 core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
431 core_clk_period_in_ns &= MASK_CLK_NS_REG;
436 if (rate == PA_HS_MODE_A) {
437 if (gear > ARRAY_SIZE(hs_fr_table_rA)) {
439 "%s: index %d exceeds table size %zu\n",
441 ARRAY_SIZE(hs_fr_table_rA));
444 tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];
445 } else if (rate == PA_HS_MODE_B) {
446 if (gear > ARRAY_SIZE(hs_fr_table_rB)) {
448 "%s: index %d exceeds table size %zu\n",
450 ARRAY_SIZE(hs_fr_table_rB));
453 tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];
455 dev_err(hba->dev, "%s: invalid rate = %d\n",
462 if (gear > ARRAY_SIZE(pwm_fr_table)) {
464 "%s: index %d exceeds table size %zu\n",
466 ARRAY_SIZE(pwm_fr_table));
469 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];
473 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);
477 if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=
478 (core_clk_period_in_ns | tx_clk_cycles_per_us)) {
479 /* this register 2 fields shall be written at once */
480 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us,
481 REG_UFS_TX_SYMBOL_CLK_NS_US);
483 * make sure above write gets applied before we return from
489 if (update_link_startup_timer) {
490 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100),
491 REG_UFS_PA_LINK_STARTUP_TIMER);
493 * make sure that this configuration is applied before
506 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
507 enum ufs_notify_change_status status)
510 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
514 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE,
516 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
522 if (ufs_qcom_cap_qunipro(host))
524 * set unipro core clock cycles to 150 & clear clock
527 err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba,
531 * Some UFS devices (and may be host) have issues if LCC is
532 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
533 * before link startup which will make sure that both host
534 * and device TX LCC are disabled once link startup is
537 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41)
538 err = ufshcd_dme_set(hba,
539 UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE),
544 ufs_qcom_link_startup_post_change(hba);
554 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
556 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
557 struct phy *phy = host->generic_phy;
560 if (ufs_qcom_is_link_off(hba)) {
562 * Disable the tx/rx lane symbol clocks before PHY is
563 * powered down as the PLL source should be disabled
564 * after downstream clocks are disabled.
566 ufs_qcom_disable_lane_clks(host);
569 /* Assert PHY soft reset */
570 ufs_qcom_assert_reset(hba);
575 * If UniPro link is not active, PHY ref_clk, main PHY analog power
576 * rail and low noise analog power rail for PLL can be switched off.
578 if (!ufs_qcom_is_link_active(hba)) {
579 ufs_qcom_disable_lane_clks(host);
587 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
589 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
590 struct phy *phy = host->generic_phy;
593 err = phy_power_on(phy);
595 dev_err(hba->dev, "%s: failed enabling regs, err = %d\n",
600 err = ufs_qcom_enable_lane_clks(host);
604 hba->is_sys_suspended = false;
610 struct ufs_qcom_dev_params {
611 u32 pwm_rx_gear; /* pwm rx gear to work in */
612 u32 pwm_tx_gear; /* pwm tx gear to work in */
613 u32 hs_rx_gear; /* hs rx gear to work in */
614 u32 hs_tx_gear; /* hs tx gear to work in */
615 u32 rx_lanes; /* number of rx lanes */
616 u32 tx_lanes; /* number of tx lanes */
617 u32 rx_pwr_pwm; /* rx pwm working pwr */
618 u32 tx_pwr_pwm; /* tx pwm working pwr */
619 u32 rx_pwr_hs; /* rx hs working pwr */
620 u32 tx_pwr_hs; /* tx hs working pwr */
621 u32 hs_rate; /* rate A/B to work in HS */
622 u32 desired_working_mode;
625 static int ufs_qcom_get_pwr_dev_param(struct ufs_qcom_dev_params *qcom_param,
626 struct ufs_pa_layer_attr *dev_max,
627 struct ufs_pa_layer_attr *agreed_pwr)
631 bool is_dev_sup_hs = false;
632 bool is_qcom_max_hs = false;
634 if (dev_max->pwr_rx == FAST_MODE)
635 is_dev_sup_hs = true;
637 if (qcom_param->desired_working_mode == FAST) {
638 is_qcom_max_hs = true;
639 min_qcom_gear = min_t(u32, qcom_param->hs_rx_gear,
640 qcom_param->hs_tx_gear);
642 min_qcom_gear = min_t(u32, qcom_param->pwm_rx_gear,
643 qcom_param->pwm_tx_gear);
647 * device doesn't support HS but qcom_param->desired_working_mode is
648 * HS, thus device and qcom_param don't agree
650 if (!is_dev_sup_hs && is_qcom_max_hs) {
651 pr_err("%s: failed to agree on power mode (device doesn't support HS but requested power is HS)\n",
654 } else if (is_dev_sup_hs && is_qcom_max_hs) {
656 * since device supports HS, it supports FAST_MODE.
657 * since qcom_param->desired_working_mode is also HS
658 * then final decision (FAST/FASTAUTO) is done according
659 * to qcom_params as it is the restricting factor
661 agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
662 qcom_param->rx_pwr_hs;
665 * here qcom_param->desired_working_mode is PWM.
666 * it doesn't matter whether device supports HS or PWM,
667 * in both cases qcom_param->desired_working_mode will
670 agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
671 qcom_param->rx_pwr_pwm;
675 * we would like tx to work in the minimum number of lanes
676 * between device capability and vendor preferences.
677 * the same decision will be made for rx
679 agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,
680 qcom_param->tx_lanes);
681 agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,
682 qcom_param->rx_lanes);
684 /* device maximum gear is the minimum between device rx and tx gears */
685 min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
688 * if both device capabilities and vendor pre-defined preferences are
689 * both HS or both PWM then set the minimum gear to be the chosen
691 * if one is PWM and one is HS then the one that is PWM get to decide
692 * what is the gear, as it is the one that also decided previously what
693 * pwr the device will be configured to.
695 if ((is_dev_sup_hs && is_qcom_max_hs) ||
696 (!is_dev_sup_hs && !is_qcom_max_hs))
697 agreed_pwr->gear_rx = agreed_pwr->gear_tx =
698 min_t(u32, min_dev_gear, min_qcom_gear);
699 else if (!is_dev_sup_hs)
700 agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_dev_gear;
702 agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_qcom_gear;
704 agreed_pwr->hs_rate = qcom_param->hs_rate;
708 #ifdef CONFIG_MSM_BUS_SCALING
709 static int ufs_qcom_get_bus_vote(struct ufs_qcom_host *host,
710 const char *speed_mode)
712 struct device *dev = host->hba->dev;
713 struct device_node *np = dev->of_node;
715 const char *key = "qcom,bus-vector-names";
722 if (host->bus_vote.is_max_bw_needed && !!strcmp(speed_mode, "MIN"))
723 err = of_property_match_string(np, key, "MAX");
725 err = of_property_match_string(np, key, speed_mode);
729 dev_err(dev, "%s: Invalid %s mode %d\n",
730 __func__, speed_mode, err);
734 static void ufs_qcom_get_speed_mode(struct ufs_pa_layer_attr *p, char *result)
736 int gear = max_t(u32, p->gear_rx, p->gear_tx);
737 int lanes = max_t(u32, p->lane_rx, p->lane_tx);
740 /* default to PWM Gear 1, Lane 1 if power mode is not initialized */
747 if (!p->pwr_rx && !p->pwr_tx) {
749 snprintf(result, BUS_VECTOR_NAME_LEN, "MIN");
750 } else if (p->pwr_rx == FAST_MODE || p->pwr_rx == FASTAUTO_MODE ||
751 p->pwr_tx == FAST_MODE || p->pwr_tx == FASTAUTO_MODE) {
753 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_R%s_G%d_L%d", "HS",
754 p->hs_rate == PA_HS_MODE_B ? "B" : "A", gear, lanes);
757 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_G%d_L%d",
762 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
766 if (vote != host->bus_vote.curr_vote) {
767 err = msm_bus_scale_client_update_request(
768 host->bus_vote.client_handle, vote);
770 dev_err(host->hba->dev,
771 "%s: msm_bus_scale_client_update_request() failed: bus_client_handle=0x%x, vote=%d, err=%d\n",
772 __func__, host->bus_vote.client_handle,
777 host->bus_vote.curr_vote = vote;
783 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
787 char mode[BUS_VECTOR_NAME_LEN];
789 ufs_qcom_get_speed_mode(&host->dev_req_params, mode);
791 vote = ufs_qcom_get_bus_vote(host, mode);
793 err = ufs_qcom_set_bus_vote(host, vote);
798 dev_err(host->hba->dev, "%s: failed %d\n", __func__, err);
800 host->bus_vote.saved_vote = vote;
805 show_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
808 struct ufs_hba *hba = dev_get_drvdata(dev);
809 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
811 return snprintf(buf, PAGE_SIZE, "%u\n",
812 host->bus_vote.is_max_bw_needed);
816 store_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
817 const char *buf, size_t count)
819 struct ufs_hba *hba = dev_get_drvdata(dev);
820 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
823 if (!kstrtou32(buf, 0, &value)) {
824 host->bus_vote.is_max_bw_needed = !!value;
825 ufs_qcom_update_bus_bw_vote(host);
831 static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
834 struct msm_bus_scale_pdata *bus_pdata;
835 struct device *dev = host->hba->dev;
836 struct platform_device *pdev = to_platform_device(dev);
837 struct device_node *np = dev->of_node;
839 bus_pdata = msm_bus_cl_get_pdata(pdev);
841 dev_err(dev, "%s: failed to get bus vectors\n", __func__);
846 err = of_property_count_strings(np, "qcom,bus-vector-names");
847 if (err < 0 || err != bus_pdata->num_usecases) {
848 dev_err(dev, "%s: qcom,bus-vector-names not specified correctly %d\n",
853 host->bus_vote.client_handle = msm_bus_scale_register_client(bus_pdata);
854 if (!host->bus_vote.client_handle) {
855 dev_err(dev, "%s: msm_bus_scale_register_client failed\n",
861 /* cache the vote index for minimum and maximum bandwidth */
862 host->bus_vote.min_bw_vote = ufs_qcom_get_bus_vote(host, "MIN");
863 host->bus_vote.max_bw_vote = ufs_qcom_get_bus_vote(host, "MAX");
865 host->bus_vote.max_bus_bw.show = show_ufs_to_mem_max_bus_bw;
866 host->bus_vote.max_bus_bw.store = store_ufs_to_mem_max_bus_bw;
867 sysfs_attr_init(&host->bus_vote.max_bus_bw.attr);
868 host->bus_vote.max_bus_bw.attr.name = "max_bus_bw";
869 host->bus_vote.max_bus_bw.attr.mode = S_IRUGO | S_IWUSR;
870 err = device_create_file(dev, &host->bus_vote.max_bus_bw);
874 #else /* CONFIG_MSM_BUS_SCALING */
875 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
880 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
885 static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
889 #endif /* CONFIG_MSM_BUS_SCALING */
891 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
893 if (host->dev_ref_clk_ctrl_mmio &&
894 (enable ^ host->is_dev_ref_clk_enabled)) {
895 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
898 temp |= host->dev_ref_clk_en_mask;
900 temp &= ~host->dev_ref_clk_en_mask;
903 * If we are here to disable this clock it might be immediately
904 * after entering into hibern8 in which case we need to make
905 * sure that device ref_clk is active at least 1us after the
911 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
914 * Make sure the write to ref_clk reaches the destination and
915 * not stored in a Write Buffer (WB).
917 readl(host->dev_ref_clk_ctrl_mmio);
920 * If we call hibern8 exit after this, we need to make sure that
921 * device ref_clk is stable for at least 1us before the hibern8
927 host->is_dev_ref_clk_enabled = enable;
931 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
932 enum ufs_notify_change_status status,
933 struct ufs_pa_layer_attr *dev_max_params,
934 struct ufs_pa_layer_attr *dev_req_params)
937 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
938 struct phy *phy = host->generic_phy;
939 struct ufs_qcom_dev_params ufs_qcom_cap;
943 if (!dev_req_params) {
944 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
951 ufs_qcom_cap.tx_lanes = UFS_QCOM_LIMIT_NUM_LANES_TX;
952 ufs_qcom_cap.rx_lanes = UFS_QCOM_LIMIT_NUM_LANES_RX;
953 ufs_qcom_cap.hs_rx_gear = UFS_QCOM_LIMIT_HSGEAR_RX;
954 ufs_qcom_cap.hs_tx_gear = UFS_QCOM_LIMIT_HSGEAR_TX;
955 ufs_qcom_cap.pwm_rx_gear = UFS_QCOM_LIMIT_PWMGEAR_RX;
956 ufs_qcom_cap.pwm_tx_gear = UFS_QCOM_LIMIT_PWMGEAR_TX;
957 ufs_qcom_cap.rx_pwr_pwm = UFS_QCOM_LIMIT_RX_PWR_PWM;
958 ufs_qcom_cap.tx_pwr_pwm = UFS_QCOM_LIMIT_TX_PWR_PWM;
959 ufs_qcom_cap.rx_pwr_hs = UFS_QCOM_LIMIT_RX_PWR_HS;
960 ufs_qcom_cap.tx_pwr_hs = UFS_QCOM_LIMIT_TX_PWR_HS;
961 ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
962 ufs_qcom_cap.desired_working_mode =
963 UFS_QCOM_LIMIT_DESIRED_MODE;
965 if (host->hw_ver.major == 0x1) {
967 * HS-G3 operations may not reliably work on legacy QCOM
968 * UFS host controller hardware even though capability
969 * exchange during link startup phase may end up
970 * negotiating maximum supported gear as G3.
971 * Hence downgrade the maximum supported gear to HS-G2.
973 if (ufs_qcom_cap.hs_tx_gear > UFS_HS_G2)
974 ufs_qcom_cap.hs_tx_gear = UFS_HS_G2;
975 if (ufs_qcom_cap.hs_rx_gear > UFS_HS_G2)
976 ufs_qcom_cap.hs_rx_gear = UFS_HS_G2;
979 ret = ufs_qcom_get_pwr_dev_param(&ufs_qcom_cap,
983 pr_err("%s: failed to determine capabilities\n",
988 /* enable the device ref clock before changing to HS mode */
989 if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
990 ufshcd_is_hs_mode(dev_req_params))
991 ufs_qcom_dev_ref_clk_ctrl(host, true);
994 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
995 dev_req_params->pwr_rx,
996 dev_req_params->hs_rate, false)) {
997 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
1000 * we return error code at the end of the routine,
1001 * but continue to configure UFS_PHY_TX_LANE_ENABLE
1002 * and bus voting as usual
1007 val = ~(MAX_U32 << dev_req_params->lane_tx);
1008 res = ufs_qcom_phy_set_tx_lane_enable(phy, val);
1010 dev_err(hba->dev, "%s: ufs_qcom_phy_set_tx_lane_enable() failed res = %d\n",
1015 /* cache the power mode parameters to use internally */
1016 memcpy(&host->dev_req_params,
1017 dev_req_params, sizeof(*dev_req_params));
1018 ufs_qcom_update_bus_bw_vote(host);
1020 /* disable the device ref clock if entered PWM mode */
1021 if (ufshcd_is_hs_mode(&hba->pwr_info) &&
1022 !ufshcd_is_hs_mode(dev_req_params))
1023 ufs_qcom_dev_ref_clk_ctrl(host, false);
1033 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
1036 u32 pa_vs_config_reg1;
1038 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
1039 &pa_vs_config_reg1);
1043 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
1044 err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
1045 (pa_vs_config_reg1 | (1 << 12)));
1051 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
1055 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)
1056 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
1061 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
1063 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1065 if (host->hw_ver.major == 0x1)
1066 return UFSHCI_VERSION_11;
1068 return UFSHCI_VERSION_20;
1072 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
1073 * @hba: host controller instance
1075 * QCOM UFS host controller might have some non standard behaviours (quirks)
1076 * than what is specified by UFSHCI specification. Advertise all such
1077 * quirks to standard UFS host controller driver so standard takes them into
1080 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
1082 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1084 if (host->hw_ver.major == 0x01) {
1085 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
1086 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP
1087 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE;
1089 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001)
1090 hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR;
1092 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
1095 if (host->hw_ver.major == 0x2) {
1096 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
1098 if (!ufs_qcom_cap_qunipro(host))
1099 /* Legacy UniPro mode still need following quirks */
1100 hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
1101 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
1102 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP);
1106 static void ufs_qcom_set_caps(struct ufs_hba *hba)
1108 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1110 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
1111 hba->caps |= UFSHCD_CAP_CLK_SCALING;
1112 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
1114 if (host->hw_ver.major >= 0x2) {
1115 host->caps = UFS_QCOM_CAP_QUNIPRO |
1116 UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE;
1121 * ufs_qcom_setup_clocks - enables/disable clocks
1122 * @hba: host controller instance
1123 * @on: If true, enable clocks else disable them.
1124 * @status: PRE_CHANGE or POST_CHANGE notify
1126 * Returns 0 on success, non-zero on failure.
1128 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
1129 enum ufs_notify_change_status status)
1131 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1136 * In case ufs_qcom_init() is not yet done, simply ignore.
1137 * This ufs_qcom_setup_clocks() shall be called from
1138 * ufs_qcom_init() after init is done.
1143 if (on && (status == POST_CHANGE)) {
1144 phy_power_on(host->generic_phy);
1146 /* enable the device ref clock for HS mode*/
1147 if (ufshcd_is_hs_mode(&hba->pwr_info))
1148 ufs_qcom_dev_ref_clk_ctrl(host, true);
1149 vote = host->bus_vote.saved_vote;
1150 if (vote == host->bus_vote.min_bw_vote)
1151 ufs_qcom_update_bus_bw_vote(host);
1153 } else if (!on && (status == PRE_CHANGE)) {
1154 if (!ufs_qcom_is_link_active(hba)) {
1155 /* disable device ref_clk */
1156 ufs_qcom_dev_ref_clk_ctrl(host, false);
1158 /* powering off PHY during aggressive clk gating */
1159 phy_power_off(host->generic_phy);
1162 vote = host->bus_vote.min_bw_vote;
1165 err = ufs_qcom_set_bus_vote(host, vote);
1167 dev_err(hba->dev, "%s: set bus vote failed %d\n",
1173 #define ANDROID_BOOT_DEV_MAX 30
1174 static char android_boot_dev[ANDROID_BOOT_DEV_MAX];
1177 static int __init get_android_boot_dev(char *str)
1179 strlcpy(android_boot_dev, str, ANDROID_BOOT_DEV_MAX);
1182 __setup("androidboot.bootdevice=", get_android_boot_dev);
1186 * ufs_qcom_init - bind phy with controller
1187 * @hba: host controller instance
1189 * Binds PHY with controller and powers up PHY enabling clocks
1192 * Returns -EPROBE_DEFER if binding fails, returns negative error
1193 * on phy power up failure and returns zero on success.
1195 static int ufs_qcom_init(struct ufs_hba *hba)
1198 struct device *dev = hba->dev;
1199 struct platform_device *pdev = to_platform_device(dev);
1200 struct ufs_qcom_host *host;
1201 struct resource *res;
1203 if (strlen(android_boot_dev) && strcmp(android_boot_dev, dev_name(dev)))
1206 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
1209 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
1213 /* Make a two way bind between the qcom host and the hba */
1215 ufshcd_set_variant(hba, host);
1218 * voting/devoting device ref_clk source is time consuming hence
1219 * skip devoting it during aggressive clock gating. This clock
1220 * will still be gated off during runtime suspend.
1222 host->generic_phy = devm_phy_get(dev, "ufsphy");
1224 if (host->generic_phy == ERR_PTR(-EPROBE_DEFER)) {
1226 * UFS driver might be probed before the phy driver does.
1227 * In that case we would like to return EPROBE_DEFER code.
1229 err = -EPROBE_DEFER;
1230 dev_warn(dev, "%s: required phy device. hasn't probed yet. err = %d\n",
1232 goto out_variant_clear;
1233 } else if (IS_ERR(host->generic_phy)) {
1234 err = PTR_ERR(host->generic_phy);
1235 dev_err(dev, "%s: PHY get failed %d\n", __func__, err);
1236 goto out_variant_clear;
1239 err = ufs_qcom_bus_register(host);
1241 goto out_variant_clear;
1243 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1244 &host->hw_ver.minor, &host->hw_ver.step);
1247 * for newer controllers, device reference clock control bit has
1248 * moved inside UFS controller register address space itself.
1250 if (host->hw_ver.major >= 0x02) {
1251 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1252 host->dev_ref_clk_en_mask = BIT(26);
1254 /* "dev_ref_clk_ctrl_mem" is optional resource */
1255 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1257 host->dev_ref_clk_ctrl_mmio =
1258 devm_ioremap_resource(dev, res);
1259 if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) {
1261 "%s: could not map dev_ref_clk_ctrl_mmio, err %ld\n",
1263 PTR_ERR(host->dev_ref_clk_ctrl_mmio));
1264 host->dev_ref_clk_ctrl_mmio = NULL;
1266 host->dev_ref_clk_en_mask = BIT(5);
1270 /* update phy revision information before calling phy_init() */
1271 ufs_qcom_phy_save_controller_version(host->generic_phy,
1272 host->hw_ver.major, host->hw_ver.minor, host->hw_ver.step);
1274 err = ufs_qcom_init_lane_clks(host);
1276 goto out_variant_clear;
1278 ufs_qcom_set_caps(hba);
1279 ufs_qcom_advertise_quirks(hba);
1281 ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
1283 if (hba->dev->id < MAX_UFS_QCOM_HOSTS)
1284 ufs_qcom_hosts[hba->dev->id] = host;
1286 host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN;
1287 ufs_qcom_get_default_testbus_cfg(host);
1288 err = ufs_qcom_testbus_config(host);
1290 dev_warn(dev, "%s: failed to configure the testbus %d\n",
1298 ufshcd_set_variant(hba, NULL);
1303 static void ufs_qcom_exit(struct ufs_hba *hba)
1305 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1307 ufs_qcom_disable_lane_clks(host);
1308 phy_power_off(host->generic_phy);
1309 phy_exit(host->generic_phy);
1312 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
1316 u32 core_clk_ctrl_reg;
1318 if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK)
1321 err = ufshcd_dme_get(hba,
1322 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1323 &core_clk_ctrl_reg);
1327 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
1328 core_clk_ctrl_reg |= clk_cycles;
1330 /* Clear CORE_CLK_DIV_EN */
1331 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1333 err = ufshcd_dme_set(hba,
1334 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1340 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
1342 /* nothing to do as of now */
1346 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1348 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1350 if (!ufs_qcom_cap_qunipro(host))
1353 /* set unipro core clock cycles to 150 and clear clock divider */
1354 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150);
1357 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1359 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1361 u32 core_clk_ctrl_reg;
1363 if (!ufs_qcom_cap_qunipro(host))
1366 err = ufshcd_dme_get(hba,
1367 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1368 &core_clk_ctrl_reg);
1370 /* make sure CORE_CLK_DIV_EN is cleared */
1372 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1373 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1374 err = ufshcd_dme_set(hba,
1375 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1382 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
1384 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1386 if (!ufs_qcom_cap_qunipro(host))
1389 /* set unipro core clock cycles to 75 and clear clock divider */
1390 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75);
1393 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
1394 bool scale_up, enum ufs_notify_change_status status)
1396 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1397 struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;
1400 if (status == PRE_CHANGE) {
1402 err = ufs_qcom_clk_scale_up_pre_change(hba);
1404 err = ufs_qcom_clk_scale_down_pre_change(hba);
1407 err = ufs_qcom_clk_scale_up_post_change(hba);
1409 err = ufs_qcom_clk_scale_down_post_change(hba);
1411 if (err || !dev_req_params)
1414 ufs_qcom_cfg_timers(hba,
1415 dev_req_params->gear_rx,
1416 dev_req_params->pwr_rx,
1417 dev_req_params->hs_rate,
1419 ufs_qcom_update_bus_bw_vote(host);
1426 static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba,
1427 void *priv, void (*print_fn)(struct ufs_hba *hba,
1428 int offset, int num_regs, const char *str, void *priv))
1431 struct ufs_qcom_host *host;
1433 if (unlikely(!hba)) {
1434 pr_err("%s: hba is NULL\n", __func__);
1437 if (unlikely(!print_fn)) {
1438 dev_err(hba->dev, "%s: print_fn is NULL\n", __func__);
1442 host = ufshcd_get_variant(hba);
1443 if (!(host->dbg_print_en & UFS_QCOM_DBG_PRINT_REGS_EN))
1446 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1447 print_fn(hba, reg, 44, "UFS_UFS_DBG_RD_REG_OCSC ", priv);
1449 reg = ufshcd_readl(hba, REG_UFS_CFG1);
1450 reg |= UTP_DBG_RAMS_EN;
1451 ufshcd_writel(hba, reg, REG_UFS_CFG1);
1453 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1454 print_fn(hba, reg, 32, "UFS_UFS_DBG_RD_EDTL_RAM ", priv);
1456 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1457 print_fn(hba, reg, 128, "UFS_UFS_DBG_RD_DESC_RAM ", priv);
1459 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1460 print_fn(hba, reg, 64, "UFS_UFS_DBG_RD_PRDT_RAM ", priv);
1462 /* clear bit 17 - UTP_DBG_RAMS_EN */
1463 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1465 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1466 print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UAWM ", priv);
1468 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1469 print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UARM ", priv);
1471 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1472 print_fn(hba, reg, 48, "UFS_DBG_RD_REG_TXUC ", priv);
1474 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1475 print_fn(hba, reg, 27, "UFS_DBG_RD_REG_RXUC ", priv);
1477 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1478 print_fn(hba, reg, 19, "UFS_DBG_RD_REG_DFC ", priv);
1480 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1481 print_fn(hba, reg, 34, "UFS_DBG_RD_REG_TRLUT ", priv);
1483 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1484 print_fn(hba, reg, 9, "UFS_DBG_RD_REG_TMRLUT ", priv);
1487 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1489 if (host->dbg_print_en & UFS_QCOM_DBG_PRINT_TEST_BUS_EN) {
1490 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1491 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1492 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1494 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 0, REG_UFS_CFG1);
1495 ufshcd_rmwl(host->hba, TEST_BUS_EN, 0, REG_UFS_CFG1);
1499 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1501 /* provide a legal default configuration */
1502 host->testbus.select_major = TSTBUS_UNIPRO;
1503 host->testbus.select_minor = 37;
1506 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1508 if (host->testbus.select_major >= TSTBUS_MAX) {
1509 dev_err(host->hba->dev,
1510 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1511 __func__, host->testbus.select_major);
1518 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1522 u32 mask = TEST_BUS_SUB_SEL_MASK;
1527 if (!ufs_qcom_testbus_cfg_is_ok(host))
1530 switch (host->testbus.select_major) {
1532 reg = UFS_TEST_BUS_CTRL_0;
1536 reg = UFS_TEST_BUS_CTRL_0;
1540 reg = UFS_TEST_BUS_CTRL_0;
1544 reg = UFS_TEST_BUS_CTRL_0;
1548 reg = UFS_TEST_BUS_CTRL_1;
1552 reg = UFS_TEST_BUS_CTRL_1;
1556 reg = UFS_TEST_BUS_CTRL_1;
1560 reg = UFS_TEST_BUS_CTRL_1;
1563 case TSTBUS_WRAPPER:
1564 reg = UFS_TEST_BUS_CTRL_2;
1567 case TSTBUS_COMBINED:
1568 reg = UFS_TEST_BUS_CTRL_2;
1571 case TSTBUS_UTP_HCI:
1572 reg = UFS_TEST_BUS_CTRL_2;
1576 reg = UFS_UNIPRO_CFG;
1581 * No need for a default case, since
1582 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1587 ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1588 (u32)host->testbus.select_major << 19,
1590 ufshcd_rmwl(host->hba, mask,
1591 (u32)host->testbus.select_minor << offset,
1593 ufs_qcom_enable_test_bus(host);
1595 * Make sure the test bus configuration is
1596 * committed before returning.
1603 static void ufs_qcom_testbus_read(struct ufs_hba *hba)
1605 ufshcd_dump_regs(hba, UFS_TEST_BUS, 4, "UFS_TEST_BUS ");
1608 static void ufs_qcom_print_unipro_testbus(struct ufs_hba *hba)
1610 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1611 u32 *testbus = NULL;
1612 int i, nminor = 256, testbus_len = nminor * sizeof(u32);
1614 testbus = kmalloc(testbus_len, GFP_KERNEL);
1618 host->testbus.select_major = TSTBUS_UNIPRO;
1619 for (i = 0; i < nminor; i++) {
1620 host->testbus.select_minor = i;
1621 ufs_qcom_testbus_config(host);
1622 testbus[i] = ufshcd_readl(hba, UFS_TEST_BUS);
1624 print_hex_dump(KERN_ERR, "UNIPRO_TEST_BUS ", DUMP_PREFIX_OFFSET,
1625 16, 4, testbus, testbus_len, false);
1629 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1631 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
1632 "HCI Vendor Specific Registers ");
1634 /* sleep a bit intermittently as we are dumping too much data */
1635 ufs_qcom_print_hw_debug_reg_all(hba, NULL, ufs_qcom_dump_regs_wrapper);
1637 ufs_qcom_testbus_read(hba);
1639 ufs_qcom_print_unipro_testbus(hba);
1644 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1646 * The variant operations configure the necessary controller and PHY
1647 * handshake during initialization.
1649 static struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1651 .init = ufs_qcom_init,
1652 .exit = ufs_qcom_exit,
1653 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version,
1654 .clk_scale_notify = ufs_qcom_clk_scale_notify,
1655 .setup_clocks = ufs_qcom_setup_clocks,
1656 .hce_enable_notify = ufs_qcom_hce_enable_notify,
1657 .link_startup_notify = ufs_qcom_link_startup_notify,
1658 .pwr_change_notify = ufs_qcom_pwr_change_notify,
1659 .apply_dev_quirks = ufs_qcom_apply_dev_quirks,
1660 .suspend = ufs_qcom_suspend,
1661 .resume = ufs_qcom_resume,
1662 .dbg_register_dump = ufs_qcom_dump_dbg_regs,
1666 * ufs_qcom_probe - probe routine of the driver
1667 * @pdev: pointer to Platform device handle
1669 * Return zero for success and non-zero for failure
1671 static int ufs_qcom_probe(struct platform_device *pdev)
1674 struct device *dev = &pdev->dev;
1676 /* Perform generic probe */
1677 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1679 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
1685 * ufs_qcom_remove - set driver_data of the device to NULL
1686 * @pdev: pointer to platform device handle
1690 static int ufs_qcom_remove(struct platform_device *pdev)
1692 struct ufs_hba *hba = platform_get_drvdata(pdev);
1694 pm_runtime_get_sync(&(pdev)->dev);
1699 static const struct of_device_id ufs_qcom_of_match[] = {
1700 { .compatible = "qcom,ufshc"},
1703 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
1705 static const struct dev_pm_ops ufs_qcom_pm_ops = {
1706 .suspend = ufshcd_pltfrm_suspend,
1707 .resume = ufshcd_pltfrm_resume,
1708 .runtime_suspend = ufshcd_pltfrm_runtime_suspend,
1709 .runtime_resume = ufshcd_pltfrm_runtime_resume,
1710 .runtime_idle = ufshcd_pltfrm_runtime_idle,
1713 static struct platform_driver ufs_qcom_pltform = {
1714 .probe = ufs_qcom_probe,
1715 .remove = ufs_qcom_remove,
1716 .shutdown = ufshcd_pltfrm_shutdown,
1718 .name = "ufshcd-qcom",
1719 .pm = &ufs_qcom_pm_ops,
1720 .of_match_table = of_match_ptr(ufs_qcom_of_match),
1723 module_platform_driver(ufs_qcom_pltform);
1725 MODULE_LICENSE("GPL v2");