1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * skl-tplg-interface.h - Intel DSP FW private data interface
5 * Copyright (C) 2015 Intel Corp
6 * Author: Jeeja KP <jeeja.kp@intel.com>
7 * Nilofer, Samreen <samreen.nilofer@intel.com>
10 #ifndef __HDA_TPLG_INTERFACE_H__
11 #define __HDA_TPLG_INTERFACE_H__
13 #include <linux/types.h>
16 * Default types range from 0~12. type can range from 0 to 0xff
17 * SST types start at higher to avoid any overlapping in future
19 #define SKL_CONTROL_TYPE_BYTE_TLV 0x100
20 #define SKL_CONTROL_TYPE_MIC_SELECT 0x102
21 #define SKL_CONTROL_TYPE_MULTI_IO_SELECT 0x103
22 #define SKL_CONTROL_TYPE_MULTI_IO_SELECT_DMIC 0x104
24 #define HDA_SST_CFG_MAX 900 /* size of copier cfg*/
25 #define MAX_IN_QUEUE 8
26 #define MAX_OUT_QUEUE 8
28 #define SKL_UUID_STR_SZ 40
29 /* Event types goes here */
30 /* Reserve event type 0 for no event handlers */
31 enum skl_event_types {
40 * enum skl_ch_cfg - channel configuration
42 * @SKL_CH_CFG_MONO: One channel only
43 * @SKL_CH_CFG_STEREO: L & R
44 * @SKL_CH_CFG_2_1: L, R & LFE
45 * @SKL_CH_CFG_3_0: L, C & R
46 * @SKL_CH_CFG_3_1: L, C, R & LFE
47 * @SKL_CH_CFG_QUATRO: L, R, Ls & Rs
48 * @SKL_CH_CFG_4_0: L, C, R & Cs
49 * @SKL_CH_CFG_5_0: L, C, R, Ls & Rs
50 * @SKL_CH_CFG_5_1: L, C, R, Ls, Rs & LFE
51 * @SKL_CH_CFG_DUAL_MONO: One channel replicated in two
52 * @SKL_CH_CFG_I2S_DUAL_STEREO_0: Stereo(L,R) in 4 slots, 1st stream:[ L, R, -, - ]
53 * @SKL_CH_CFG_I2S_DUAL_STEREO_1: Stereo(L,R) in 4 slots, 2nd stream:[ -, -, L, R ]
54 * @SKL_CH_CFG_INVALID: Invalid
58 SKL_CH_CFG_STEREO = 1,
62 SKL_CH_CFG_QUATRO = 5,
66 SKL_CH_CFG_DUAL_MONO = 9,
67 SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10,
68 SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11,
69 SKL_CH_CFG_4_CHANNEL = 12,
73 enum skl_module_type {
74 SKL_MODULE_TYPE_MIXER = 0,
75 SKL_MODULE_TYPE_COPIER,
76 SKL_MODULE_TYPE_UPDWMIX,
77 SKL_MODULE_TYPE_SRCINT,
79 SKL_MODULE_TYPE_BASE_OUTFMT,
81 SKL_MODULE_TYPE_MIC_SELECT,
84 enum skl_core_affinity {
85 SKL_AFFINITY_CORE_0 = 0,
90 enum skl_pipe_conn_type {
91 SKL_PIPE_CONN_TYPE_NONE = 0,
92 SKL_PIPE_CONN_TYPE_FE,
96 enum skl_hw_conn_type {
104 SKL_DEVICE_DMIC = 0x1,
105 SKL_DEVICE_I2S = 0x2,
106 SKL_DEVICE_SLIMBUS = 0x3,
107 SKL_DEVICE_HDALINK = 0x4,
108 SKL_DEVICE_HDAHOST = 0x5,
113 * enum skl_interleaving - interleaving style
115 * @SKL_INTERLEAVING_PER_CHANNEL: [s1_ch1...s1_chN,...,sM_ch1...sM_chN]
116 * @SKL_INTERLEAVING_PER_SAMPLE: [s1_ch1...sM_ch1,...,s1_chN...sM_chN]
118 enum skl_interleaving {
119 SKL_INTERLEAVING_PER_CHANNEL = 0,
120 SKL_INTERLEAVING_PER_SAMPLE = 1,
123 enum skl_sample_type {
124 SKL_SAMPLE_TYPE_INT_MSB = 0,
125 SKL_SAMPLE_TYPE_INT_LSB = 1,
126 SKL_SAMPLE_TYPE_INT_SIGNED = 2,
127 SKL_SAMPLE_TYPE_INT_UNSIGNED = 3,
128 SKL_SAMPLE_TYPE_FLOAT = 4
131 enum module_pin_type {
132 /* All pins of the module takes same PCM inputs or outputs
135 SKL_PIN_TYPE_HOMOGENEOUS,
136 /* All pins of the module takes different PCM inputs or outputs
139 SKL_PIN_TYPE_HETEROGENEOUS,
142 enum skl_module_param_type {
143 SKL_PARAM_DEFAULT = 0,
149 struct skl_dfw_algo_data {
162 enum skl_tuple_type {
167 /* v4 configuration data */
169 struct skl_dfw_v4_module_pin {
174 struct skl_dfw_v4_module_fmt {
178 __u32 valid_bit_depth;
180 __u32 interleaving_style;
185 struct skl_dfw_v4_module_caps {
190 __u32 caps[HDA_SST_CFG_MAX];
193 struct skl_dfw_v4_pipe {
198 __u16 memory_pages:8;
201 struct skl_dfw_v4_module {
202 char uuid[SKL_UUID_STR_SZ];
212 __u32 max_in_queue:8;
213 __u32 max_out_queue:8;
221 __u32 hw_conn_type:4;
224 __u32 params_fixup:8;
226 __u32 input_pin_type:1;
227 __u32 output_pin_type:1;
228 __u32 is_dynamic_in_pin:1;
229 __u32 is_dynamic_out_pin:1;
233 struct skl_dfw_v4_pipe pipe;
234 struct skl_dfw_v4_module_fmt in_fmt[MAX_IN_QUEUE];
235 struct skl_dfw_v4_module_fmt out_fmt[MAX_OUT_QUEUE];
236 struct skl_dfw_v4_module_pin in_pin[MAX_IN_QUEUE];
237 struct skl_dfw_v4_module_pin out_pin[MAX_OUT_QUEUE];
238 struct skl_dfw_v4_module_caps caps;