2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef KFD_IOCTL_H_INCLUDED
24 #define KFD_IOCTL_H_INCLUDED
27 #include <linux/ioctl.h>
30 * - 1.1 - initial version
31 * - 1.3 - Add SMI events support
32 * - 1.4 - Indicate new SRAM EDC bit in device properties
34 * - 1.6 - Query clear flags in SVM get_attr API
35 * - 1.7 - Checkpoint Restore (CRIU) API
36 * - 1.8 - CRIU - Support for SDMA transfers with GTT BOs
38 #define KFD_IOCTL_MAJOR_VERSION 1
39 #define KFD_IOCTL_MINOR_VERSION 8
41 struct kfd_ioctl_get_version_args {
42 __u32 major_version; /* from KFD */
43 __u32 minor_version; /* from KFD */
46 /* For kfd_ioctl_create_queue_args.queue_type. */
47 #define KFD_IOC_QUEUE_TYPE_COMPUTE 0x0
48 #define KFD_IOC_QUEUE_TYPE_SDMA 0x1
49 #define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 0x2
50 #define KFD_IOC_QUEUE_TYPE_SDMA_XGMI 0x3
52 #define KFD_MAX_QUEUE_PERCENTAGE 100
53 #define KFD_MAX_QUEUE_PRIORITY 15
55 struct kfd_ioctl_create_queue_args {
56 __u64 ring_base_address; /* to KFD */
57 __u64 write_pointer_address; /* from KFD */
58 __u64 read_pointer_address; /* from KFD */
59 __u64 doorbell_offset; /* from KFD */
61 __u32 ring_size; /* to KFD */
62 __u32 gpu_id; /* to KFD */
63 __u32 queue_type; /* to KFD */
64 __u32 queue_percentage; /* to KFD */
65 __u32 queue_priority; /* to KFD */
66 __u32 queue_id; /* from KFD */
68 __u64 eop_buffer_address; /* to KFD */
69 __u64 eop_buffer_size; /* to KFD */
70 __u64 ctx_save_restore_address; /* to KFD */
71 __u32 ctx_save_restore_size; /* to KFD */
72 __u32 ctl_stack_size; /* to KFD */
75 struct kfd_ioctl_destroy_queue_args {
76 __u32 queue_id; /* to KFD */
80 struct kfd_ioctl_update_queue_args {
81 __u64 ring_base_address; /* to KFD */
83 __u32 queue_id; /* to KFD */
84 __u32 ring_size; /* to KFD */
85 __u32 queue_percentage; /* to KFD */
86 __u32 queue_priority; /* to KFD */
89 struct kfd_ioctl_set_cu_mask_args {
90 __u32 queue_id; /* to KFD */
91 __u32 num_cu_mask; /* to KFD */
92 __u64 cu_mask_ptr; /* to KFD */
95 struct kfd_ioctl_get_queue_wave_state_args {
96 __u64 ctl_stack_address; /* to KFD */
97 __u32 ctl_stack_used_size; /* from KFD */
98 __u32 save_area_used_size; /* from KFD */
99 __u32 queue_id; /* to KFD */
103 /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */
104 #define KFD_IOC_CACHE_POLICY_COHERENT 0
105 #define KFD_IOC_CACHE_POLICY_NONCOHERENT 1
107 struct kfd_ioctl_set_memory_policy_args {
108 __u64 alternate_aperture_base; /* to KFD */
109 __u64 alternate_aperture_size; /* to KFD */
111 __u32 gpu_id; /* to KFD */
112 __u32 default_policy; /* to KFD */
113 __u32 alternate_policy; /* to KFD */
118 * All counters are monotonic. They are used for profiling of compute jobs.
119 * The profiling is done by userspace.
121 * In case of GPU reset, the counter should not be affected.
124 struct kfd_ioctl_get_clock_counters_args {
125 __u64 gpu_clock_counter; /* from KFD */
126 __u64 cpu_clock_counter; /* from KFD */
127 __u64 system_clock_counter; /* from KFD */
128 __u64 system_clock_freq; /* from KFD */
130 __u32 gpu_id; /* to KFD */
134 struct kfd_process_device_apertures {
135 __u64 lds_base; /* from KFD */
136 __u64 lds_limit; /* from KFD */
137 __u64 scratch_base; /* from KFD */
138 __u64 scratch_limit; /* from KFD */
139 __u64 gpuvm_base; /* from KFD */
140 __u64 gpuvm_limit; /* from KFD */
141 __u32 gpu_id; /* from KFD */
146 * AMDKFD_IOC_GET_PROCESS_APERTURES is deprecated. Use
147 * AMDKFD_IOC_GET_PROCESS_APERTURES_NEW instead, which supports an
148 * unlimited number of GPUs.
150 #define NUM_OF_SUPPORTED_GPUS 7
151 struct kfd_ioctl_get_process_apertures_args {
152 struct kfd_process_device_apertures
153 process_apertures[NUM_OF_SUPPORTED_GPUS];/* from KFD */
155 /* from KFD, should be in the range [1 - NUM_OF_SUPPORTED_GPUS] */
160 struct kfd_ioctl_get_process_apertures_new_args {
161 /* User allocated. Pointer to struct kfd_process_device_apertures
162 * filled in by Kernel
164 __u64 kfd_process_device_apertures_ptr;
165 /* to KFD - indicates amount of memory present in
166 * kfd_process_device_apertures_ptr
167 * from KFD - Number of entries filled by KFD.
173 #define MAX_ALLOWED_NUM_POINTS 100
174 #define MAX_ALLOWED_AW_BUFF_SIZE 4096
175 #define MAX_ALLOWED_WAC_BUFF_SIZE 128
177 struct kfd_ioctl_dbg_register_args {
178 __u32 gpu_id; /* to KFD */
182 struct kfd_ioctl_dbg_unregister_args {
183 __u32 gpu_id; /* to KFD */
187 struct kfd_ioctl_dbg_address_watch_args {
188 __u64 content_ptr; /* a pointer to the actual content */
189 __u32 gpu_id; /* to KFD */
190 __u32 buf_size_in_bytes; /*including gpu_id and buf_size */
193 struct kfd_ioctl_dbg_wave_control_args {
194 __u64 content_ptr; /* a pointer to the actual content */
195 __u32 gpu_id; /* to KFD */
196 __u32 buf_size_in_bytes; /*including gpu_id and buf_size */
199 #define KFD_INVALID_FD 0xffffffff
201 /* Matching HSA_EVENTTYPE */
202 #define KFD_IOC_EVENT_SIGNAL 0
203 #define KFD_IOC_EVENT_NODECHANGE 1
204 #define KFD_IOC_EVENT_DEVICESTATECHANGE 2
205 #define KFD_IOC_EVENT_HW_EXCEPTION 3
206 #define KFD_IOC_EVENT_SYSTEM_EVENT 4
207 #define KFD_IOC_EVENT_DEBUG_EVENT 5
208 #define KFD_IOC_EVENT_PROFILE_EVENT 6
209 #define KFD_IOC_EVENT_QUEUE_EVENT 7
210 #define KFD_IOC_EVENT_MEMORY 8
212 #define KFD_IOC_WAIT_RESULT_COMPLETE 0
213 #define KFD_IOC_WAIT_RESULT_TIMEOUT 1
214 #define KFD_IOC_WAIT_RESULT_FAIL 2
216 #define KFD_SIGNAL_EVENT_LIMIT 4096
218 /* For kfd_event_data.hw_exception_data.reset_type. */
219 #define KFD_HW_EXCEPTION_WHOLE_GPU_RESET 0
220 #define KFD_HW_EXCEPTION_PER_ENGINE_RESET 1
222 /* For kfd_event_data.hw_exception_data.reset_cause. */
223 #define KFD_HW_EXCEPTION_GPU_HANG 0
224 #define KFD_HW_EXCEPTION_ECC 1
226 /* For kfd_hsa_memory_exception_data.ErrorType */
227 #define KFD_MEM_ERR_NO_RAS 0
228 #define KFD_MEM_ERR_SRAM_ECC 1
229 #define KFD_MEM_ERR_POISON_CONSUMED 2
230 #define KFD_MEM_ERR_GPU_HANG 3
232 struct kfd_ioctl_create_event_args {
233 __u64 event_page_offset; /* from KFD */
234 __u32 event_trigger_data; /* from KFD - signal events only */
235 __u32 event_type; /* to KFD */
236 __u32 auto_reset; /* to KFD */
237 __u32 node_id; /* to KFD - only valid for certain
239 __u32 event_id; /* from KFD */
240 __u32 event_slot_index; /* from KFD */
243 struct kfd_ioctl_destroy_event_args {
244 __u32 event_id; /* to KFD */
248 struct kfd_ioctl_set_event_args {
249 __u32 event_id; /* to KFD */
253 struct kfd_ioctl_reset_event_args {
254 __u32 event_id; /* to KFD */
258 struct kfd_memory_exception_failure {
259 __u32 NotPresent; /* Page not present or supervisor privilege */
260 __u32 ReadOnly; /* Write access to a read-only page */
261 __u32 NoExecute; /* Execute access to a page marked NX */
262 __u32 imprecise; /* Can't determine the exact fault address */
265 /* memory exception data */
266 struct kfd_hsa_memory_exception_data {
267 struct kfd_memory_exception_failure failure;
270 __u32 ErrorType; /* 0 = no RAS error,
272 * 2 = Link_SYNFLOOD (poison),
273 * 3 = GPU hang (not attributable to a specific cause),
274 * other values reserved
278 /* hw exception data */
279 struct kfd_hsa_hw_exception_data {
287 struct kfd_event_data {
289 struct kfd_hsa_memory_exception_data memory_exception_data;
290 struct kfd_hsa_hw_exception_data hw_exception_data;
292 __u64 kfd_event_data_ext; /* pointer to an extension structure
293 for future exception types */
294 __u32 event_id; /* to KFD */
298 struct kfd_ioctl_wait_events_args {
299 __u64 events_ptr; /* pointed to struct
300 kfd_event_data array, to KFD */
301 __u32 num_events; /* to KFD */
302 __u32 wait_for_all; /* to KFD */
303 __u32 timeout; /* to KFD */
304 __u32 wait_result; /* from KFD */
307 struct kfd_ioctl_set_scratch_backing_va_args {
308 __u64 va_addr; /* to KFD */
309 __u32 gpu_id; /* to KFD */
313 struct kfd_ioctl_get_tile_config_args {
314 /* to KFD: pointer to tile array */
315 __u64 tile_config_ptr;
316 /* to KFD: pointer to macro tile array */
317 __u64 macro_tile_config_ptr;
318 /* to KFD: array size allocated by user mode
319 * from KFD: array size filled by kernel
321 __u32 num_tile_configs;
322 /* to KFD: array size allocated by user mode
323 * from KFD: array size filled by kernel
325 __u32 num_macro_tile_configs;
327 __u32 gpu_id; /* to KFD */
328 __u32 gb_addr_config; /* from KFD */
329 __u32 num_banks; /* from KFD */
330 __u32 num_ranks; /* from KFD */
331 /* struct size can be extended later if needed
332 * without breaking ABI compatibility
336 struct kfd_ioctl_set_trap_handler_args {
337 __u64 tba_addr; /* to KFD */
338 __u64 tma_addr; /* to KFD */
339 __u32 gpu_id; /* to KFD */
343 struct kfd_ioctl_acquire_vm_args {
344 __u32 drm_fd; /* to KFD */
345 __u32 gpu_id; /* to KFD */
348 /* Allocation flags: memory types */
349 #define KFD_IOC_ALLOC_MEM_FLAGS_VRAM (1 << 0)
350 #define KFD_IOC_ALLOC_MEM_FLAGS_GTT (1 << 1)
351 #define KFD_IOC_ALLOC_MEM_FLAGS_USERPTR (1 << 2)
352 #define KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL (1 << 3)
353 #define KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP (1 << 4)
354 /* Allocation flags: attributes/access options */
355 #define KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE (1 << 31)
356 #define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE (1 << 30)
357 #define KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC (1 << 29)
358 #define KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE (1 << 28)
359 #define KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM (1 << 27)
360 #define KFD_IOC_ALLOC_MEM_FLAGS_COHERENT (1 << 26)
361 #define KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED (1 << 25)
363 /* Allocate memory for later SVM (shared virtual memory) mapping.
365 * @va_addr: virtual address of the memory to be allocated
366 * all later mappings on all GPUs will use this address
367 * @size: size in bytes
368 * @handle: buffer handle returned to user mode, used to refer to
369 * this allocation for mapping, unmapping and freeing
370 * @mmap_offset: for CPU-mapping the allocation by mmapping a render node
371 * for userptrs this is overloaded to specify the CPU address
372 * @gpu_id: device identifier
373 * @flags: memory type and attributes. See KFD_IOC_ALLOC_MEM_FLAGS above
375 struct kfd_ioctl_alloc_memory_of_gpu_args {
376 __u64 va_addr; /* to KFD */
377 __u64 size; /* to KFD */
378 __u64 handle; /* from KFD */
379 __u64 mmap_offset; /* to KFD (userptr), from KFD (mmap offset) */
380 __u32 gpu_id; /* to KFD */
384 /* Free memory allocated with kfd_ioctl_alloc_memory_of_gpu
386 * @handle: memory handle returned by alloc
388 struct kfd_ioctl_free_memory_of_gpu_args {
389 __u64 handle; /* to KFD */
392 /* Map memory to one or more GPUs
394 * @handle: memory handle returned by alloc
395 * @device_ids_array_ptr: array of gpu_ids (__u32 per device)
396 * @n_devices: number of devices in the array
397 * @n_success: number of devices mapped successfully
399 * @n_success returns information to the caller how many devices from
400 * the start of the array have mapped the buffer successfully. It can
401 * be passed into a subsequent retry call to skip those devices. For
402 * the first call the caller should initialize it to 0.
404 * If the ioctl completes with return code 0 (success), n_success ==
407 struct kfd_ioctl_map_memory_to_gpu_args {
408 __u64 handle; /* to KFD */
409 __u64 device_ids_array_ptr; /* to KFD */
410 __u32 n_devices; /* to KFD */
411 __u32 n_success; /* to/from KFD */
414 /* Unmap memory from one or more GPUs
416 * same arguments as for mapping
418 struct kfd_ioctl_unmap_memory_from_gpu_args {
419 __u64 handle; /* to KFD */
420 __u64 device_ids_array_ptr; /* to KFD */
421 __u32 n_devices; /* to KFD */
422 __u32 n_success; /* to/from KFD */
425 /* Allocate GWS for specific queue
427 * @queue_id: queue's id that GWS is allocated for
428 * @num_gws: how many GWS to allocate
429 * @first_gws: index of the first GWS allocated.
430 * only support contiguous GWS allocation
432 struct kfd_ioctl_alloc_queue_gws_args {
433 __u32 queue_id; /* to KFD */
434 __u32 num_gws; /* to KFD */
435 __u32 first_gws; /* from KFD */
439 struct kfd_ioctl_get_dmabuf_info_args {
440 __u64 size; /* from KFD */
441 __u64 metadata_ptr; /* to KFD */
442 __u32 metadata_size; /* to KFD (space allocated by user)
443 * from KFD (actual metadata size)
445 __u32 gpu_id; /* from KFD */
446 __u32 flags; /* from KFD (KFD_IOC_ALLOC_MEM_FLAGS) */
447 __u32 dmabuf_fd; /* to KFD */
450 struct kfd_ioctl_import_dmabuf_args {
451 __u64 va_addr; /* to KFD */
452 __u64 handle; /* from KFD */
453 __u32 gpu_id; /* to KFD */
454 __u32 dmabuf_fd; /* to KFD */
458 * KFD SMI(System Management Interface) events
461 KFD_SMI_EVENT_NONE = 0, /* not used */
462 KFD_SMI_EVENT_VMFAULT = 1, /* event start counting at 1 */
463 KFD_SMI_EVENT_THERMAL_THROTTLE = 2,
464 KFD_SMI_EVENT_GPU_PRE_RESET = 3,
465 KFD_SMI_EVENT_GPU_POST_RESET = 4,
468 #define KFD_SMI_EVENT_MASK_FROM_INDEX(i) (1ULL << ((i) - 1))
469 #define KFD_SMI_EVENT_MSG_SIZE 96
471 struct kfd_ioctl_smi_events_args {
472 __u32 gpuid; /* to KFD */
473 __u32 anon_fd; /* from KFD */
476 /**************************************************************************************************
477 * CRIU IOCTLs (Checkpoint Restore In Userspace)
479 * When checkpointing a process, the userspace application will perform:
480 * 1. PROCESS_INFO op to determine current process information. This pauses execution and evicts
482 * 2. CHECKPOINT op to checkpoint process contents (BOs, queues, events, svm-ranges)
483 * 3. UNPAUSE op to un-evict all the queues
485 * When restoring a process, the CRIU userspace application will perform:
487 * 1. RESTORE op to restore process contents
488 * 2. RESUME op to start the process
490 * Note: Queues are forced into an evicted state after a successful PROCESS_INFO. User
491 * application needs to perform an UNPAUSE operation after calling PROCESS_INFO.
495 KFD_CRIU_OP_PROCESS_INFO,
496 KFD_CRIU_OP_CHECKPOINT,
503 * kfd_ioctl_criu_args - Arguments perform CRIU operation
504 * @devices: [in/out] User pointer to memory location for devices information.
505 * This is an array of type kfd_criu_device_bucket.
506 * @bos: [in/out] User pointer to memory location for BOs information
507 * This is an array of type kfd_criu_bo_bucket.
508 * @priv_data: [in/out] User pointer to memory location for private data
509 * @priv_data_size: [in/out] Size of priv_data in bytes
510 * @num_devices: [in/out] Number of GPUs used by process. Size of @devices array.
511 * @num_bos [in/out] Number of BOs used by process. Size of @bos array.
512 * @num_objects: [in/out] Number of objects used by process. Objects are opaque to
514 * @pid: [in/out] PID of the process being checkpointed
515 * @op [in] Type of operation (kfd_criu_op)
517 * Return: 0 on success, -errno on failure
519 struct kfd_ioctl_criu_args {
520 __u64 devices; /* Used during ops: CHECKPOINT, RESTORE */
521 __u64 bos; /* Used during ops: CHECKPOINT, RESTORE */
522 __u64 priv_data; /* Used during ops: CHECKPOINT, RESTORE */
523 __u64 priv_data_size; /* Used during ops: PROCESS_INFO, RESTORE */
524 __u32 num_devices; /* Used during ops: PROCESS_INFO, RESTORE */
525 __u32 num_bos; /* Used during ops: PROCESS_INFO, RESTORE */
526 __u32 num_objects; /* Used during ops: PROCESS_INFO, RESTORE */
527 __u32 pid; /* Used during ops: PROCESS_INFO, RESUME */
531 struct kfd_criu_device_bucket {
538 struct kfd_criu_bo_bucket {
542 __u64 restored_offset; /* During restore, updated offset for BO */
543 __u32 gpu_id; /* This is the user_gpu_id */
549 /* CRIU IOCTLs - END */
550 /**************************************************************************************************/
552 /* Register offset inside the remapped mmio page
554 enum kfd_mmio_remap {
555 KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL = 0,
556 KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4,
559 /* Guarantee host access to memory */
560 #define KFD_IOCTL_SVM_FLAG_HOST_ACCESS 0x00000001
561 /* Fine grained coherency between all devices with access */
562 #define KFD_IOCTL_SVM_FLAG_COHERENT 0x00000002
563 /* Use any GPU in same hive as preferred device */
564 #define KFD_IOCTL_SVM_FLAG_HIVE_LOCAL 0x00000004
565 /* GPUs only read, allows replication */
566 #define KFD_IOCTL_SVM_FLAG_GPU_RO 0x00000008
567 /* Allow execution on GPU */
568 #define KFD_IOCTL_SVM_FLAG_GPU_EXEC 0x00000010
569 /* GPUs mostly read, may allow similar optimizations as RO, but writes fault */
570 #define KFD_IOCTL_SVM_FLAG_GPU_READ_MOSTLY 0x00000020
573 * kfd_ioctl_svm_op - SVM ioctl operations
575 * @KFD_IOCTL_SVM_OP_SET_ATTR: Modify one or more attributes
576 * @KFD_IOCTL_SVM_OP_GET_ATTR: Query one or more attributes
578 enum kfd_ioctl_svm_op {
579 KFD_IOCTL_SVM_OP_SET_ATTR,
580 KFD_IOCTL_SVM_OP_GET_ATTR
583 /** kfd_ioctl_svm_location - Enum for preferred and prefetch locations
585 * GPU IDs are used to specify GPUs as preferred and prefetch locations.
586 * Below definitions are used for system memory or for leaving the preferred
587 * location unspecified.
589 enum kfd_ioctl_svm_location {
590 KFD_IOCTL_SVM_LOCATION_SYSMEM = 0,
591 KFD_IOCTL_SVM_LOCATION_UNDEFINED = 0xffffffff
595 * kfd_ioctl_svm_attr_type - SVM attribute types
597 * @KFD_IOCTL_SVM_ATTR_PREFERRED_LOC: gpuid of the preferred location, 0 for
599 * @KFD_IOCTL_SVM_ATTR_PREFETCH_LOC: gpuid of the prefetch location, 0 for
600 * system memory. Setting this triggers an
601 * immediate prefetch (migration).
602 * @KFD_IOCTL_SVM_ATTR_ACCESS:
603 * @KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE:
604 * @KFD_IOCTL_SVM_ATTR_NO_ACCESS: specify memory access for the gpuid given
605 * by the attribute value
606 * @KFD_IOCTL_SVM_ATTR_SET_FLAGS: bitmask of flags to set (see
607 * KFD_IOCTL_SVM_FLAG_...)
608 * @KFD_IOCTL_SVM_ATTR_CLR_FLAGS: bitmask of flags to clear
609 * @KFD_IOCTL_SVM_ATTR_GRANULARITY: migration granularity
612 enum kfd_ioctl_svm_attr_type {
613 KFD_IOCTL_SVM_ATTR_PREFERRED_LOC,
614 KFD_IOCTL_SVM_ATTR_PREFETCH_LOC,
615 KFD_IOCTL_SVM_ATTR_ACCESS,
616 KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE,
617 KFD_IOCTL_SVM_ATTR_NO_ACCESS,
618 KFD_IOCTL_SVM_ATTR_SET_FLAGS,
619 KFD_IOCTL_SVM_ATTR_CLR_FLAGS,
620 KFD_IOCTL_SVM_ATTR_GRANULARITY
624 * kfd_ioctl_svm_attribute - Attributes as pairs of type and value
626 * The meaning of the @value depends on the attribute type.
628 * @type: attribute type (see enum @kfd_ioctl_svm_attr_type)
629 * @value: attribute value
631 struct kfd_ioctl_svm_attribute {
637 * kfd_ioctl_svm_args - Arguments for SVM ioctl
639 * @op specifies the operation to perform (see enum
640 * @kfd_ioctl_svm_op). @start_addr and @size are common for all
643 * A variable number of attributes can be given in @attrs.
644 * @nattr specifies the number of attributes. New attributes can be
645 * added in the future without breaking the ABI. If unknown attributes
646 * are given, the function returns -EINVAL.
648 * @KFD_IOCTL_SVM_OP_SET_ATTR sets attributes for a virtual address
649 * range. It may overlap existing virtual address ranges. If it does,
650 * the existing ranges will be split such that the attribute changes
651 * only apply to the specified address range.
653 * @KFD_IOCTL_SVM_OP_GET_ATTR returns the intersection of attributes
654 * over all memory in the given range and returns the result as the
655 * attribute value. If different pages have different preferred or
656 * prefetch locations, 0xffffffff will be returned for
657 * @KFD_IOCTL_SVM_ATTR_PREFERRED_LOC or
658 * @KFD_IOCTL_SVM_ATTR_PREFETCH_LOC resepctively. For
659 * @KFD_IOCTL_SVM_ATTR_SET_FLAGS, flags of all pages will be
660 * aggregated by bitwise AND. That means, a flag will be set in the
661 * output, if that flag is set for all pages in the range. For
662 * @KFD_IOCTL_SVM_ATTR_CLR_FLAGS, flags of all pages will be
663 * aggregated by bitwise NOR. That means, a flag will be set in the
664 * output, if that flag is clear for all pages in the range.
665 * The minimum migration granularity throughout the range will be
666 * returned for @KFD_IOCTL_SVM_ATTR_GRANULARITY.
668 * Querying of accessibility attributes works by initializing the
669 * attribute type to @KFD_IOCTL_SVM_ATTR_ACCESS and the value to the
670 * GPUID being queried. Multiple attributes can be given to allow
671 * querying multiple GPUIDs. The ioctl function overwrites the
672 * attribute type to indicate the access for the specified GPU.
674 struct kfd_ioctl_svm_args {
679 /* Variable length array of attributes */
680 struct kfd_ioctl_svm_attribute attrs[];
684 * kfd_ioctl_set_xnack_mode_args - Arguments for set_xnack_mode
686 * @xnack_enabled: [in/out] Whether to enable XNACK mode for this process
688 * @xnack_enabled indicates whether recoverable page faults should be
689 * enabled for the current process. 0 means disabled, positive means
690 * enabled, negative means leave unchanged. If enabled, virtual address
691 * translations on GFXv9 and later AMD GPUs can return XNACK and retry
692 * the access until a valid PTE is available. This is used to implement
693 * device page faults.
695 * On output, @xnack_enabled returns the (new) current mode (0 or
696 * positive). Therefore, a negative input value can be used to query
697 * the current mode without changing it.
699 * The XNACK mode fundamentally changes the way SVM managed memory works
700 * in the driver, with subtle effects on application performance and
703 * Enabling XNACK mode requires shader programs to be compiled
704 * differently. Furthermore, not all GPUs support changing the mode
705 * per-process. Therefore changing the mode is only allowed while no
706 * user mode queues exist in the process. This ensure that no shader
707 * code is running that may be compiled for the wrong mode. And GPUs
708 * that cannot change to the requested mode will prevent the XNACK
709 * mode from occurring. All GPUs used by the process must be in the
712 * GFXv8 or older GPUs do not support 48 bit virtual addresses or SVM.
713 * Therefore those GPUs are not considered for the XNACK mode switch.
715 * Return: 0 on success, -errno on failure
717 struct kfd_ioctl_set_xnack_mode_args {
721 #define AMDKFD_IOCTL_BASE 'K'
722 #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr)
723 #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type)
724 #define AMDKFD_IOW(nr, type) _IOW(AMDKFD_IOCTL_BASE, nr, type)
725 #define AMDKFD_IOWR(nr, type) _IOWR(AMDKFD_IOCTL_BASE, nr, type)
727 #define AMDKFD_IOC_GET_VERSION \
728 AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args)
730 #define AMDKFD_IOC_CREATE_QUEUE \
731 AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args)
733 #define AMDKFD_IOC_DESTROY_QUEUE \
734 AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args)
736 #define AMDKFD_IOC_SET_MEMORY_POLICY \
737 AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args)
739 #define AMDKFD_IOC_GET_CLOCK_COUNTERS \
740 AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args)
742 #define AMDKFD_IOC_GET_PROCESS_APERTURES \
743 AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args)
745 #define AMDKFD_IOC_UPDATE_QUEUE \
746 AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args)
748 #define AMDKFD_IOC_CREATE_EVENT \
749 AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args)
751 #define AMDKFD_IOC_DESTROY_EVENT \
752 AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args)
754 #define AMDKFD_IOC_SET_EVENT \
755 AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args)
757 #define AMDKFD_IOC_RESET_EVENT \
758 AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args)
760 #define AMDKFD_IOC_WAIT_EVENTS \
761 AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args)
763 #define AMDKFD_IOC_DBG_REGISTER_DEPRECATED \
764 AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args)
766 #define AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED \
767 AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args)
769 #define AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED \
770 AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args)
772 #define AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED \
773 AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args)
775 #define AMDKFD_IOC_SET_SCRATCH_BACKING_VA \
776 AMDKFD_IOWR(0x11, struct kfd_ioctl_set_scratch_backing_va_args)
778 #define AMDKFD_IOC_GET_TILE_CONFIG \
779 AMDKFD_IOWR(0x12, struct kfd_ioctl_get_tile_config_args)
781 #define AMDKFD_IOC_SET_TRAP_HANDLER \
782 AMDKFD_IOW(0x13, struct kfd_ioctl_set_trap_handler_args)
784 #define AMDKFD_IOC_GET_PROCESS_APERTURES_NEW \
786 struct kfd_ioctl_get_process_apertures_new_args)
788 #define AMDKFD_IOC_ACQUIRE_VM \
789 AMDKFD_IOW(0x15, struct kfd_ioctl_acquire_vm_args)
791 #define AMDKFD_IOC_ALLOC_MEMORY_OF_GPU \
792 AMDKFD_IOWR(0x16, struct kfd_ioctl_alloc_memory_of_gpu_args)
794 #define AMDKFD_IOC_FREE_MEMORY_OF_GPU \
795 AMDKFD_IOW(0x17, struct kfd_ioctl_free_memory_of_gpu_args)
797 #define AMDKFD_IOC_MAP_MEMORY_TO_GPU \
798 AMDKFD_IOWR(0x18, struct kfd_ioctl_map_memory_to_gpu_args)
800 #define AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU \
801 AMDKFD_IOWR(0x19, struct kfd_ioctl_unmap_memory_from_gpu_args)
803 #define AMDKFD_IOC_SET_CU_MASK \
804 AMDKFD_IOW(0x1A, struct kfd_ioctl_set_cu_mask_args)
806 #define AMDKFD_IOC_GET_QUEUE_WAVE_STATE \
807 AMDKFD_IOWR(0x1B, struct kfd_ioctl_get_queue_wave_state_args)
809 #define AMDKFD_IOC_GET_DMABUF_INFO \
810 AMDKFD_IOWR(0x1C, struct kfd_ioctl_get_dmabuf_info_args)
812 #define AMDKFD_IOC_IMPORT_DMABUF \
813 AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args)
815 #define AMDKFD_IOC_ALLOC_QUEUE_GWS \
816 AMDKFD_IOWR(0x1E, struct kfd_ioctl_alloc_queue_gws_args)
818 #define AMDKFD_IOC_SMI_EVENTS \
819 AMDKFD_IOWR(0x1F, struct kfd_ioctl_smi_events_args)
821 #define AMDKFD_IOC_SVM AMDKFD_IOWR(0x20, struct kfd_ioctl_svm_args)
823 #define AMDKFD_IOC_SET_XNACK_MODE \
824 AMDKFD_IOWR(0x21, struct kfd_ioctl_set_xnack_mode_args)
826 #define AMDKFD_IOC_CRIU_OP \
827 AMDKFD_IOWR(0x22, struct kfd_ioctl_criu_args)
829 #define AMDKFD_COMMAND_START 0x01
830 #define AMDKFD_COMMAND_END 0x23