2 * Driver for msm7k serial device and console
4 * Copyright (C) 2007 Google, Inc.
5 * Author: Robert Love <rlove@google.com>
6 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19 # define SUPPORT_SYSRQ
22 #include <linux/kernel.h>
23 #include <linux/atomic.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmaengine.h>
26 #include <linux/module.h>
28 #include <linux/ioport.h>
29 #include <linux/interrupt.h>
30 #include <linux/init.h>
31 #include <linux/console.h>
32 #include <linux/tty.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial_core.h>
35 #include <linux/slab.h>
36 #include <linux/clk.h>
37 #include <linux/platform_device.h>
38 #include <linux/delay.h>
40 #include <linux/of_device.h>
41 #include <linux/wait.h>
43 #define UART_MR1 0x0000
45 #define UART_MR1_AUTO_RFR_LEVEL0 0x3F
46 #define UART_MR1_AUTO_RFR_LEVEL1 0x3FF00
47 #define UART_DM_MR1_AUTO_RFR_LEVEL1 0xFFFFFF00
48 #define UART_MR1_RX_RDY_CTL BIT(7)
49 #define UART_MR1_CTS_CTL BIT(6)
51 #define UART_MR2 0x0004
52 #define UART_MR2_ERROR_MODE BIT(6)
53 #define UART_MR2_BITS_PER_CHAR 0x30
54 #define UART_MR2_BITS_PER_CHAR_5 (0x0 << 4)
55 #define UART_MR2_BITS_PER_CHAR_6 (0x1 << 4)
56 #define UART_MR2_BITS_PER_CHAR_7 (0x2 << 4)
57 #define UART_MR2_BITS_PER_CHAR_8 (0x3 << 4)
58 #define UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2)
59 #define UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2)
60 #define UART_MR2_PARITY_MODE_NONE 0x0
61 #define UART_MR2_PARITY_MODE_ODD 0x1
62 #define UART_MR2_PARITY_MODE_EVEN 0x2
63 #define UART_MR2_PARITY_MODE_SPACE 0x3
64 #define UART_MR2_PARITY_MODE 0x3
66 #define UART_CSR 0x0008
68 #define UART_TF 0x000C
69 #define UARTDM_TF 0x0070
71 #define UART_CR 0x0010
72 #define UART_CR_CMD_NULL (0 << 4)
73 #define UART_CR_CMD_RESET_RX (1 << 4)
74 #define UART_CR_CMD_RESET_TX (2 << 4)
75 #define UART_CR_CMD_RESET_ERR (3 << 4)
76 #define UART_CR_CMD_RESET_BREAK_INT (4 << 4)
77 #define UART_CR_CMD_START_BREAK (5 << 4)
78 #define UART_CR_CMD_STOP_BREAK (6 << 4)
79 #define UART_CR_CMD_RESET_CTS (7 << 4)
80 #define UART_CR_CMD_RESET_STALE_INT (8 << 4)
81 #define UART_CR_CMD_PACKET_MODE (9 << 4)
82 #define UART_CR_CMD_MODE_RESET (12 << 4)
83 #define UART_CR_CMD_SET_RFR (13 << 4)
84 #define UART_CR_CMD_RESET_RFR (14 << 4)
85 #define UART_CR_CMD_PROTECTION_EN (16 << 4)
86 #define UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8)
87 #define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4)
88 #define UART_CR_CMD_FORCE_STALE (4 << 8)
89 #define UART_CR_CMD_RESET_TX_READY (3 << 8)
90 #define UART_CR_TX_DISABLE BIT(3)
91 #define UART_CR_TX_ENABLE BIT(2)
92 #define UART_CR_RX_DISABLE BIT(1)
93 #define UART_CR_RX_ENABLE BIT(0)
94 #define UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4))
96 #define UART_IMR 0x0014
97 #define UART_IMR_TXLEV BIT(0)
98 #define UART_IMR_RXSTALE BIT(3)
99 #define UART_IMR_RXLEV BIT(4)
100 #define UART_IMR_DELTA_CTS BIT(5)
101 #define UART_IMR_CURRENT_CTS BIT(6)
102 #define UART_IMR_RXBREAK_START BIT(10)
104 #define UART_IPR_RXSTALE_LAST 0x20
105 #define UART_IPR_STALE_LSB 0x1F
106 #define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80
107 #define UART_DM_IPR_STALE_TIMEOUT_MSB 0xFFFFFF80
109 #define UART_IPR 0x0018
110 #define UART_TFWR 0x001C
111 #define UART_RFWR 0x0020
112 #define UART_HCR 0x0024
114 #define UART_MREG 0x0028
115 #define UART_NREG 0x002C
116 #define UART_DREG 0x0030
117 #define UART_MNDREG 0x0034
118 #define UART_IRDA 0x0038
119 #define UART_MISR_MODE 0x0040
120 #define UART_MISR_RESET 0x0044
121 #define UART_MISR_EXPORT 0x0048
122 #define UART_MISR_VAL 0x004C
123 #define UART_TEST_CTRL 0x0050
125 #define UART_SR 0x0008
126 #define UART_SR_HUNT_CHAR BIT(7)
127 #define UART_SR_RX_BREAK BIT(6)
128 #define UART_SR_PAR_FRAME_ERR BIT(5)
129 #define UART_SR_OVERRUN BIT(4)
130 #define UART_SR_TX_EMPTY BIT(3)
131 #define UART_SR_TX_READY BIT(2)
132 #define UART_SR_RX_FULL BIT(1)
133 #define UART_SR_RX_READY BIT(0)
135 #define UART_RF 0x000C
136 #define UARTDM_RF 0x0070
137 #define UART_MISR 0x0010
138 #define UART_ISR 0x0014
139 #define UART_ISR_TX_READY BIT(7)
141 #define UARTDM_RXFS 0x50
142 #define UARTDM_RXFS_BUF_SHIFT 0x7
143 #define UARTDM_RXFS_BUF_MASK 0x7
145 #define UARTDM_DMEN 0x3C
146 #define UARTDM_DMEN_RX_SC_ENABLE BIT(5)
147 #define UARTDM_DMEN_TX_SC_ENABLE BIT(4)
149 #define UARTDM_DMEN_TX_BAM_ENABLE BIT(2) /* UARTDM_1P4 */
150 #define UARTDM_DMEN_TX_DM_ENABLE BIT(0) /* < UARTDM_1P4 */
152 #define UARTDM_DMEN_RX_BAM_ENABLE BIT(3) /* UARTDM_1P4 */
153 #define UARTDM_DMEN_RX_DM_ENABLE BIT(1) /* < UARTDM_1P4 */
155 #define UARTDM_DMRX 0x34
156 #define UARTDM_NCF_TX 0x40
157 #define UARTDM_RX_TOTAL_SNAP 0x38
159 #define UARTDM_BURST_SIZE 16 /* in bytes */
160 #define UARTDM_TX_AIGN(x) ((x) & ~0x3) /* valid for > 1p3 */
161 #define UARTDM_TX_MAX 256 /* in bytes, valid for <= 1p3 */
162 #define UARTDM_RX_SIZE (UART_XMIT_SIZE / 4)
172 struct dma_chan *chan;
173 enum dma_data_direction dir;
179 struct dma_async_tx_descriptor *desc;
183 struct uart_port uart;
189 unsigned int old_snap_state;
191 struct msm_dma tx_dma;
192 struct msm_dma rx_dma;
195 #define UART_TO_MSM(uart_port) container_of(uart_port, struct msm_port, uart)
198 void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
200 writel_relaxed(val, port->membase + off);
204 unsigned int msm_read(struct uart_port *port, unsigned int off)
206 return readl_relaxed(port->membase + off);
210 * Setup the MND registers to use the TCXO clock.
212 static void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
214 msm_write(port, 0x06, UART_MREG);
215 msm_write(port, 0xF1, UART_NREG);
216 msm_write(port, 0x0F, UART_DREG);
217 msm_write(port, 0x1A, UART_MNDREG);
218 port->uartclk = 1843200;
222 * Setup the MND registers to use the TCXO clock divided by 4.
224 static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
226 msm_write(port, 0x18, UART_MREG);
227 msm_write(port, 0xF6, UART_NREG);
228 msm_write(port, 0x0F, UART_DREG);
229 msm_write(port, 0x0A, UART_MNDREG);
230 port->uartclk = 1843200;
233 static void msm_serial_set_mnd_regs(struct uart_port *port)
235 struct msm_port *msm_port = UART_TO_MSM(port);
238 * These registers don't exist so we change the clk input rate
239 * on uartdm hardware instead
241 if (msm_port->is_uartdm)
244 if (port->uartclk == 19200000)
245 msm_serial_set_mnd_regs_tcxo(port);
246 else if (port->uartclk == 4800000)
247 msm_serial_set_mnd_regs_tcxoby4(port);
250 static void msm_handle_tx(struct uart_port *port);
251 static void msm_start_rx_dma(struct msm_port *msm_port);
253 static void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
255 struct device *dev = port->dev;
262 dmaengine_terminate_all(dma->chan);
265 * DMA Stall happens if enqueue and flush command happens concurrently.
266 * For example before changing the baud rate/protocol configuration and
267 * sending flush command to ADM, disable the channel of UARTDM.
268 * Note: should not reset the receiver here immediately as it is not
269 * suggested to do disable/reset or reset/disable at the same time.
271 val = msm_read(port, UARTDM_DMEN);
272 val &= ~dma->enable_bit;
273 msm_write(port, val, UARTDM_DMEN);
276 dma_unmap_single(dev, dma->phys, mapped, dma->dir);
279 static void msm_release_dma(struct msm_port *msm_port)
283 dma = &msm_port->tx_dma;
285 msm_stop_dma(&msm_port->uart, dma);
286 dma_release_channel(dma->chan);
289 memset(dma, 0, sizeof(*dma));
291 dma = &msm_port->rx_dma;
293 msm_stop_dma(&msm_port->uart, dma);
294 dma_release_channel(dma->chan);
298 memset(dma, 0, sizeof(*dma));
301 static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
303 struct device *dev = msm_port->uart.dev;
304 struct dma_slave_config conf;
309 dma = &msm_port->tx_dma;
311 /* allocate DMA resources, if available */
312 dma->chan = dma_request_slave_channel_reason(dev, "tx");
313 if (IS_ERR(dma->chan))
316 of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci);
318 memset(&conf, 0, sizeof(conf));
319 conf.direction = DMA_MEM_TO_DEV;
320 conf.device_fc = true;
321 conf.dst_addr = base + UARTDM_TF;
322 conf.dst_maxburst = UARTDM_BURST_SIZE;
323 conf.slave_id = crci;
325 ret = dmaengine_slave_config(dma->chan, &conf);
329 dma->dir = DMA_TO_DEVICE;
331 if (msm_port->is_uartdm < UARTDM_1P4)
332 dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE;
334 dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE;
339 dma_release_channel(dma->chan);
341 memset(dma, 0, sizeof(*dma));
344 static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base)
346 struct device *dev = msm_port->uart.dev;
347 struct dma_slave_config conf;
352 dma = &msm_port->rx_dma;
354 /* allocate DMA resources, if available */
355 dma->chan = dma_request_slave_channel_reason(dev, "rx");
356 if (IS_ERR(dma->chan))
359 of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci);
361 dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL);
365 memset(&conf, 0, sizeof(conf));
366 conf.direction = DMA_DEV_TO_MEM;
367 conf.device_fc = true;
368 conf.src_addr = base + UARTDM_RF;
369 conf.src_maxburst = UARTDM_BURST_SIZE;
370 conf.slave_id = crci;
372 ret = dmaengine_slave_config(dma->chan, &conf);
376 dma->dir = DMA_FROM_DEVICE;
378 if (msm_port->is_uartdm < UARTDM_1P4)
379 dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE;
381 dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE;
387 dma_release_channel(dma->chan);
389 memset(dma, 0, sizeof(*dma));
392 static inline void msm_wait_for_xmitr(struct uart_port *port)
394 unsigned int timeout = 500000;
396 while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
397 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
403 msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);
406 static void msm_stop_tx(struct uart_port *port)
408 struct msm_port *msm_port = UART_TO_MSM(port);
410 msm_port->imr &= ~UART_IMR_TXLEV;
411 msm_write(port, msm_port->imr, UART_IMR);
414 static void msm_start_tx(struct uart_port *port)
416 struct msm_port *msm_port = UART_TO_MSM(port);
417 struct msm_dma *dma = &msm_port->tx_dma;
419 /* Already started in DMA mode */
423 msm_port->imr |= UART_IMR_TXLEV;
424 msm_write(port, msm_port->imr, UART_IMR);
427 static void msm_reset_dm_count(struct uart_port *port, int count)
429 msm_wait_for_xmitr(port);
430 msm_write(port, count, UARTDM_NCF_TX);
431 msm_read(port, UARTDM_NCF_TX);
434 static void msm_complete_tx_dma(void *args)
436 struct msm_port *msm_port = args;
437 struct uart_port *port = &msm_port->uart;
438 struct circ_buf *xmit = &port->state->xmit;
439 struct msm_dma *dma = &msm_port->tx_dma;
440 struct dma_tx_state state;
441 enum dma_status status;
446 spin_lock_irqsave(&port->lock, flags);
448 /* Already stopped */
452 status = dmaengine_tx_status(dma->chan, dma->cookie, &state);
454 dma_unmap_single(port->dev, dma->phys, dma->count, dma->dir);
456 val = msm_read(port, UARTDM_DMEN);
457 val &= ~dma->enable_bit;
458 msm_write(port, val, UARTDM_DMEN);
460 if (msm_port->is_uartdm > UARTDM_1P3) {
461 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
462 msm_write(port, UART_CR_TX_ENABLE, UART_CR);
465 count = dma->count - state.residue;
466 port->icount.tx += count;
470 xmit->tail &= UART_XMIT_SIZE - 1;
472 /* Restore "Tx FIFO below watermark" interrupt */
473 msm_port->imr |= UART_IMR_TXLEV;
474 msm_write(port, msm_port->imr, UART_IMR);
476 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
477 uart_write_wakeup(port);
481 spin_unlock_irqrestore(&port->lock, flags);
484 static int msm_handle_tx_dma(struct msm_port *msm_port, unsigned int count)
486 struct circ_buf *xmit = &msm_port->uart.state->xmit;
487 struct uart_port *port = &msm_port->uart;
488 struct msm_dma *dma = &msm_port->tx_dma;
493 cpu_addr = &xmit->buf[xmit->tail];
495 dma->phys = dma_map_single(port->dev, cpu_addr, count, dma->dir);
496 ret = dma_mapping_error(port->dev, dma->phys);
500 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
501 count, DMA_MEM_TO_DEV,
509 dma->desc->callback = msm_complete_tx_dma;
510 dma->desc->callback_param = msm_port;
512 dma->cookie = dmaengine_submit(dma->desc);
513 ret = dma_submit_error(dma->cookie);
518 * Using DMA complete for Tx FIFO reload, no need for
519 * "Tx FIFO below watermark" one, disable it
521 msm_port->imr &= ~UART_IMR_TXLEV;
522 msm_write(port, msm_port->imr, UART_IMR);
526 val = msm_read(port, UARTDM_DMEN);
527 val |= dma->enable_bit;
529 if (msm_port->is_uartdm < UARTDM_1P4)
530 msm_write(port, val, UARTDM_DMEN);
532 msm_reset_dm_count(port, count);
534 if (msm_port->is_uartdm > UARTDM_1P3)
535 msm_write(port, val, UARTDM_DMEN);
537 dma_async_issue_pending(dma->chan);
540 dma_unmap_single(port->dev, dma->phys, count, dma->dir);
544 static void msm_complete_rx_dma(void *args)
546 struct msm_port *msm_port = args;
547 struct uart_port *port = &msm_port->uart;
548 struct tty_port *tport = &port->state->port;
549 struct msm_dma *dma = &msm_port->rx_dma;
550 int count = 0, i, sysrq;
554 spin_lock_irqsave(&port->lock, flags);
556 /* Already stopped */
560 val = msm_read(port, UARTDM_DMEN);
561 val &= ~dma->enable_bit;
562 msm_write(port, val, UARTDM_DMEN);
564 if (msm_read(port, UART_SR) & UART_SR_OVERRUN) {
565 port->icount.overrun++;
566 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
567 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
570 count = msm_read(port, UARTDM_RX_TOTAL_SNAP);
572 port->icount.rx += count;
576 dma_unmap_single(port->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
578 for (i = 0; i < count; i++) {
579 char flag = TTY_NORMAL;
581 if (msm_port->break_detected && dma->virt[i] == 0) {
584 msm_port->break_detected = false;
585 if (uart_handle_break(port))
589 if (!(port->read_status_mask & UART_SR_RX_BREAK))
592 spin_unlock_irqrestore(&port->lock, flags);
593 sysrq = uart_handle_sysrq_char(port, dma->virt[i]);
594 spin_lock_irqsave(&port->lock, flags);
596 tty_insert_flip_char(tport, dma->virt[i], flag);
599 msm_start_rx_dma(msm_port);
601 spin_unlock_irqrestore(&port->lock, flags);
604 tty_flip_buffer_push(tport);
607 static void msm_start_rx_dma(struct msm_port *msm_port)
609 struct msm_dma *dma = &msm_port->rx_dma;
610 struct uart_port *uart = &msm_port->uart;
617 dma->phys = dma_map_single(uart->dev, dma->virt,
618 UARTDM_RX_SIZE, dma->dir);
619 ret = dma_mapping_error(uart->dev, dma->phys);
623 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
624 UARTDM_RX_SIZE, DMA_DEV_TO_MEM,
629 dma->desc->callback = msm_complete_rx_dma;
630 dma->desc->callback_param = msm_port;
632 dma->cookie = dmaengine_submit(dma->desc);
633 ret = dma_submit_error(dma->cookie);
637 * Using DMA for FIFO off-load, no need for "Rx FIFO over
638 * watermark" or "stale" interrupts, disable them
640 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
643 * Well, when DMA is ADM3 engine(implied by <= UARTDM v1.3),
644 * we need RXSTALE to flush input DMA fifo to memory
646 if (msm_port->is_uartdm < UARTDM_1P4)
647 msm_port->imr |= UART_IMR_RXSTALE;
649 msm_write(uart, msm_port->imr, UART_IMR);
651 dma->count = UARTDM_RX_SIZE;
653 dma_async_issue_pending(dma->chan);
655 msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);
656 msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
658 val = msm_read(uart, UARTDM_DMEN);
659 val |= dma->enable_bit;
661 if (msm_port->is_uartdm < UARTDM_1P4)
662 msm_write(uart, val, UARTDM_DMEN);
664 msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX);
666 if (msm_port->is_uartdm > UARTDM_1P3)
667 msm_write(uart, val, UARTDM_DMEN);
671 dma_unmap_single(uart->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
674 static void msm_stop_rx(struct uart_port *port)
676 struct msm_port *msm_port = UART_TO_MSM(port);
677 struct msm_dma *dma = &msm_port->rx_dma;
679 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
680 msm_write(port, msm_port->imr, UART_IMR);
683 msm_stop_dma(port, dma);
686 static void msm_enable_ms(struct uart_port *port)
688 struct msm_port *msm_port = UART_TO_MSM(port);
690 msm_port->imr |= UART_IMR_DELTA_CTS;
691 msm_write(port, msm_port->imr, UART_IMR);
694 static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr)
696 struct tty_port *tport = &port->state->port;
699 struct msm_port *msm_port = UART_TO_MSM(port);
701 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
702 port->icount.overrun++;
703 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
704 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
707 if (misr & UART_IMR_RXSTALE) {
708 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
709 msm_port->old_snap_state;
710 msm_port->old_snap_state = 0;
712 count = 4 * (msm_read(port, UART_RFWR));
713 msm_port->old_snap_state += count;
716 /* TODO: Precise error reporting */
718 port->icount.rx += count;
721 unsigned char buf[4];
722 int sysrq, r_count, i;
724 sr = msm_read(port, UART_SR);
725 if ((sr & UART_SR_RX_READY) == 0) {
726 msm_port->old_snap_state -= count;
730 ioread32_rep(port->membase + UARTDM_RF, buf, 1);
731 r_count = min_t(int, count, sizeof(buf));
733 for (i = 0; i < r_count; i++) {
734 char flag = TTY_NORMAL;
736 if (msm_port->break_detected && buf[i] == 0) {
739 msm_port->break_detected = false;
740 if (uart_handle_break(port))
744 if (!(port->read_status_mask & UART_SR_RX_BREAK))
747 spin_unlock(&port->lock);
748 sysrq = uart_handle_sysrq_char(port, buf[i]);
749 spin_lock(&port->lock);
751 tty_insert_flip_char(tport, buf[i], flag);
756 spin_unlock(&port->lock);
757 tty_flip_buffer_push(tport);
758 spin_lock(&port->lock);
760 if (misr & (UART_IMR_RXSTALE))
761 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
762 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
763 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
766 msm_start_rx_dma(msm_port);
769 static void msm_handle_rx(struct uart_port *port)
771 struct tty_port *tport = &port->state->port;
775 * Handle overrun. My understanding of the hardware is that overrun
776 * is not tied to the RX buffer, so we handle the case out of band.
778 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
779 port->icount.overrun++;
780 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
781 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
784 /* and now the main RX loop */
785 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
787 char flag = TTY_NORMAL;
790 c = msm_read(port, UART_RF);
792 if (sr & UART_SR_RX_BREAK) {
794 if (uart_handle_break(port))
796 } else if (sr & UART_SR_PAR_FRAME_ERR) {
797 port->icount.frame++;
802 /* Mask conditions we're ignorning. */
803 sr &= port->read_status_mask;
805 if (sr & UART_SR_RX_BREAK)
807 else if (sr & UART_SR_PAR_FRAME_ERR)
810 spin_unlock(&port->lock);
811 sysrq = uart_handle_sysrq_char(port, c);
812 spin_lock(&port->lock);
814 tty_insert_flip_char(tport, c, flag);
817 spin_unlock(&port->lock);
818 tty_flip_buffer_push(tport);
819 spin_lock(&port->lock);
822 static void msm_handle_tx_pio(struct uart_port *port, unsigned int tx_count)
824 struct circ_buf *xmit = &port->state->xmit;
825 struct msm_port *msm_port = UART_TO_MSM(port);
826 unsigned int num_chars;
827 unsigned int tf_pointer = 0;
830 if (msm_port->is_uartdm)
831 tf = port->membase + UARTDM_TF;
833 tf = port->membase + UART_TF;
835 if (tx_count && msm_port->is_uartdm)
836 msm_reset_dm_count(port, tx_count);
838 while (tf_pointer < tx_count) {
842 if (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
845 if (msm_port->is_uartdm)
846 num_chars = min(tx_count - tf_pointer,
847 (unsigned int)sizeof(buf));
851 for (i = 0; i < num_chars; i++) {
852 buf[i] = xmit->buf[xmit->tail + i];
856 iowrite32_rep(tf, buf, 1);
857 xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1);
858 tf_pointer += num_chars;
861 /* disable tx interrupts if nothing more to send */
862 if (uart_circ_empty(xmit))
865 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
866 uart_write_wakeup(port);
869 static void msm_handle_tx(struct uart_port *port)
871 struct msm_port *msm_port = UART_TO_MSM(port);
872 struct circ_buf *xmit = &msm_port->uart.state->xmit;
873 struct msm_dma *dma = &msm_port->tx_dma;
874 unsigned int pio_count, dma_count, dma_min;
880 if (msm_port->is_uartdm)
881 tf = port->membase + UARTDM_TF;
883 tf = port->membase + UART_TF;
885 buf[0] = port->x_char;
887 if (msm_port->is_uartdm)
888 msm_reset_dm_count(port, 1);
890 iowrite32_rep(tf, buf, 1);
896 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
901 pio_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
902 dma_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
904 dma_min = 1; /* Always DMA */
905 if (msm_port->is_uartdm > UARTDM_1P3) {
906 dma_count = UARTDM_TX_AIGN(dma_count);
907 dma_min = UARTDM_BURST_SIZE;
909 if (dma_count > UARTDM_TX_MAX)
910 dma_count = UARTDM_TX_MAX;
913 if (pio_count > port->fifosize)
914 pio_count = port->fifosize;
916 if (!dma->chan || dma_count < dma_min)
917 msm_handle_tx_pio(port, pio_count);
919 err = msm_handle_tx_dma(msm_port, dma_count);
921 if (err) /* fall back to PIO mode */
922 msm_handle_tx_pio(port, pio_count);
925 static void msm_handle_delta_cts(struct uart_port *port)
927 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
929 wake_up_interruptible(&port->state->port.delta_msr_wait);
932 static irqreturn_t msm_uart_irq(int irq, void *dev_id)
934 struct uart_port *port = dev_id;
935 struct msm_port *msm_port = UART_TO_MSM(port);
936 struct msm_dma *dma = &msm_port->rx_dma;
941 spin_lock_irqsave(&port->lock, flags);
942 misr = msm_read(port, UART_MISR);
943 msm_write(port, 0, UART_IMR); /* disable interrupt */
945 if (misr & UART_IMR_RXBREAK_START) {
946 msm_port->break_detected = true;
947 msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR);
950 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
952 val = UART_CR_CMD_STALE_EVENT_DISABLE;
953 msm_write(port, val, UART_CR);
954 val = UART_CR_CMD_RESET_STALE_INT;
955 msm_write(port, val, UART_CR);
957 * Flush DMA input fifo to memory, this will also
958 * trigger DMA RX completion
960 dmaengine_terminate_all(dma->chan);
961 } else if (msm_port->is_uartdm) {
962 msm_handle_rx_dm(port, misr);
967 if (misr & UART_IMR_TXLEV)
969 if (misr & UART_IMR_DELTA_CTS)
970 msm_handle_delta_cts(port);
972 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
973 spin_unlock_irqrestore(&port->lock, flags);
978 static unsigned int msm_tx_empty(struct uart_port *port)
980 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
983 static unsigned int msm_get_mctrl(struct uart_port *port)
985 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
988 static void msm_reset(struct uart_port *port)
990 struct msm_port *msm_port = UART_TO_MSM(port);
993 /* reset everything */
994 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
995 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
996 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
997 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
998 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
999 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
1000 mr = msm_read(port, UART_MR1);
1001 mr &= ~UART_MR1_RX_RDY_CTL;
1002 msm_write(port, mr, UART_MR1);
1004 /* Disable DM modes */
1005 if (msm_port->is_uartdm)
1006 msm_write(port, 0, UARTDM_DMEN);
1009 static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
1013 mr = msm_read(port, UART_MR1);
1015 if (!(mctrl & TIOCM_RTS)) {
1016 mr &= ~UART_MR1_RX_RDY_CTL;
1017 msm_write(port, mr, UART_MR1);
1018 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
1020 mr |= UART_MR1_RX_RDY_CTL;
1021 msm_write(port, mr, UART_MR1);
1025 static void msm_break_ctl(struct uart_port *port, int break_ctl)
1028 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
1030 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
1033 struct msm_baud_map {
1039 static const struct msm_baud_map *
1040 msm_find_best_baud(struct uart_port *port, unsigned int baud,
1041 unsigned long *rate)
1043 struct msm_port *msm_port = UART_TO_MSM(port);
1044 unsigned int divisor, result;
1045 unsigned long target, old, best_rate = 0, diff, best_diff = ULONG_MAX;
1046 const struct msm_baud_map *entry, *end, *best;
1047 static const struct msm_baud_map table[] = {
1066 best = table; /* Default to smallest divider */
1067 target = clk_round_rate(msm_port->clk, 16 * baud);
1068 divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1070 end = table + ARRAY_SIZE(table);
1072 while (entry < end) {
1073 if (entry->divisor <= divisor) {
1074 result = target / entry->divisor / 16;
1075 diff = abs(result - baud);
1077 /* Keep track of best entry */
1078 if (diff < best_diff) {
1086 } else if (entry->divisor > divisor) {
1088 target = clk_round_rate(msm_port->clk, old + 1);
1090 * The rate didn't get any faster so we can't do
1091 * better at dividing it down
1096 /* Start the divisor search over at this new rate */
1098 divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1108 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud,
1109 unsigned long *saved_flags)
1111 unsigned int rxstale, watermark, mask;
1112 struct msm_port *msm_port = UART_TO_MSM(port);
1113 const struct msm_baud_map *entry;
1114 unsigned long flags, rate;
1116 flags = *saved_flags;
1117 spin_unlock_irqrestore(&port->lock, flags);
1119 entry = msm_find_best_baud(port, baud, &rate);
1120 clk_set_rate(msm_port->clk, rate);
1121 baud = rate / 16 / entry->divisor;
1123 spin_lock_irqsave(&port->lock, flags);
1124 *saved_flags = flags;
1125 port->uartclk = rate;
1127 msm_write(port, entry->code, UART_CSR);
1129 /* RX stale watermark */
1130 rxstale = entry->rxstale;
1131 watermark = UART_IPR_STALE_LSB & rxstale;
1132 if (msm_port->is_uartdm) {
1133 mask = UART_DM_IPR_STALE_TIMEOUT_MSB;
1135 watermark |= UART_IPR_RXSTALE_LAST;
1136 mask = UART_IPR_STALE_TIMEOUT_MSB;
1139 watermark |= mask & (rxstale << 2);
1141 msm_write(port, watermark, UART_IPR);
1143 /* set RX watermark */
1144 watermark = (port->fifosize * 3) / 4;
1145 msm_write(port, watermark, UART_RFWR);
1147 /* set TX watermark */
1148 msm_write(port, 10, UART_TFWR);
1150 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
1153 /* Enable RX and TX */
1154 msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR);
1156 /* turn on RX and CTS interrupts */
1157 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
1158 UART_IMR_CURRENT_CTS | UART_IMR_RXBREAK_START;
1160 msm_write(port, msm_port->imr, UART_IMR);
1162 if (msm_port->is_uartdm) {
1163 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1164 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1165 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
1171 static void msm_init_clock(struct uart_port *port)
1173 struct msm_port *msm_port = UART_TO_MSM(port);
1175 clk_prepare_enable(msm_port->clk);
1176 clk_prepare_enable(msm_port->pclk);
1177 msm_serial_set_mnd_regs(port);
1180 static int msm_startup(struct uart_port *port)
1182 struct msm_port *msm_port = UART_TO_MSM(port);
1183 unsigned int data, rfr_level, mask;
1186 snprintf(msm_port->name, sizeof(msm_port->name),
1187 "msm_serial%d", port->line);
1189 msm_init_clock(port);
1191 if (likely(port->fifosize > 12))
1192 rfr_level = port->fifosize - 12;
1194 rfr_level = port->fifosize;
1196 /* set automatic RFR level */
1197 data = msm_read(port, UART_MR1);
1199 if (msm_port->is_uartdm)
1200 mask = UART_DM_MR1_AUTO_RFR_LEVEL1;
1202 mask = UART_MR1_AUTO_RFR_LEVEL1;
1205 data &= ~UART_MR1_AUTO_RFR_LEVEL0;
1206 data |= mask & (rfr_level << 2);
1207 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
1208 msm_write(port, data, UART_MR1);
1210 if (msm_port->is_uartdm) {
1211 msm_request_tx_dma(msm_port, msm_port->uart.mapbase);
1212 msm_request_rx_dma(msm_port, msm_port->uart.mapbase);
1215 ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH,
1216 msm_port->name, port);
1223 if (msm_port->is_uartdm)
1224 msm_release_dma(msm_port);
1226 clk_disable_unprepare(msm_port->pclk);
1227 clk_disable_unprepare(msm_port->clk);
1232 static void msm_shutdown(struct uart_port *port)
1234 struct msm_port *msm_port = UART_TO_MSM(port);
1237 msm_write(port, 0, UART_IMR); /* disable interrupts */
1239 if (msm_port->is_uartdm)
1240 msm_release_dma(msm_port);
1242 clk_disable_unprepare(msm_port->clk);
1244 free_irq(port->irq, port);
1247 static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
1248 struct ktermios *old)
1250 struct msm_port *msm_port = UART_TO_MSM(port);
1251 struct msm_dma *dma = &msm_port->rx_dma;
1252 unsigned long flags;
1253 unsigned int baud, mr;
1255 spin_lock_irqsave(&port->lock, flags);
1257 if (dma->chan) /* Terminate if any */
1258 msm_stop_dma(port, dma);
1260 /* calculate and set baud rate */
1261 baud = uart_get_baud_rate(port, termios, old, 300, 4000000);
1262 baud = msm_set_baud_rate(port, baud, &flags);
1263 if (tty_termios_baud_rate(termios))
1264 tty_termios_encode_baud_rate(termios, baud, baud);
1266 /* calculate parity */
1267 mr = msm_read(port, UART_MR2);
1268 mr &= ~UART_MR2_PARITY_MODE;
1269 if (termios->c_cflag & PARENB) {
1270 if (termios->c_cflag & PARODD)
1271 mr |= UART_MR2_PARITY_MODE_ODD;
1272 else if (termios->c_cflag & CMSPAR)
1273 mr |= UART_MR2_PARITY_MODE_SPACE;
1275 mr |= UART_MR2_PARITY_MODE_EVEN;
1278 /* calculate bits per char */
1279 mr &= ~UART_MR2_BITS_PER_CHAR;
1280 switch (termios->c_cflag & CSIZE) {
1282 mr |= UART_MR2_BITS_PER_CHAR_5;
1285 mr |= UART_MR2_BITS_PER_CHAR_6;
1288 mr |= UART_MR2_BITS_PER_CHAR_7;
1292 mr |= UART_MR2_BITS_PER_CHAR_8;
1296 /* calculate stop bits */
1297 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
1298 if (termios->c_cflag & CSTOPB)
1299 mr |= UART_MR2_STOP_BIT_LEN_TWO;
1301 mr |= UART_MR2_STOP_BIT_LEN_ONE;
1303 /* set parity, bits per char, and stop bit */
1304 msm_write(port, mr, UART_MR2);
1306 /* calculate and set hardware flow control */
1307 mr = msm_read(port, UART_MR1);
1308 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
1309 if (termios->c_cflag & CRTSCTS) {
1310 mr |= UART_MR1_CTS_CTL;
1311 mr |= UART_MR1_RX_RDY_CTL;
1313 msm_write(port, mr, UART_MR1);
1315 /* Configure status bits to ignore based on termio flags. */
1316 port->read_status_mask = 0;
1317 if (termios->c_iflag & INPCK)
1318 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
1319 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1320 port->read_status_mask |= UART_SR_RX_BREAK;
1322 uart_update_timeout(port, termios->c_cflag, baud);
1324 /* Try to use DMA */
1325 msm_start_rx_dma(msm_port);
1327 spin_unlock_irqrestore(&port->lock, flags);
1330 static const char *msm_type(struct uart_port *port)
1335 static void msm_release_port(struct uart_port *port)
1337 struct platform_device *pdev = to_platform_device(port->dev);
1338 struct resource *uart_resource;
1339 resource_size_t size;
1341 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1342 if (unlikely(!uart_resource))
1344 size = resource_size(uart_resource);
1346 release_mem_region(port->mapbase, size);
1347 iounmap(port->membase);
1348 port->membase = NULL;
1351 static int msm_request_port(struct uart_port *port)
1353 struct platform_device *pdev = to_platform_device(port->dev);
1354 struct resource *uart_resource;
1355 resource_size_t size;
1358 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1359 if (unlikely(!uart_resource))
1362 size = resource_size(uart_resource);
1364 if (!request_mem_region(port->mapbase, size, "msm_serial"))
1367 port->membase = ioremap(port->mapbase, size);
1368 if (!port->membase) {
1370 goto fail_release_port;
1376 release_mem_region(port->mapbase, size);
1380 static void msm_config_port(struct uart_port *port, int flags)
1384 if (flags & UART_CONFIG_TYPE) {
1385 port->type = PORT_MSM;
1386 ret = msm_request_port(port);
1392 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
1394 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
1396 if (unlikely(port->irq != ser->irq))
1401 static void msm_power(struct uart_port *port, unsigned int state,
1402 unsigned int oldstate)
1404 struct msm_port *msm_port = UART_TO_MSM(port);
1408 clk_prepare_enable(msm_port->clk);
1409 clk_prepare_enable(msm_port->pclk);
1412 clk_disable_unprepare(msm_port->clk);
1413 clk_disable_unprepare(msm_port->pclk);
1416 pr_err("msm_serial: Unknown PM state %d\n", state);
1420 #ifdef CONFIG_CONSOLE_POLL
1421 static int msm_poll_get_char_single(struct uart_port *port)
1423 struct msm_port *msm_port = UART_TO_MSM(port);
1424 unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF;
1426 if (!(msm_read(port, UART_SR) & UART_SR_RX_READY))
1427 return NO_POLL_CHAR;
1429 return msm_read(port, rf_reg) & 0xff;
1432 static int msm_poll_get_char_dm(struct uart_port *port)
1437 unsigned char *sp = (unsigned char *)&slop;
1439 /* Check if a previous read had more than one char */
1441 c = sp[sizeof(slop) - count];
1443 /* Or if FIFO is empty */
1444 } else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) {
1446 * If RX packing buffer has less than a word, force stale to
1447 * push contents into RX FIFO
1449 count = msm_read(port, UARTDM_RXFS);
1450 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK;
1452 msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);
1453 slop = msm_read(port, UARTDM_RF);
1456 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1457 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1458 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE,
1463 /* FIFO has a word */
1465 slop = msm_read(port, UARTDM_RF);
1467 count = sizeof(slop) - 1;
1473 static int msm_poll_get_char(struct uart_port *port)
1477 struct msm_port *msm_port = UART_TO_MSM(port);
1479 /* Disable all interrupts */
1480 imr = msm_read(port, UART_IMR);
1481 msm_write(port, 0, UART_IMR);
1483 if (msm_port->is_uartdm)
1484 c = msm_poll_get_char_dm(port);
1486 c = msm_poll_get_char_single(port);
1488 /* Enable interrupts */
1489 msm_write(port, imr, UART_IMR);
1494 static void msm_poll_put_char(struct uart_port *port, unsigned char c)
1497 struct msm_port *msm_port = UART_TO_MSM(port);
1499 /* Disable all interrupts */
1500 imr = msm_read(port, UART_IMR);
1501 msm_write(port, 0, UART_IMR);
1503 if (msm_port->is_uartdm)
1504 msm_reset_dm_count(port, 1);
1506 /* Wait until FIFO is empty */
1507 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1510 /* Write a character */
1511 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
1513 /* Wait until FIFO is empty */
1514 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1517 /* Enable interrupts */
1518 msm_write(port, imr, UART_IMR);
1522 static struct uart_ops msm_uart_pops = {
1523 .tx_empty = msm_tx_empty,
1524 .set_mctrl = msm_set_mctrl,
1525 .get_mctrl = msm_get_mctrl,
1526 .stop_tx = msm_stop_tx,
1527 .start_tx = msm_start_tx,
1528 .stop_rx = msm_stop_rx,
1529 .enable_ms = msm_enable_ms,
1530 .break_ctl = msm_break_ctl,
1531 .startup = msm_startup,
1532 .shutdown = msm_shutdown,
1533 .set_termios = msm_set_termios,
1535 .release_port = msm_release_port,
1536 .request_port = msm_request_port,
1537 .config_port = msm_config_port,
1538 .verify_port = msm_verify_port,
1540 #ifdef CONFIG_CONSOLE_POLL
1541 .poll_get_char = msm_poll_get_char,
1542 .poll_put_char = msm_poll_put_char,
1546 static struct msm_port msm_uart_ports[] = {
1550 .ops = &msm_uart_pops,
1551 .flags = UPF_BOOT_AUTOCONF,
1559 .ops = &msm_uart_pops,
1560 .flags = UPF_BOOT_AUTOCONF,
1568 .ops = &msm_uart_pops,
1569 .flags = UPF_BOOT_AUTOCONF,
1576 #define UART_NR ARRAY_SIZE(msm_uart_ports)
1578 static inline struct uart_port *msm_get_port_from_line(unsigned int line)
1580 return &msm_uart_ports[line].uart;
1583 #ifdef CONFIG_SERIAL_MSM_CONSOLE
1584 static void __msm_console_write(struct uart_port *port, const char *s,
1585 unsigned int count, bool is_uartdm)
1588 int num_newlines = 0;
1589 bool replaced = false;
1594 tf = port->membase + UARTDM_TF;
1596 tf = port->membase + UART_TF;
1598 /* Account for newlines that will get a carriage return added */
1599 for (i = 0; i < count; i++)
1602 count += num_newlines;
1606 else if (oops_in_progress)
1607 locked = spin_trylock(&port->lock);
1609 spin_lock(&port->lock);
1612 msm_reset_dm_count(port, count);
1617 unsigned int num_chars;
1618 char buf[4] = { 0 };
1621 num_chars = min(count - i, (unsigned int)sizeof(buf));
1625 for (j = 0; j < num_chars; j++) {
1628 if (c == '\n' && !replaced) {
1633 if (j < num_chars) {
1640 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1643 iowrite32_rep(tf, buf, 1);
1648 spin_unlock(&port->lock);
1651 static void msm_console_write(struct console *co, const char *s,
1654 struct uart_port *port;
1655 struct msm_port *msm_port;
1657 BUG_ON(co->index < 0 || co->index >= UART_NR);
1659 port = msm_get_port_from_line(co->index);
1660 msm_port = UART_TO_MSM(port);
1662 __msm_console_write(port, s, count, msm_port->is_uartdm);
1665 static int __init msm_console_setup(struct console *co, char *options)
1667 struct uart_port *port;
1673 if (unlikely(co->index >= UART_NR || co->index < 0))
1676 port = msm_get_port_from_line(co->index);
1678 if (unlikely(!port->membase))
1681 msm_init_clock(port);
1684 uart_parse_options(options, &baud, &parity, &bits, &flow);
1686 pr_info("msm_serial: console setup on port #%d\n", port->line);
1688 return uart_set_options(port, co, baud, parity, bits, flow);
1692 msm_serial_early_write(struct console *con, const char *s, unsigned n)
1694 struct earlycon_device *dev = con->data;
1696 __msm_console_write(&dev->port, s, n, false);
1700 msm_serial_early_console_setup(struct earlycon_device *device, const char *opt)
1702 if (!device->port.membase)
1705 device->con->write = msm_serial_early_write;
1708 OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart",
1709 msm_serial_early_console_setup);
1712 msm_serial_early_write_dm(struct console *con, const char *s, unsigned n)
1714 struct earlycon_device *dev = con->data;
1716 __msm_console_write(&dev->port, s, n, true);
1720 msm_serial_early_console_setup_dm(struct earlycon_device *device,
1723 if (!device->port.membase)
1726 device->con->write = msm_serial_early_write_dm;
1729 OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm",
1730 msm_serial_early_console_setup_dm);
1732 static struct uart_driver msm_uart_driver;
1734 static struct console msm_console = {
1736 .write = msm_console_write,
1737 .device = uart_console_device,
1738 .setup = msm_console_setup,
1739 .flags = CON_PRINTBUFFER,
1741 .data = &msm_uart_driver,
1744 #define MSM_CONSOLE (&msm_console)
1747 #define MSM_CONSOLE NULL
1750 static struct uart_driver msm_uart_driver = {
1751 .owner = THIS_MODULE,
1752 .driver_name = "msm_serial",
1753 .dev_name = "ttyMSM",
1755 .cons = MSM_CONSOLE,
1758 static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
1760 static const struct of_device_id msm_uartdm_table[] = {
1761 { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 },
1762 { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 },
1763 { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 },
1764 { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 },
1768 static int msm_serial_probe(struct platform_device *pdev)
1770 struct msm_port *msm_port;
1771 struct resource *resource;
1772 struct uart_port *port;
1773 const struct of_device_id *id;
1776 if (pdev->dev.of_node)
1777 line = of_alias_get_id(pdev->dev.of_node, "serial");
1782 line = atomic_inc_return(&msm_uart_next_id) - 1;
1784 if (unlikely(line < 0 || line >= UART_NR))
1787 dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line);
1789 port = msm_get_port_from_line(line);
1790 port->dev = &pdev->dev;
1791 msm_port = UART_TO_MSM(port);
1793 id = of_match_device(msm_uartdm_table, &pdev->dev);
1795 msm_port->is_uartdm = (unsigned long)id->data;
1797 msm_port->is_uartdm = 0;
1799 msm_port->clk = devm_clk_get(&pdev->dev, "core");
1800 if (IS_ERR(msm_port->clk))
1801 return PTR_ERR(msm_port->clk);
1803 if (msm_port->is_uartdm) {
1804 msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
1805 if (IS_ERR(msm_port->pclk))
1806 return PTR_ERR(msm_port->pclk);
1809 port->uartclk = clk_get_rate(msm_port->clk);
1810 dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk);
1812 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1813 if (unlikely(!resource))
1815 port->mapbase = resource->start;
1817 irq = platform_get_irq(pdev, 0);
1818 if (unlikely(irq < 0))
1822 platform_set_drvdata(pdev, port);
1824 return uart_add_one_port(&msm_uart_driver, port);
1827 static int msm_serial_remove(struct platform_device *pdev)
1829 struct uart_port *port = platform_get_drvdata(pdev);
1831 uart_remove_one_port(&msm_uart_driver, port);
1836 static const struct of_device_id msm_match_table[] = {
1837 { .compatible = "qcom,msm-uart" },
1838 { .compatible = "qcom,msm-uartdm" },
1841 MODULE_DEVICE_TABLE(of, msm_match_table);
1843 static struct platform_driver msm_platform_driver = {
1844 .remove = msm_serial_remove,
1845 .probe = msm_serial_probe,
1847 .name = "msm_serial",
1848 .of_match_table = msm_match_table,
1852 static int __init msm_serial_init(void)
1856 ret = uart_register_driver(&msm_uart_driver);
1860 ret = platform_driver_register(&msm_platform_driver);
1862 uart_unregister_driver(&msm_uart_driver);
1864 pr_info("msm_serial: driver initialized\n");
1869 static void __exit msm_serial_exit(void)
1871 platform_driver_unregister(&msm_platform_driver);
1872 uart_unregister_driver(&msm_uart_driver);
1875 module_init(msm_serial_init);
1876 module_exit(msm_serial_exit);
1878 MODULE_AUTHOR("Robert Love <rlove@google.com>");
1879 MODULE_DESCRIPTION("Driver for msm7x serial device");
1880 MODULE_LICENSE("GPL");