2 * Driver for Atmel AT91 Serial ports
3 * Copyright (C) 2003 Rick Bronson
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * DMA support added by Chip Coldwell.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/tty.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/init.h>
29 #include <linux/serial.h>
30 #include <linux/clk.h>
31 #include <linux/console.h>
32 #include <linux/sysrq.h>
33 #include <linux/tty_flip.h>
34 #include <linux/platform_device.h>
36 #include <linux/of_device.h>
37 #include <linux/of_gpio.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmaengine.h>
40 #include <linux/atmel_pdc.h>
41 #include <linux/uaccess.h>
42 #include <linux/platform_data/atmel.h>
43 #include <linux/timer.h>
44 #include <linux/gpio.h>
45 #include <linux/gpio/consumer.h>
46 #include <linux/err.h>
47 #include <linux/irq.h>
48 #include <linux/suspend.h>
52 #include <asm/ioctls.h>
54 #define PDC_BUFFER_SIZE 512
55 /* Revisit: We should calculate this based on the actual port settings */
56 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
58 /* The minium number of data FIFOs should be able to contain */
59 #define ATMEL_MIN_FIFO_SIZE 8
61 * These two offsets are substracted from the RX FIFO size to define the RTS
62 * high and low thresholds
64 #define ATMEL_RTS_HIGH_OFFSET 16
65 #define ATMEL_RTS_LOW_OFFSET 20
67 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
71 #include <linux/serial_core.h>
73 #include "serial_mctrl_gpio.h"
74 #include "atmel_serial.h"
76 static void atmel_start_rx(struct uart_port *port);
77 static void atmel_stop_rx(struct uart_port *port);
79 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
81 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
82 * should coexist with the 8250 driver, such as if we have an external 16C550
84 #define SERIAL_ATMEL_MAJOR 204
85 #define MINOR_START 154
86 #define ATMEL_DEVICENAME "ttyAT"
90 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
91 * name, but it is legally reserved for the 8250 driver. */
92 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
93 #define MINOR_START 64
94 #define ATMEL_DEVICENAME "ttyS"
98 #define ATMEL_ISR_PASS_LIMIT 256
100 struct atmel_dma_buffer {
103 unsigned int dma_size;
107 struct atmel_uart_char {
113 * Be careful, the real size of the ring buffer is
114 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
115 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
118 #define ATMEL_SERIAL_RINGSIZE 1024
121 * at91: 6 USARTs and one DBGU port (SAM9260)
122 * samx7: 3 USARTs and 5 UARTs
124 #define ATMEL_MAX_UART 8
127 * We wrap our port structure around the generic uart_port.
129 struct atmel_uart_port {
130 struct uart_port uart; /* uart */
131 struct clk *clk; /* uart clock */
132 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
133 u32 backup_imr; /* IMR saved during suspend */
134 int break_active; /* break being received */
136 bool use_dma_rx; /* enable DMA receiver */
137 bool use_pdc_rx; /* enable PDC receiver */
138 short pdc_rx_idx; /* current PDC RX buffer */
139 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
141 bool use_dma_tx; /* enable DMA transmitter */
142 bool use_pdc_tx; /* enable PDC transmitter */
143 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
145 spinlock_t lock_tx; /* port lock */
146 spinlock_t lock_rx; /* port lock */
147 struct dma_chan *chan_tx;
148 struct dma_chan *chan_rx;
149 struct dma_async_tx_descriptor *desc_tx;
150 struct dma_async_tx_descriptor *desc_rx;
151 dma_cookie_t cookie_tx;
152 dma_cookie_t cookie_rx;
153 struct scatterlist sg_tx;
154 struct scatterlist sg_rx;
155 struct tasklet_struct tasklet_rx;
156 struct tasklet_struct tasklet_tx;
157 atomic_t tasklet_shutdown;
158 unsigned int irq_status_prev;
161 struct circ_buf rx_ring;
163 struct mctrl_gpios *gpios;
164 unsigned int tx_done_mask;
169 u32 rtor; /* address of receiver timeout register if it exists */
170 bool has_frac_baudrate;
172 struct timer_list uart_timer;
175 unsigned int pending;
176 unsigned int pending_status;
177 spinlock_t lock_suspended;
179 bool hd_start_rx; /* can start RX during half-duplex operation */
194 int (*prepare_rx)(struct uart_port *port);
195 int (*prepare_tx)(struct uart_port *port);
196 void (*schedule_rx)(struct uart_port *port);
197 void (*schedule_tx)(struct uart_port *port);
198 void (*release_rx)(struct uart_port *port);
199 void (*release_tx)(struct uart_port *port);
202 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
203 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
206 static struct console atmel_console;
209 #if defined(CONFIG_OF)
210 static const struct of_device_id atmel_serial_dt_ids[] = {
211 { .compatible = "atmel,at91rm9200-usart" },
212 { .compatible = "atmel,at91sam9260-usart" },
217 static inline struct atmel_uart_port *
218 to_atmel_uart_port(struct uart_port *uart)
220 return container_of(uart, struct atmel_uart_port, uart);
223 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
225 return __raw_readl(port->membase + reg);
228 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
230 __raw_writel(value, port->membase + reg);
233 static inline u8 atmel_uart_read_char(struct uart_port *port)
235 return __raw_readb(port->membase + ATMEL_US_RHR);
238 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
240 __raw_writeb(value, port->membase + ATMEL_US_THR);
243 static inline int atmel_uart_is_half_duplex(struct uart_port *port)
245 return (port->rs485.flags & SER_RS485_ENABLED) &&
246 !(port->rs485.flags & SER_RS485_RX_DURING_TX);
249 #ifdef CONFIG_SERIAL_ATMEL_PDC
250 static bool atmel_use_pdc_rx(struct uart_port *port)
252 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
254 return atmel_port->use_pdc_rx;
257 static bool atmel_use_pdc_tx(struct uart_port *port)
259 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
261 return atmel_port->use_pdc_tx;
264 static bool atmel_use_pdc_rx(struct uart_port *port)
269 static bool atmel_use_pdc_tx(struct uart_port *port)
275 static bool atmel_use_dma_tx(struct uart_port *port)
277 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
279 return atmel_port->use_dma_tx;
282 static bool atmel_use_dma_rx(struct uart_port *port)
284 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
286 return atmel_port->use_dma_rx;
289 static bool atmel_use_fifo(struct uart_port *port)
291 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
293 return atmel_port->fifo_size;
296 static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
297 struct tasklet_struct *t)
299 if (!atomic_read(&atmel_port->tasklet_shutdown))
303 static unsigned int atmel_get_lines_status(struct uart_port *port)
305 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
306 unsigned int status, ret = 0;
308 status = atmel_uart_readl(port, ATMEL_US_CSR);
310 mctrl_gpio_get(atmel_port->gpios, &ret);
312 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
315 status &= ~ATMEL_US_CTS;
317 status |= ATMEL_US_CTS;
320 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
323 status &= ~ATMEL_US_DSR;
325 status |= ATMEL_US_DSR;
328 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
331 status &= ~ATMEL_US_RI;
333 status |= ATMEL_US_RI;
336 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
339 status &= ~ATMEL_US_DCD;
341 status |= ATMEL_US_DCD;
347 /* Enable or disable the rs485 support */
348 static int atmel_config_rs485(struct uart_port *port,
349 struct serial_rs485 *rs485conf)
351 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
354 /* Disable interrupts */
355 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
357 mode = atmel_uart_readl(port, ATMEL_US_MR);
359 /* Resetting serial mode to RS232 (0x0) */
360 mode &= ~ATMEL_US_USMODE;
362 port->rs485 = *rs485conf;
364 if (rs485conf->flags & SER_RS485_ENABLED) {
365 dev_dbg(port->dev, "Setting UART to RS485\n");
366 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
367 atmel_uart_writel(port, ATMEL_US_TTGR,
368 rs485conf->delay_rts_after_send);
369 mode |= ATMEL_US_USMODE_RS485;
371 dev_dbg(port->dev, "Setting UART to RS232\n");
372 if (atmel_use_pdc_tx(port))
373 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
376 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
378 atmel_uart_writel(port, ATMEL_US_MR, mode);
380 /* Enable interrupts */
381 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
387 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
389 static u_int atmel_tx_empty(struct uart_port *port)
391 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
397 * Set state of the modem control output lines
399 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
401 unsigned int control = 0;
402 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
403 unsigned int rts_paused, rts_ready;
404 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
406 /* override mode to RS485 if needed, otherwise keep the current mode */
407 if (port->rs485.flags & SER_RS485_ENABLED) {
408 atmel_uart_writel(port, ATMEL_US_TTGR,
409 port->rs485.delay_rts_after_send);
410 mode &= ~ATMEL_US_USMODE;
411 mode |= ATMEL_US_USMODE_RS485;
414 /* set the RTS line state according to the mode */
415 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
416 /* force RTS line to high level */
417 rts_paused = ATMEL_US_RTSEN;
419 /* give the control of the RTS line back to the hardware */
420 rts_ready = ATMEL_US_RTSDIS;
422 /* force RTS line to high level */
423 rts_paused = ATMEL_US_RTSDIS;
425 /* force RTS line to low level */
426 rts_ready = ATMEL_US_RTSEN;
429 if (mctrl & TIOCM_RTS)
430 control |= rts_ready;
432 control |= rts_paused;
434 if (mctrl & TIOCM_DTR)
435 control |= ATMEL_US_DTREN;
437 control |= ATMEL_US_DTRDIS;
439 atmel_uart_writel(port, ATMEL_US_CR, control);
441 mctrl_gpio_set(atmel_port->gpios, mctrl);
443 /* Local loopback mode? */
444 mode &= ~ATMEL_US_CHMODE;
445 if (mctrl & TIOCM_LOOP)
446 mode |= ATMEL_US_CHMODE_LOC_LOOP;
448 mode |= ATMEL_US_CHMODE_NORMAL;
450 atmel_uart_writel(port, ATMEL_US_MR, mode);
454 * Get state of the modem control input lines
456 static u_int atmel_get_mctrl(struct uart_port *port)
458 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
459 unsigned int ret = 0, status;
461 status = atmel_uart_readl(port, ATMEL_US_CSR);
464 * The control signals are active low.
466 if (!(status & ATMEL_US_DCD))
468 if (!(status & ATMEL_US_CTS))
470 if (!(status & ATMEL_US_DSR))
472 if (!(status & ATMEL_US_RI))
475 return mctrl_gpio_get(atmel_port->gpios, &ret);
481 static void atmel_stop_tx(struct uart_port *port)
483 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
485 if (atmel_use_pdc_tx(port)) {
486 /* disable PDC transmit */
487 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
491 * Disable the transmitter.
492 * This is mandatory when DMA is used, otherwise the DMA buffer
493 * is fully transmitted.
495 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
497 /* Disable interrupts */
498 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
500 if (atmel_uart_is_half_duplex(port))
501 if (!atomic_read(&atmel_port->tasklet_shutdown))
502 atmel_start_rx(port);
507 * Start transmitting.
509 static void atmel_start_tx(struct uart_port *port)
511 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
513 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
515 /* The transmitter is already running. Yes, we
519 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
520 if (atmel_uart_is_half_duplex(port))
523 if (atmel_use_pdc_tx(port))
524 /* re-enable PDC transmit */
525 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
527 /* Enable interrupts */
528 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
530 /* re-enable the transmitter */
531 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
535 * start receiving - port is in process of being opened.
537 static void atmel_start_rx(struct uart_port *port)
539 /* reset status and receiver */
540 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
542 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
544 if (atmel_use_pdc_rx(port)) {
545 /* enable PDC controller */
546 atmel_uart_writel(port, ATMEL_US_IER,
547 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
548 port->read_status_mask);
549 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
551 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
556 * Stop receiving - port is in process of being closed.
558 static void atmel_stop_rx(struct uart_port *port)
560 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
562 if (atmel_use_pdc_rx(port)) {
563 /* disable PDC receive */
564 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
565 atmel_uart_writel(port, ATMEL_US_IDR,
566 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
567 port->read_status_mask);
569 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
574 * Enable modem status interrupts
576 static void atmel_enable_ms(struct uart_port *port)
578 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
582 * Interrupt should not be enabled twice
584 if (atmel_port->ms_irq_enabled)
587 atmel_port->ms_irq_enabled = true;
589 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
590 ier |= ATMEL_US_CTSIC;
592 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
593 ier |= ATMEL_US_DSRIC;
595 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
596 ier |= ATMEL_US_RIIC;
598 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
599 ier |= ATMEL_US_DCDIC;
601 atmel_uart_writel(port, ATMEL_US_IER, ier);
603 mctrl_gpio_enable_ms(atmel_port->gpios);
607 * Disable modem status interrupts
609 static void atmel_disable_ms(struct uart_port *port)
611 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
615 * Interrupt should not be disabled twice
617 if (!atmel_port->ms_irq_enabled)
620 atmel_port->ms_irq_enabled = false;
622 mctrl_gpio_disable_ms(atmel_port->gpios);
624 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
625 idr |= ATMEL_US_CTSIC;
627 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
628 idr |= ATMEL_US_DSRIC;
630 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
631 idr |= ATMEL_US_RIIC;
633 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
634 idr |= ATMEL_US_DCDIC;
636 atmel_uart_writel(port, ATMEL_US_IDR, idr);
640 * Control the transmission of a break signal
642 static void atmel_break_ctl(struct uart_port *port, int break_state)
644 if (break_state != 0)
646 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
649 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
653 * Stores the incoming character in the ring buffer
656 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
659 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
660 struct circ_buf *ring = &atmel_port->rx_ring;
661 struct atmel_uart_char *c;
663 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
664 /* Buffer overflow, ignore char */
667 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
671 /* Make sure the character is stored before we update head. */
674 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
678 * Deal with parity, framing and overrun errors.
680 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
683 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
685 if (status & ATMEL_US_RXBRK) {
686 /* ignore side-effect */
687 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
690 if (status & ATMEL_US_PARE)
691 port->icount.parity++;
692 if (status & ATMEL_US_FRAME)
693 port->icount.frame++;
694 if (status & ATMEL_US_OVRE)
695 port->icount.overrun++;
699 * Characters received (called from interrupt handler)
701 static void atmel_rx_chars(struct uart_port *port)
703 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
704 unsigned int status, ch;
706 status = atmel_uart_readl(port, ATMEL_US_CSR);
707 while (status & ATMEL_US_RXRDY) {
708 ch = atmel_uart_read_char(port);
711 * note that the error handling code is
712 * out of the main execution path
714 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
715 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
716 || atmel_port->break_active)) {
719 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
721 if (status & ATMEL_US_RXBRK
722 && !atmel_port->break_active) {
723 atmel_port->break_active = 1;
724 atmel_uart_writel(port, ATMEL_US_IER,
728 * This is either the end-of-break
729 * condition or we've received at
730 * least one character without RXBRK
731 * being set. In both cases, the next
732 * RXBRK will indicate start-of-break.
734 atmel_uart_writel(port, ATMEL_US_IDR,
736 status &= ~ATMEL_US_RXBRK;
737 atmel_port->break_active = 0;
741 atmel_buffer_rx_char(port, status, ch);
742 status = atmel_uart_readl(port, ATMEL_US_CSR);
745 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
749 * Transmit characters (called from tasklet with TXRDY interrupt
752 static void atmel_tx_chars(struct uart_port *port)
754 struct circ_buf *xmit = &port->state->xmit;
755 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
758 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
759 atmel_uart_write_char(port, port->x_char);
763 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
766 while (atmel_uart_readl(port, ATMEL_US_CSR) &
767 atmel_port->tx_done_mask) {
768 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
769 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
771 if (uart_circ_empty(xmit))
775 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
776 uart_write_wakeup(port);
778 if (!uart_circ_empty(xmit))
779 /* Enable interrupts */
780 atmel_uart_writel(port, ATMEL_US_IER,
781 atmel_port->tx_done_mask);
784 static void atmel_complete_tx_dma(void *arg)
786 struct atmel_uart_port *atmel_port = arg;
787 struct uart_port *port = &atmel_port->uart;
788 struct circ_buf *xmit = &port->state->xmit;
789 struct dma_chan *chan = atmel_port->chan_tx;
792 spin_lock_irqsave(&port->lock, flags);
795 dmaengine_terminate_all(chan);
796 xmit->tail += atmel_port->tx_len;
797 xmit->tail &= UART_XMIT_SIZE - 1;
799 port->icount.tx += atmel_port->tx_len;
801 spin_lock_irq(&atmel_port->lock_tx);
802 async_tx_ack(atmel_port->desc_tx);
803 atmel_port->cookie_tx = -EINVAL;
804 atmel_port->desc_tx = NULL;
805 spin_unlock_irq(&atmel_port->lock_tx);
807 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
808 uart_write_wakeup(port);
811 * xmit is a circular buffer so, if we have just send data from
812 * xmit->tail to the end of xmit->buf, now we have to transmit the
813 * remaining data from the beginning of xmit->buf to xmit->head.
815 if (!uart_circ_empty(xmit))
816 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
817 else if (atmel_uart_is_half_duplex(port)) {
819 * DMA done, re-enable TXEMPTY and signal that we can stop
820 * TX and start RX for RS485
822 atmel_port->hd_start_rx = true;
823 atmel_uart_writel(port, ATMEL_US_IER,
824 atmel_port->tx_done_mask);
827 spin_unlock_irqrestore(&port->lock, flags);
830 static void atmel_release_tx_dma(struct uart_port *port)
832 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
833 struct dma_chan *chan = atmel_port->chan_tx;
836 dmaengine_terminate_all(chan);
837 dma_release_channel(chan);
838 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
842 atmel_port->desc_tx = NULL;
843 atmel_port->chan_tx = NULL;
844 atmel_port->cookie_tx = -EINVAL;
848 * Called from tasklet with TXRDY interrupt is disabled.
850 static void atmel_tx_dma(struct uart_port *port)
852 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
853 struct circ_buf *xmit = &port->state->xmit;
854 struct dma_chan *chan = atmel_port->chan_tx;
855 struct dma_async_tx_descriptor *desc;
856 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
857 unsigned int tx_len, part1_len, part2_len, sg_len;
858 dma_addr_t phys_addr;
860 /* Make sure we have an idle channel */
861 if (atmel_port->desc_tx != NULL)
864 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
867 * Port xmit buffer is already mapped,
868 * and it is one page... Just adjust
869 * offsets and lengths. Since it is a circular buffer,
870 * we have to transmit till the end, and then the rest.
871 * Take the port lock to get a
872 * consistent xmit buffer state.
874 tx_len = CIRC_CNT_TO_END(xmit->head,
878 if (atmel_port->fifo_size) {
879 /* multi data mode */
880 part1_len = (tx_len & ~0x3); /* DWORD access */
881 part2_len = (tx_len & 0x3); /* BYTE access */
883 /* single data (legacy) mode */
885 part2_len = tx_len; /* BYTE access only */
888 sg_init_table(sgl, 2);
890 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
893 sg_dma_address(sg) = phys_addr;
894 sg_dma_len(sg) = part1_len;
896 phys_addr += part1_len;
901 sg_dma_address(sg) = phys_addr;
902 sg_dma_len(sg) = part2_len;
906 * save tx_len so atmel_complete_tx_dma() will increase
907 * xmit->tail correctly
909 atmel_port->tx_len = tx_len;
911 desc = dmaengine_prep_slave_sg(chan,
918 dev_err(port->dev, "Failed to send via dma!\n");
922 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
924 atmel_port->desc_tx = desc;
925 desc->callback = atmel_complete_tx_dma;
926 desc->callback_param = atmel_port;
927 atmel_port->cookie_tx = dmaengine_submit(desc);
930 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
931 uart_write_wakeup(port);
934 static int atmel_prepare_tx_dma(struct uart_port *port)
936 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
938 struct dma_slave_config config;
942 dma_cap_set(DMA_SLAVE, mask);
944 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
945 if (atmel_port->chan_tx == NULL)
947 dev_info(port->dev, "using %s for tx DMA transfers\n",
948 dma_chan_name(atmel_port->chan_tx));
950 spin_lock_init(&atmel_port->lock_tx);
951 sg_init_table(&atmel_port->sg_tx, 1);
952 /* UART circular tx buffer is an aligned page. */
953 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
954 sg_set_page(&atmel_port->sg_tx,
955 virt_to_page(port->state->xmit.buf),
957 offset_in_page(port->state->xmit.buf));
958 nent = dma_map_sg(port->dev,
964 dev_dbg(port->dev, "need to release resource of dma\n");
967 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
968 sg_dma_len(&atmel_port->sg_tx),
969 port->state->xmit.buf,
970 &sg_dma_address(&atmel_port->sg_tx));
973 /* Configure the slave DMA */
974 memset(&config, 0, sizeof(config));
975 config.direction = DMA_MEM_TO_DEV;
976 config.dst_addr_width = (atmel_port->fifo_size) ?
977 DMA_SLAVE_BUSWIDTH_4_BYTES :
978 DMA_SLAVE_BUSWIDTH_1_BYTE;
979 config.dst_addr = port->mapbase + ATMEL_US_THR;
980 config.dst_maxburst = 1;
982 ret = dmaengine_slave_config(atmel_port->chan_tx,
985 dev_err(port->dev, "DMA tx slave configuration failed\n");
992 dev_err(port->dev, "TX channel not available, switch to pio\n");
993 atmel_port->use_dma_tx = 0;
994 if (atmel_port->chan_tx)
995 atmel_release_tx_dma(port);
999 static void atmel_complete_rx_dma(void *arg)
1001 struct uart_port *port = arg;
1002 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1004 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1007 static void atmel_release_rx_dma(struct uart_port *port)
1009 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1010 struct dma_chan *chan = atmel_port->chan_rx;
1013 dmaengine_terminate_all(chan);
1014 dma_release_channel(chan);
1015 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1019 atmel_port->desc_rx = NULL;
1020 atmel_port->chan_rx = NULL;
1021 atmel_port->cookie_rx = -EINVAL;
1024 static void atmel_rx_from_dma(struct uart_port *port)
1026 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1027 struct tty_port *tport = &port->state->port;
1028 struct circ_buf *ring = &atmel_port->rx_ring;
1029 struct dma_chan *chan = atmel_port->chan_rx;
1030 struct dma_tx_state state;
1031 enum dma_status dmastat;
1035 /* Reset the UART timeout early so that we don't miss one */
1036 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1037 dmastat = dmaengine_tx_status(chan,
1038 atmel_port->cookie_rx,
1040 /* Restart a new tasklet if DMA status is error */
1041 if (dmastat == DMA_ERROR) {
1042 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1043 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1044 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1048 /* CPU claims ownership of RX DMA buffer */
1049 dma_sync_sg_for_cpu(port->dev,
1055 * ring->head points to the end of data already written by the DMA.
1056 * ring->tail points to the beginning of data to be read by the
1058 * The current transfer size should not be larger than the dma buffer
1061 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1062 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1064 * At this point ring->head may point to the first byte right after the
1065 * last byte of the dma buffer:
1066 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1068 * However ring->tail must always points inside the dma buffer:
1069 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1071 * Since we use a ring buffer, we have to handle the case
1072 * where head is lower than tail. In such a case, we first read from
1073 * tail to the end of the buffer then reset tail.
1075 if (ring->head < ring->tail) {
1076 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1078 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1080 port->icount.rx += count;
1083 /* Finally we read data from tail to head */
1084 if (ring->tail < ring->head) {
1085 count = ring->head - ring->tail;
1087 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1088 /* Wrap ring->head if needed */
1089 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1091 ring->tail = ring->head;
1092 port->icount.rx += count;
1095 /* USART retreives ownership of RX DMA buffer */
1096 dma_sync_sg_for_device(port->dev,
1102 * Drop the lock here since it might end up calling
1103 * uart_start(), which takes the lock.
1105 spin_unlock(&port->lock);
1106 tty_flip_buffer_push(tport);
1107 spin_lock(&port->lock);
1109 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1112 static int atmel_prepare_rx_dma(struct uart_port *port)
1114 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1115 struct dma_async_tx_descriptor *desc;
1116 dma_cap_mask_t mask;
1117 struct dma_slave_config config;
1118 struct circ_buf *ring;
1121 ring = &atmel_port->rx_ring;
1124 dma_cap_set(DMA_CYCLIC, mask);
1126 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1127 if (atmel_port->chan_rx == NULL)
1129 dev_info(port->dev, "using %s for rx DMA transfers\n",
1130 dma_chan_name(atmel_port->chan_rx));
1132 spin_lock_init(&atmel_port->lock_rx);
1133 sg_init_table(&atmel_port->sg_rx, 1);
1134 /* UART circular rx buffer is an aligned page. */
1135 BUG_ON(!PAGE_ALIGNED(ring->buf));
1136 sg_set_page(&atmel_port->sg_rx,
1137 virt_to_page(ring->buf),
1138 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1139 offset_in_page(ring->buf));
1140 nent = dma_map_sg(port->dev,
1146 dev_dbg(port->dev, "need to release resource of dma\n");
1149 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1150 sg_dma_len(&atmel_port->sg_rx),
1152 &sg_dma_address(&atmel_port->sg_rx));
1155 /* Configure the slave DMA */
1156 memset(&config, 0, sizeof(config));
1157 config.direction = DMA_DEV_TO_MEM;
1158 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1159 config.src_addr = port->mapbase + ATMEL_US_RHR;
1160 config.src_maxburst = 1;
1162 ret = dmaengine_slave_config(atmel_port->chan_rx,
1165 dev_err(port->dev, "DMA rx slave configuration failed\n");
1169 * Prepare a cyclic dma transfer, assign 2 descriptors,
1170 * each one is half ring buffer size
1172 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1173 sg_dma_address(&atmel_port->sg_rx),
1174 sg_dma_len(&atmel_port->sg_rx),
1175 sg_dma_len(&atmel_port->sg_rx)/2,
1177 DMA_PREP_INTERRUPT);
1179 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1182 desc->callback = atmel_complete_rx_dma;
1183 desc->callback_param = port;
1184 atmel_port->desc_rx = desc;
1185 atmel_port->cookie_rx = dmaengine_submit(desc);
1190 dev_err(port->dev, "RX channel not available, switch to pio\n");
1191 atmel_port->use_dma_rx = 0;
1192 if (atmel_port->chan_rx)
1193 atmel_release_rx_dma(port);
1197 static void atmel_uart_timer_callback(unsigned long data)
1199 struct uart_port *port = (void *)data;
1200 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1202 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1203 tasklet_schedule(&atmel_port->tasklet_rx);
1204 mod_timer(&atmel_port->uart_timer,
1205 jiffies + uart_poll_timeout(port));
1210 * receive interrupt handler.
1213 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1215 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1217 if (atmel_use_pdc_rx(port)) {
1219 * PDC receive. Just schedule the tasklet and let it
1220 * figure out the details.
1222 * TODO: We're not handling error flags correctly at
1225 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1226 atmel_uart_writel(port, ATMEL_US_IDR,
1227 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1228 atmel_tasklet_schedule(atmel_port,
1229 &atmel_port->tasklet_rx);
1232 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1233 ATMEL_US_FRAME | ATMEL_US_PARE))
1234 atmel_pdc_rxerr(port, pending);
1237 if (atmel_use_dma_rx(port)) {
1238 if (pending & ATMEL_US_TIMEOUT) {
1239 atmel_uart_writel(port, ATMEL_US_IDR,
1241 atmel_tasklet_schedule(atmel_port,
1242 &atmel_port->tasklet_rx);
1246 /* Interrupt receive */
1247 if (pending & ATMEL_US_RXRDY)
1248 atmel_rx_chars(port);
1249 else if (pending & ATMEL_US_RXBRK) {
1251 * End of break detected. If it came along with a
1252 * character, atmel_rx_chars will handle it.
1254 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1255 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1256 atmel_port->break_active = 0;
1261 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1264 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1266 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1268 if (pending & atmel_port->tx_done_mask) {
1269 atmel_uart_writel(port, ATMEL_US_IDR,
1270 atmel_port->tx_done_mask);
1272 /* Start RX if flag was set and FIFO is empty */
1273 if (atmel_port->hd_start_rx) {
1274 if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1275 & ATMEL_US_TXEMPTY))
1276 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1278 atmel_port->hd_start_rx = false;
1279 atmel_start_rx(port);
1282 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1287 * status flags interrupt handler.
1290 atmel_handle_status(struct uart_port *port, unsigned int pending,
1291 unsigned int status)
1293 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1294 unsigned int status_change;
1296 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1297 | ATMEL_US_CTSIC)) {
1298 status_change = status ^ atmel_port->irq_status_prev;
1299 atmel_port->irq_status_prev = status;
1301 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1302 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1303 /* TODO: All reads to CSR will clear these interrupts! */
1304 if (status_change & ATMEL_US_RI)
1306 if (status_change & ATMEL_US_DSR)
1308 if (status_change & ATMEL_US_DCD)
1309 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1310 if (status_change & ATMEL_US_CTS)
1311 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1313 wake_up_interruptible(&port->state->port.delta_msr_wait);
1321 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1323 struct uart_port *port = dev_id;
1324 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1325 unsigned int status, pending, mask, pass_counter = 0;
1327 spin_lock(&atmel_port->lock_suspended);
1330 status = atmel_get_lines_status(port);
1331 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1332 pending = status & mask;
1336 if (atmel_port->suspended) {
1337 atmel_port->pending |= pending;
1338 atmel_port->pending_status = status;
1339 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1344 atmel_handle_receive(port, pending);
1345 atmel_handle_status(port, pending, status);
1346 atmel_handle_transmit(port, pending);
1347 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1349 spin_unlock(&atmel_port->lock_suspended);
1351 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1354 static void atmel_release_tx_pdc(struct uart_port *port)
1356 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1357 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1359 dma_unmap_single(port->dev,
1366 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1368 static void atmel_tx_pdc(struct uart_port *port)
1370 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1371 struct circ_buf *xmit = &port->state->xmit;
1372 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1375 /* nothing left to transmit? */
1376 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1379 xmit->tail += pdc->ofs;
1380 xmit->tail &= UART_XMIT_SIZE - 1;
1382 port->icount.tx += pdc->ofs;
1385 /* more to transmit - setup next transfer */
1387 /* disable PDC transmit */
1388 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1390 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1391 dma_sync_single_for_device(port->dev,
1396 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1399 atmel_uart_writel(port, ATMEL_PDC_TPR,
1400 pdc->dma_addr + xmit->tail);
1401 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1402 /* re-enable PDC transmit */
1403 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1404 /* Enable interrupts */
1405 atmel_uart_writel(port, ATMEL_US_IER,
1406 atmel_port->tx_done_mask);
1408 if (atmel_uart_is_half_duplex(port)) {
1409 /* DMA done, stop TX, start RX for RS485 */
1410 atmel_start_rx(port);
1414 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1415 uart_write_wakeup(port);
1418 static int atmel_prepare_tx_pdc(struct uart_port *port)
1420 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1421 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1422 struct circ_buf *xmit = &port->state->xmit;
1424 pdc->buf = xmit->buf;
1425 pdc->dma_addr = dma_map_single(port->dev,
1429 pdc->dma_size = UART_XMIT_SIZE;
1435 static void atmel_rx_from_ring(struct uart_port *port)
1437 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1438 struct circ_buf *ring = &atmel_port->rx_ring;
1440 unsigned int status;
1442 while (ring->head != ring->tail) {
1443 struct atmel_uart_char c;
1445 /* Make sure c is loaded after head. */
1448 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1450 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1457 * note that the error handling code is
1458 * out of the main execution path
1460 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1461 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1462 if (status & ATMEL_US_RXBRK) {
1463 /* ignore side-effect */
1464 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1467 if (uart_handle_break(port))
1470 if (status & ATMEL_US_PARE)
1471 port->icount.parity++;
1472 if (status & ATMEL_US_FRAME)
1473 port->icount.frame++;
1474 if (status & ATMEL_US_OVRE)
1475 port->icount.overrun++;
1477 status &= port->read_status_mask;
1479 if (status & ATMEL_US_RXBRK)
1481 else if (status & ATMEL_US_PARE)
1483 else if (status & ATMEL_US_FRAME)
1488 if (uart_handle_sysrq_char(port, c.ch))
1491 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1495 * Drop the lock here since it might end up calling
1496 * uart_start(), which takes the lock.
1498 spin_unlock(&port->lock);
1499 tty_flip_buffer_push(&port->state->port);
1500 spin_lock(&port->lock);
1503 static void atmel_release_rx_pdc(struct uart_port *port)
1505 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1508 for (i = 0; i < 2; i++) {
1509 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1511 dma_unmap_single(port->dev,
1519 static void atmel_rx_from_pdc(struct uart_port *port)
1521 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1522 struct tty_port *tport = &port->state->port;
1523 struct atmel_dma_buffer *pdc;
1524 int rx_idx = atmel_port->pdc_rx_idx;
1530 /* Reset the UART timeout early so that we don't miss one */
1531 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1533 pdc = &atmel_port->pdc_rx[rx_idx];
1534 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1537 /* If the PDC has switched buffers, RPR won't contain
1538 * any address within the current buffer. Since head
1539 * is unsigned, we just need a one-way comparison to
1542 * In this case, we just need to consume the entire
1543 * buffer and resubmit it for DMA. This will clear the
1544 * ENDRX bit as well, so that we can safely re-enable
1545 * all interrupts below.
1547 head = min(head, pdc->dma_size);
1549 if (likely(head != tail)) {
1550 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1551 pdc->dma_size, DMA_FROM_DEVICE);
1554 * head will only wrap around when we recycle
1555 * the DMA buffer, and when that happens, we
1556 * explicitly set tail to 0. So head will
1557 * always be greater than tail.
1559 count = head - tail;
1561 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1564 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1565 pdc->dma_size, DMA_FROM_DEVICE);
1567 port->icount.rx += count;
1572 * If the current buffer is full, we need to check if
1573 * the next one contains any additional data.
1575 if (head >= pdc->dma_size) {
1577 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1578 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1581 atmel_port->pdc_rx_idx = rx_idx;
1583 } while (head >= pdc->dma_size);
1586 * Drop the lock here since it might end up calling
1587 * uart_start(), which takes the lock.
1589 spin_unlock(&port->lock);
1590 tty_flip_buffer_push(tport);
1591 spin_lock(&port->lock);
1593 atmel_uart_writel(port, ATMEL_US_IER,
1594 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1597 static int atmel_prepare_rx_pdc(struct uart_port *port)
1599 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1602 for (i = 0; i < 2; i++) {
1603 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1605 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1606 if (pdc->buf == NULL) {
1608 dma_unmap_single(port->dev,
1609 atmel_port->pdc_rx[0].dma_addr,
1612 kfree(atmel_port->pdc_rx[0].buf);
1614 atmel_port->use_pdc_rx = 0;
1617 pdc->dma_addr = dma_map_single(port->dev,
1621 pdc->dma_size = PDC_BUFFER_SIZE;
1625 atmel_port->pdc_rx_idx = 0;
1627 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1628 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1630 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1631 atmel_port->pdc_rx[1].dma_addr);
1632 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1638 * tasklet handling tty stuff outside the interrupt handler.
1640 static void atmel_tasklet_rx_func(unsigned long data)
1642 struct uart_port *port = (struct uart_port *)data;
1643 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1645 /* The interrupt handler does not take the lock */
1646 spin_lock(&port->lock);
1647 atmel_port->schedule_rx(port);
1648 spin_unlock(&port->lock);
1651 static void atmel_tasklet_tx_func(unsigned long data)
1653 struct uart_port *port = (struct uart_port *)data;
1654 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1656 /* The interrupt handler does not take the lock */
1657 spin_lock(&port->lock);
1658 atmel_port->schedule_tx(port);
1659 spin_unlock(&port->lock);
1662 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1663 struct platform_device *pdev)
1665 struct device_node *np = pdev->dev.of_node;
1667 /* DMA/PDC usage specification */
1668 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1669 if (of_property_read_bool(np, "dmas")) {
1670 atmel_port->use_dma_rx = true;
1671 atmel_port->use_pdc_rx = false;
1673 atmel_port->use_dma_rx = false;
1674 atmel_port->use_pdc_rx = true;
1677 atmel_port->use_dma_rx = false;
1678 atmel_port->use_pdc_rx = false;
1681 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1682 if (of_property_read_bool(np, "dmas")) {
1683 atmel_port->use_dma_tx = true;
1684 atmel_port->use_pdc_tx = false;
1686 atmel_port->use_dma_tx = false;
1687 atmel_port->use_pdc_tx = true;
1690 atmel_port->use_dma_tx = false;
1691 atmel_port->use_pdc_tx = false;
1695 static void atmel_init_rs485(struct uart_port *port,
1696 struct platform_device *pdev)
1698 struct device_node *np = pdev->dev.of_node;
1700 struct serial_rs485 *rs485conf = &port->rs485;
1703 /* rs485 properties */
1704 if (of_property_read_u32_array(np, "rs485-rts-delay",
1705 rs485_delay, 2) == 0) {
1706 rs485conf->delay_rts_before_send = rs485_delay[0];
1707 rs485conf->delay_rts_after_send = rs485_delay[1];
1708 rs485conf->flags = 0;
1711 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1712 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1714 if (of_get_property(np, "linux,rs485-enabled-at-boot-time", NULL))
1715 rs485conf->flags |= SER_RS485_ENABLED;
1718 static void atmel_set_ops(struct uart_port *port)
1720 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1722 if (atmel_use_dma_rx(port)) {
1723 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1724 atmel_port->schedule_rx = &atmel_rx_from_dma;
1725 atmel_port->release_rx = &atmel_release_rx_dma;
1726 } else if (atmel_use_pdc_rx(port)) {
1727 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1728 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1729 atmel_port->release_rx = &atmel_release_rx_pdc;
1731 atmel_port->prepare_rx = NULL;
1732 atmel_port->schedule_rx = &atmel_rx_from_ring;
1733 atmel_port->release_rx = NULL;
1736 if (atmel_use_dma_tx(port)) {
1737 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1738 atmel_port->schedule_tx = &atmel_tx_dma;
1739 atmel_port->release_tx = &atmel_release_tx_dma;
1740 } else if (atmel_use_pdc_tx(port)) {
1741 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1742 atmel_port->schedule_tx = &atmel_tx_pdc;
1743 atmel_port->release_tx = &atmel_release_tx_pdc;
1745 atmel_port->prepare_tx = NULL;
1746 atmel_port->schedule_tx = &atmel_tx_chars;
1747 atmel_port->release_tx = NULL;
1752 * Get ip name usart or uart
1754 static void atmel_get_ip_name(struct uart_port *port)
1756 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1757 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1759 u32 usart, dbgu_uart, new_uart;
1760 /* ASCII decoding for IP version */
1761 usart = 0x55534152; /* USAR(T) */
1762 dbgu_uart = 0x44424755; /* DBGU */
1763 new_uart = 0x55415254; /* UART */
1766 * Only USART devices from at91sam9260 SOC implement fractional
1767 * baudrate. It is available for all asynchronous modes, with the
1768 * following restriction: the sampling clock's duty cycle is not
1771 atmel_port->has_frac_baudrate = false;
1772 atmel_port->has_hw_timer = false;
1774 if (name == new_uart) {
1775 dev_dbg(port->dev, "Uart with hw timer");
1776 atmel_port->has_hw_timer = true;
1777 atmel_port->rtor = ATMEL_UA_RTOR;
1778 } else if (name == usart) {
1779 dev_dbg(port->dev, "Usart\n");
1780 atmel_port->has_frac_baudrate = true;
1781 atmel_port->has_hw_timer = true;
1782 atmel_port->rtor = ATMEL_US_RTOR;
1783 } else if (name == dbgu_uart) {
1784 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1786 /* fallback for older SoCs: use version field */
1787 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1792 dev_dbg(port->dev, "This version is usart\n");
1793 atmel_port->has_frac_baudrate = true;
1794 atmel_port->has_hw_timer = true;
1795 atmel_port->rtor = ATMEL_US_RTOR;
1799 dev_dbg(port->dev, "This version is uart\n");
1802 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1808 * Perform initialization and enable port for reception
1810 static int atmel_startup(struct uart_port *port)
1812 struct platform_device *pdev = to_platform_device(port->dev);
1813 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1817 * Ensure that no interrupts are enabled otherwise when
1818 * request_irq() is called we could get stuck trying to
1819 * handle an unexpected interrupt
1821 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1822 atmel_port->ms_irq_enabled = false;
1827 retval = request_irq(port->irq, atmel_interrupt,
1828 IRQF_SHARED | IRQF_COND_SUSPEND,
1829 dev_name(&pdev->dev), port);
1831 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1835 atomic_set(&atmel_port->tasklet_shutdown, 0);
1836 tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func,
1837 (unsigned long)port);
1838 tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func,
1839 (unsigned long)port);
1842 * Initialize DMA (if necessary)
1844 atmel_init_property(atmel_port, pdev);
1845 atmel_set_ops(port);
1847 if (atmel_port->prepare_rx) {
1848 retval = atmel_port->prepare_rx(port);
1850 atmel_set_ops(port);
1853 if (atmel_port->prepare_tx) {
1854 retval = atmel_port->prepare_tx(port);
1856 atmel_set_ops(port);
1860 * Enable FIFO when available
1862 if (atmel_port->fifo_size) {
1863 unsigned int txrdym = ATMEL_US_ONE_DATA;
1864 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1867 atmel_uart_writel(port, ATMEL_US_CR,
1872 if (atmel_use_dma_tx(port))
1873 txrdym = ATMEL_US_FOUR_DATA;
1875 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1876 if (atmel_port->rts_high &&
1877 atmel_port->rts_low)
1878 fmr |= ATMEL_US_FRTSC |
1879 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1880 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1882 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1885 /* Save current CSR for comparison in atmel_tasklet_func() */
1886 atmel_port->irq_status_prev = atmel_get_lines_status(port);
1889 * Finally, enable the serial port
1891 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1892 /* enable xmit & rcvr */
1893 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1895 setup_timer(&atmel_port->uart_timer,
1896 atmel_uart_timer_callback,
1897 (unsigned long)port);
1899 if (atmel_use_pdc_rx(port)) {
1900 /* set UART timeout */
1901 if (!atmel_port->has_hw_timer) {
1902 mod_timer(&atmel_port->uart_timer,
1903 jiffies + uart_poll_timeout(port));
1904 /* set USART timeout */
1906 atmel_uart_writel(port, atmel_port->rtor,
1908 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1910 atmel_uart_writel(port, ATMEL_US_IER,
1911 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1913 /* enable PDC controller */
1914 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1915 } else if (atmel_use_dma_rx(port)) {
1916 /* set UART timeout */
1917 if (!atmel_port->has_hw_timer) {
1918 mod_timer(&atmel_port->uart_timer,
1919 jiffies + uart_poll_timeout(port));
1920 /* set USART timeout */
1922 atmel_uart_writel(port, atmel_port->rtor,
1924 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1926 atmel_uart_writel(port, ATMEL_US_IER,
1930 /* enable receive only */
1931 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
1938 * Flush any TX data submitted for DMA. Called when the TX circular
1941 static void atmel_flush_buffer(struct uart_port *port)
1943 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1945 if (atmel_use_pdc_tx(port)) {
1946 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
1947 atmel_port->pdc_tx.ofs = 0;
1950 * in uart_flush_buffer(), the xmit circular buffer has just
1951 * been cleared, so we have to reset tx_len accordingly.
1953 atmel_port->tx_len = 0;
1959 static void atmel_shutdown(struct uart_port *port)
1961 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1963 /* Disable modem control lines interrupts */
1964 atmel_disable_ms(port);
1966 /* Disable interrupts at device level */
1967 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1969 /* Prevent spurious interrupts from scheduling the tasklet */
1970 atomic_inc(&atmel_port->tasklet_shutdown);
1973 * Prevent any tasklets being scheduled during
1976 del_timer_sync(&atmel_port->uart_timer);
1978 /* Make sure that no interrupt is on the fly */
1979 synchronize_irq(port->irq);
1982 * Clear out any scheduled tasklets before
1983 * we destroy the buffers
1985 tasklet_kill(&atmel_port->tasklet_rx);
1986 tasklet_kill(&atmel_port->tasklet_tx);
1989 * Ensure everything is stopped and
1990 * disable port and break condition.
1992 atmel_stop_rx(port);
1993 atmel_stop_tx(port);
1995 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1998 * Shut-down the DMA.
2000 if (atmel_port->release_rx)
2001 atmel_port->release_rx(port);
2002 if (atmel_port->release_tx)
2003 atmel_port->release_tx(port);
2006 * Reset ring buffer pointers
2008 atmel_port->rx_ring.head = 0;
2009 atmel_port->rx_ring.tail = 0;
2012 * Free the interrupts
2014 free_irq(port->irq, port);
2016 atmel_flush_buffer(port);
2020 * Power / Clock management.
2022 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2023 unsigned int oldstate)
2025 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2030 * Enable the peripheral clock for this serial port.
2031 * This is called on uart_open() or a resume event.
2033 clk_prepare_enable(atmel_port->clk);
2035 /* re-enable interrupts if we disabled some on suspend */
2036 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2039 /* Back up the interrupt mask and disable all interrupts */
2040 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2041 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2044 * Disable the peripheral clock for this serial port.
2045 * This is called on uart_close() or a suspend event.
2047 clk_disable_unprepare(atmel_port->clk);
2050 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2055 * Change the port parameters
2057 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2058 struct ktermios *old)
2060 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2061 unsigned long flags;
2062 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
2064 /* save the current mode register */
2065 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2067 /* reset the mode, clock divisor, parity, stop bits and data size */
2068 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2069 ATMEL_US_PAR | ATMEL_US_USMODE);
2071 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2074 switch (termios->c_cflag & CSIZE) {
2076 mode |= ATMEL_US_CHRL_5;
2079 mode |= ATMEL_US_CHRL_6;
2082 mode |= ATMEL_US_CHRL_7;
2085 mode |= ATMEL_US_CHRL_8;
2090 if (termios->c_cflag & CSTOPB)
2091 mode |= ATMEL_US_NBSTOP_2;
2094 if (termios->c_cflag & PARENB) {
2095 /* Mark or Space parity */
2096 if (termios->c_cflag & CMSPAR) {
2097 if (termios->c_cflag & PARODD)
2098 mode |= ATMEL_US_PAR_MARK;
2100 mode |= ATMEL_US_PAR_SPACE;
2101 } else if (termios->c_cflag & PARODD)
2102 mode |= ATMEL_US_PAR_ODD;
2104 mode |= ATMEL_US_PAR_EVEN;
2106 mode |= ATMEL_US_PAR_NONE;
2108 spin_lock_irqsave(&port->lock, flags);
2110 port->read_status_mask = ATMEL_US_OVRE;
2111 if (termios->c_iflag & INPCK)
2112 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2113 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2114 port->read_status_mask |= ATMEL_US_RXBRK;
2116 if (atmel_use_pdc_rx(port))
2117 /* need to enable error interrupts */
2118 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2121 * Characters to ignore
2123 port->ignore_status_mask = 0;
2124 if (termios->c_iflag & IGNPAR)
2125 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2126 if (termios->c_iflag & IGNBRK) {
2127 port->ignore_status_mask |= ATMEL_US_RXBRK;
2129 * If we're ignoring parity and break indicators,
2130 * ignore overruns too (for real raw support).
2132 if (termios->c_iflag & IGNPAR)
2133 port->ignore_status_mask |= ATMEL_US_OVRE;
2135 /* TODO: Ignore all characters if CREAD is set.*/
2137 /* update the per-port timeout */
2138 uart_update_timeout(port, termios->c_cflag, baud);
2141 * save/disable interrupts. The tty layer will ensure that the
2142 * transmitter is empty if requested by the caller, so there's
2143 * no need to wait for it here.
2145 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2146 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2148 /* disable receiver and transmitter */
2149 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2152 if (port->rs485.flags & SER_RS485_ENABLED) {
2153 atmel_uart_writel(port, ATMEL_US_TTGR,
2154 port->rs485.delay_rts_after_send);
2155 mode |= ATMEL_US_USMODE_RS485;
2156 } else if (termios->c_cflag & CRTSCTS) {
2157 /* RS232 with hardware handshake (RTS/CTS) */
2158 if (atmel_use_fifo(port) &&
2159 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2161 * with ATMEL_US_USMODE_HWHS set, the controller will
2162 * be able to drive the RTS pin high/low when the RX
2163 * FIFO is above RXFTHRES/below RXFTHRES2.
2164 * It will also disable the transmitter when the CTS
2166 * This mode is not activated if CTS pin is a GPIO
2167 * because in this case, the transmitter is always
2168 * disabled (there must be an internal pull-up
2169 * responsible for this behaviour).
2170 * If the RTS pin is a GPIO, the controller won't be
2171 * able to drive it according to the FIFO thresholds,
2172 * but it will be handled by the driver.
2174 mode |= ATMEL_US_USMODE_HWHS;
2177 * For platforms without FIFO, the flow control is
2178 * handled by the driver.
2180 mode |= ATMEL_US_USMODE_NORMAL;
2183 /* RS232 without hadware handshake */
2184 mode |= ATMEL_US_USMODE_NORMAL;
2188 * Set the baud rate:
2189 * Fractional baudrate allows to setup output frequency more
2190 * accurately. This feature is enabled only when using normal mode.
2191 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2192 * Currently, OVER is always set to 0 so we get
2193 * baudrate = selected clock / (16 * (CD + FP / 8))
2195 * 8 CD + FP = selected clock / (2 * baudrate)
2197 if (atmel_port->has_frac_baudrate) {
2198 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2200 fp = div & ATMEL_US_FP_MASK;
2202 cd = uart_get_divisor(port, baud);
2205 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2207 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2209 quot = cd | fp << ATMEL_US_FP_OFFSET;
2211 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2213 /* set the mode, clock divisor, parity, stop bits and data size */
2214 atmel_uart_writel(port, ATMEL_US_MR, mode);
2217 * when switching the mode, set the RTS line state according to the
2218 * new mode, otherwise keep the former state
2220 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2221 unsigned int rts_state;
2223 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2224 /* let the hardware control the RTS line */
2225 rts_state = ATMEL_US_RTSDIS;
2227 /* force RTS line to low level */
2228 rts_state = ATMEL_US_RTSEN;
2231 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2234 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2235 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2237 /* restore interrupts */
2238 atmel_uart_writel(port, ATMEL_US_IER, imr);
2240 /* CTS flow-control and modem-status interrupts */
2241 if (UART_ENABLE_MS(port, termios->c_cflag))
2242 atmel_enable_ms(port);
2244 atmel_disable_ms(port);
2246 spin_unlock_irqrestore(&port->lock, flags);
2249 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2251 if (termios->c_line == N_PPS) {
2252 port->flags |= UPF_HARDPPS_CD;
2253 spin_lock_irq(&port->lock);
2254 atmel_enable_ms(port);
2255 spin_unlock_irq(&port->lock);
2257 port->flags &= ~UPF_HARDPPS_CD;
2258 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2259 spin_lock_irq(&port->lock);
2260 atmel_disable_ms(port);
2261 spin_unlock_irq(&port->lock);
2267 * Return string describing the specified port
2269 static const char *atmel_type(struct uart_port *port)
2271 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2275 * Release the memory region(s) being used by 'port'.
2277 static void atmel_release_port(struct uart_port *port)
2279 struct platform_device *pdev = to_platform_device(port->dev);
2280 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2282 release_mem_region(port->mapbase, size);
2284 if (port->flags & UPF_IOREMAP) {
2285 iounmap(port->membase);
2286 port->membase = NULL;
2291 * Request the memory region(s) being used by 'port'.
2293 static int atmel_request_port(struct uart_port *port)
2295 struct platform_device *pdev = to_platform_device(port->dev);
2296 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2298 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2301 if (port->flags & UPF_IOREMAP) {
2302 port->membase = ioremap(port->mapbase, size);
2303 if (port->membase == NULL) {
2304 release_mem_region(port->mapbase, size);
2313 * Configure/autoconfigure the port.
2315 static void atmel_config_port(struct uart_port *port, int flags)
2317 if (flags & UART_CONFIG_TYPE) {
2318 port->type = PORT_ATMEL;
2319 atmel_request_port(port);
2324 * Verify the new serial_struct (for TIOCSSERIAL).
2326 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2329 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2331 if (port->irq != ser->irq)
2333 if (ser->io_type != SERIAL_IO_MEM)
2335 if (port->uartclk / 16 != ser->baud_base)
2337 if (port->mapbase != (unsigned long)ser->iomem_base)
2339 if (port->iobase != ser->port)
2346 #ifdef CONFIG_CONSOLE_POLL
2347 static int atmel_poll_get_char(struct uart_port *port)
2349 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2352 return atmel_uart_read_char(port);
2355 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2357 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2360 atmel_uart_write_char(port, ch);
2364 static const struct uart_ops atmel_pops = {
2365 .tx_empty = atmel_tx_empty,
2366 .set_mctrl = atmel_set_mctrl,
2367 .get_mctrl = atmel_get_mctrl,
2368 .stop_tx = atmel_stop_tx,
2369 .start_tx = atmel_start_tx,
2370 .stop_rx = atmel_stop_rx,
2371 .enable_ms = atmel_enable_ms,
2372 .break_ctl = atmel_break_ctl,
2373 .startup = atmel_startup,
2374 .shutdown = atmel_shutdown,
2375 .flush_buffer = atmel_flush_buffer,
2376 .set_termios = atmel_set_termios,
2377 .set_ldisc = atmel_set_ldisc,
2379 .release_port = atmel_release_port,
2380 .request_port = atmel_request_port,
2381 .config_port = atmel_config_port,
2382 .verify_port = atmel_verify_port,
2383 .pm = atmel_serial_pm,
2384 #ifdef CONFIG_CONSOLE_POLL
2385 .poll_get_char = atmel_poll_get_char,
2386 .poll_put_char = atmel_poll_put_char,
2391 * Configure the port from the platform device resource info.
2393 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2394 struct platform_device *pdev)
2397 struct uart_port *port = &atmel_port->uart;
2399 atmel_init_property(atmel_port, pdev);
2400 atmel_set_ops(port);
2402 atmel_init_rs485(port, pdev);
2404 port->iotype = UPIO_MEM;
2405 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
2406 port->ops = &atmel_pops;
2408 port->dev = &pdev->dev;
2409 port->mapbase = pdev->resource[0].start;
2410 port->irq = pdev->resource[1].start;
2411 port->rs485_config = atmel_config_rs485;
2412 port->membase = NULL;
2414 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2416 /* for console, the clock could already be configured */
2417 if (!atmel_port->clk) {
2418 atmel_port->clk = clk_get(&pdev->dev, "usart");
2419 if (IS_ERR(atmel_port->clk)) {
2420 ret = PTR_ERR(atmel_port->clk);
2421 atmel_port->clk = NULL;
2424 ret = clk_prepare_enable(atmel_port->clk);
2426 clk_put(atmel_port->clk);
2427 atmel_port->clk = NULL;
2430 port->uartclk = clk_get_rate(atmel_port->clk);
2431 clk_disable_unprepare(atmel_port->clk);
2432 /* only enable clock when USART is in use */
2435 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2436 if (port->rs485.flags & SER_RS485_ENABLED)
2437 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2438 else if (atmel_use_pdc_tx(port)) {
2439 port->fifosize = PDC_BUFFER_SIZE;
2440 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2442 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2448 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2449 static void atmel_console_putchar(struct uart_port *port, int ch)
2451 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2453 atmel_uart_write_char(port, ch);
2457 * Interrupts are disabled on entering
2459 static void atmel_console_write(struct console *co, const char *s, u_int count)
2461 struct uart_port *port = &atmel_ports[co->index].uart;
2462 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2463 unsigned int status, imr;
2464 unsigned int pdc_tx;
2467 * First, save IMR and then disable interrupts
2469 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2470 atmel_uart_writel(port, ATMEL_US_IDR,
2471 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2473 /* Store PDC transmit status and disable it */
2474 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2475 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2477 /* Make sure that tx path is actually able to send characters */
2478 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2480 uart_console_write(port, s, count, atmel_console_putchar);
2483 * Finally, wait for transmitter to become empty
2487 status = atmel_uart_readl(port, ATMEL_US_CSR);
2488 } while (!(status & ATMEL_US_TXRDY));
2490 /* Restore PDC transmit status */
2492 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2494 /* set interrupts back the way they were */
2495 atmel_uart_writel(port, ATMEL_US_IER, imr);
2499 * If the port was already initialised (eg, by a boot loader),
2500 * try to determine the current setup.
2502 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2503 int *parity, int *bits)
2505 unsigned int mr, quot;
2508 * If the baud rate generator isn't running, the port wasn't
2509 * initialized by the boot loader.
2511 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2515 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2516 if (mr == ATMEL_US_CHRL_8)
2521 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2522 if (mr == ATMEL_US_PAR_EVEN)
2524 else if (mr == ATMEL_US_PAR_ODD)
2528 * The serial core only rounds down when matching this to a
2529 * supported baud rate. Make sure we don't end up slightly
2530 * lower than one of those, as it would make us fall through
2531 * to a much lower baud rate than we really want.
2533 *baud = port->uartclk / (16 * (quot - 1));
2536 static int __init atmel_console_setup(struct console *co, char *options)
2539 struct uart_port *port = &atmel_ports[co->index].uart;
2545 if (port->membase == NULL) {
2546 /* Port not initialized yet - delay setup */
2550 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2554 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2555 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2556 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2559 uart_parse_options(options, &baud, &parity, &bits, &flow);
2561 atmel_console_get_options(port, &baud, &parity, &bits);
2563 return uart_set_options(port, co, baud, parity, bits, flow);
2566 static struct uart_driver atmel_uart;
2568 static struct console atmel_console = {
2569 .name = ATMEL_DEVICENAME,
2570 .write = atmel_console_write,
2571 .device = uart_console_device,
2572 .setup = atmel_console_setup,
2573 .flags = CON_PRINTBUFFER,
2575 .data = &atmel_uart,
2578 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2580 static inline bool atmel_is_console_port(struct uart_port *port)
2582 return port->cons && port->cons->index == port->line;
2586 #define ATMEL_CONSOLE_DEVICE NULL
2588 static inline bool atmel_is_console_port(struct uart_port *port)
2594 static struct uart_driver atmel_uart = {
2595 .owner = THIS_MODULE,
2596 .driver_name = "atmel_serial",
2597 .dev_name = ATMEL_DEVICENAME,
2598 .major = SERIAL_ATMEL_MAJOR,
2599 .minor = MINOR_START,
2600 .nr = ATMEL_MAX_UART,
2601 .cons = ATMEL_CONSOLE_DEVICE,
2605 static bool atmel_serial_clk_will_stop(void)
2607 #ifdef CONFIG_ARCH_AT91
2608 return at91_suspend_entering_slow_clock();
2614 static int atmel_serial_suspend(struct platform_device *pdev,
2617 struct uart_port *port = platform_get_drvdata(pdev);
2618 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2620 if (atmel_is_console_port(port) && console_suspend_enabled) {
2621 /* Drain the TX shifter */
2622 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2627 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2628 /* Cache register values as we won't get a full shutdown/startup
2631 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2632 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2633 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2634 atmel_port->cache.rtor = atmel_uart_readl(port,
2636 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2637 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2638 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2641 /* we can not wake up if we're running on slow clock */
2642 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2643 if (atmel_serial_clk_will_stop()) {
2644 unsigned long flags;
2646 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2647 atmel_port->suspended = true;
2648 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2649 device_set_wakeup_enable(&pdev->dev, 0);
2652 uart_suspend_port(&atmel_uart, port);
2657 static int atmel_serial_resume(struct platform_device *pdev)
2659 struct uart_port *port = platform_get_drvdata(pdev);
2660 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2661 unsigned long flags;
2663 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2664 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2665 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2666 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2667 atmel_uart_writel(port, atmel_port->rtor,
2668 atmel_port->cache.rtor);
2669 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2671 if (atmel_port->fifo_size) {
2672 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2673 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2674 atmel_uart_writel(port, ATMEL_US_FMR,
2675 atmel_port->cache.fmr);
2676 atmel_uart_writel(port, ATMEL_US_FIER,
2677 atmel_port->cache.fimr);
2679 atmel_start_rx(port);
2682 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2683 if (atmel_port->pending) {
2684 atmel_handle_receive(port, atmel_port->pending);
2685 atmel_handle_status(port, atmel_port->pending,
2686 atmel_port->pending_status);
2687 atmel_handle_transmit(port, atmel_port->pending);
2688 atmel_port->pending = 0;
2690 atmel_port->suspended = false;
2691 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2693 uart_resume_port(&atmel_uart, port);
2694 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2699 #define atmel_serial_suspend NULL
2700 #define atmel_serial_resume NULL
2703 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2704 struct platform_device *pdev)
2706 atmel_port->fifo_size = 0;
2707 atmel_port->rts_low = 0;
2708 atmel_port->rts_high = 0;
2710 if (of_property_read_u32(pdev->dev.of_node,
2712 &atmel_port->fifo_size))
2715 if (!atmel_port->fifo_size)
2718 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2719 atmel_port->fifo_size = 0;
2720 dev_err(&pdev->dev, "Invalid FIFO size\n");
2725 * 0 <= rts_low <= rts_high <= fifo_size
2726 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2727 * to flush their internal TX FIFO, commonly up to 16 data, before
2728 * actually stopping to send new data. So we try to set the RTS High
2729 * Threshold to a reasonably high value respecting this 16 data
2730 * empirical rule when possible.
2732 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2733 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2734 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2735 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2737 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2738 atmel_port->fifo_size);
2739 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2740 atmel_port->rts_high);
2741 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2742 atmel_port->rts_low);
2745 static int atmel_serial_probe(struct platform_device *pdev)
2747 struct atmel_uart_port *atmel_port;
2748 struct device_node *np = pdev->dev.of_node;
2753 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2755 ret = of_alias_get_id(np, "serial");
2757 /* port id not found in platform data nor device-tree aliases:
2758 * auto-enumerate it */
2759 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2761 if (ret >= ATMEL_MAX_UART) {
2766 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2767 /* port already in use */
2772 atmel_port = &atmel_ports[ret];
2773 atmel_port->backup_imr = 0;
2774 atmel_port->uart.line = ret;
2775 atmel_serial_probe_fifos(atmel_port, pdev);
2777 atomic_set(&atmel_port->tasklet_shutdown, 0);
2778 spin_lock_init(&atmel_port->lock_suspended);
2780 ret = atmel_init_port(atmel_port, pdev);
2784 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2785 if (IS_ERR(atmel_port->gpios)) {
2786 ret = PTR_ERR(atmel_port->gpios);
2790 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2792 data = kmalloc(sizeof(struct atmel_uart_char)
2793 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
2795 goto err_alloc_ring;
2796 atmel_port->rx_ring.buf = data;
2799 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2801 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2805 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2806 if (atmel_is_console_port(&atmel_port->uart)
2807 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2809 * The serial core enabled the clock for us, so undo
2810 * the clk_prepare_enable() in atmel_console_setup()
2812 clk_disable_unprepare(atmel_port->clk);
2816 device_init_wakeup(&pdev->dev, 1);
2817 platform_set_drvdata(pdev, atmel_port);
2820 * The peripheral clock has been disabled by atmel_init_port():
2821 * enable it before accessing I/O registers
2823 clk_prepare_enable(atmel_port->clk);
2825 if (rs485_enabled) {
2826 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2827 ATMEL_US_USMODE_NORMAL);
2828 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2833 * Get port name of usart or uart
2835 atmel_get_ip_name(&atmel_port->uart);
2838 * The peripheral clock can now safely be disabled till the port
2841 clk_disable_unprepare(atmel_port->clk);
2846 kfree(atmel_port->rx_ring.buf);
2847 atmel_port->rx_ring.buf = NULL;
2849 if (!atmel_is_console_port(&atmel_port->uart)) {
2850 clk_put(atmel_port->clk);
2851 atmel_port->clk = NULL;
2854 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2860 * Even if the driver is not modular, it makes sense to be able to
2861 * unbind a device: there can be many bound devices, and there are
2862 * situations where dynamic binding and unbinding can be useful.
2864 * For example, a connected device can require a specific firmware update
2865 * protocol that needs bitbanging on IO lines, but use the regular serial
2866 * port in the normal case.
2868 static int atmel_serial_remove(struct platform_device *pdev)
2870 struct uart_port *port = platform_get_drvdata(pdev);
2871 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2874 tasklet_kill(&atmel_port->tasklet_rx);
2875 tasklet_kill(&atmel_port->tasklet_tx);
2877 device_init_wakeup(&pdev->dev, 0);
2879 ret = uart_remove_one_port(&atmel_uart, port);
2881 kfree(atmel_port->rx_ring.buf);
2883 /* "port" is allocated statically, so we shouldn't free it */
2885 clear_bit(port->line, atmel_ports_in_use);
2887 clk_put(atmel_port->clk);
2888 atmel_port->clk = NULL;
2893 static struct platform_driver atmel_serial_driver = {
2894 .probe = atmel_serial_probe,
2895 .remove = atmel_serial_remove,
2896 .suspend = atmel_serial_suspend,
2897 .resume = atmel_serial_resume,
2899 .name = "atmel_usart",
2900 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2904 static int __init atmel_serial_init(void)
2908 ret = uart_register_driver(&atmel_uart);
2912 ret = platform_driver_register(&atmel_serial_driver);
2914 uart_unregister_driver(&atmel_uart);
2918 device_initcall(atmel_serial_init);