1 /* arch/sparc64/kernel/traps.c
3 * Copyright (C) 1995,1997,2008,2009,2012 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1997,1999,2000 Jakub Jelinek (jakub@redhat.com)
8 * I like traps on v9, :))))
11 #include <linux/extable.h>
12 #include <linux/sched/mm.h>
13 #include <linux/sched/debug.h>
14 #include <linux/linkage.h>
15 #include <linux/kernel.h>
16 #include <linux/signal.h>
17 #include <linux/smp.h>
19 #include <linux/init.h>
20 #include <linux/kdebug.h>
21 #include <linux/ftrace.h>
22 #include <linux/reboot.h>
23 #include <linux/gfp.h>
24 #include <linux/context_tracking.h>
27 #include <asm/delay.h>
28 #include <asm/ptrace.h>
29 #include <asm/oplib.h>
31 #include <asm/pgtable.h>
32 #include <asm/unistd.h>
33 #include <linux/uaccess.h>
34 #include <asm/fpumacro.h>
37 #include <asm/estate.h>
38 #include <asm/chafsr.h>
39 #include <asm/sfafsr.h>
40 #include <asm/psrcompat.h>
41 #include <asm/processor.h>
42 #include <asm/timer.h>
45 #include <asm/memctrl.h>
46 #include <asm/cacheflush.h>
47 #include <asm/setup.h>
53 /* When an irrecoverable trap occurs at tl > 0, the trap entry
54 * code logs the trap state registers at every level in the trap
55 * stack. It is found at (pt_regs + sizeof(pt_regs)) and the layout
68 static void dump_tl1_traplog(struct tl1_traplog *p)
72 printk(KERN_EMERG "TRAPLOG: Error at trap level 0x%lx, "
73 "dumping track stack.\n", p->tl);
75 limit = (tlb_type == hypervisor) ? 2 : 4;
76 for (i = 0; i < limit; i++) {
78 "TRAPLOG: Trap level %d TSTATE[%016lx] TPC[%016lx] "
79 "TNPC[%016lx] TT[%lx]\n",
81 p->trapstack[i].tstate, p->trapstack[i].tpc,
82 p->trapstack[i].tnpc, p->trapstack[i].tt);
83 printk("TRAPLOG: TPC<%pS>\n", (void *) p->trapstack[i].tpc);
87 void bad_trap(struct pt_regs *regs, long lvl)
91 if (notify_die(DIE_TRAP, "bad trap", regs,
92 0, lvl, SIGTRAP) == NOTIFY_STOP)
96 sprintf(buffer, "Bad hw trap %lx at tl0\n", lvl);
97 die_if_kernel(buffer, regs);
101 if (regs->tstate & TSTATE_PRIV) {
102 sprintf(buffer, "Kernel bad sw trap %lx", lvl);
103 die_if_kernel(buffer, regs);
105 if (test_thread_flag(TIF_32BIT)) {
106 regs->tpc &= 0xffffffff;
107 regs->tnpc &= 0xffffffff;
109 force_sig_fault(SIGILL, ILL_ILLTRP,
110 (void __user *)regs->tpc, lvl, current);
113 void bad_trap_tl1(struct pt_regs *regs, long lvl)
117 if (notify_die(DIE_TRAP_TL1, "bad trap tl1", regs,
118 0, lvl, SIGTRAP) == NOTIFY_STOP)
121 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
123 sprintf (buffer, "Bad trap %lx at tl>0", lvl);
124 die_if_kernel (buffer, regs);
127 #ifdef CONFIG_DEBUG_BUGVERBOSE
128 void do_BUG(const char *file, int line)
131 printk("kernel BUG at %s:%d!\n", file, line);
133 EXPORT_SYMBOL(do_BUG);
136 static DEFINE_SPINLOCK(dimm_handler_lock);
137 static dimm_printer_t dimm_handler;
139 static int sprintf_dimm(int synd_code, unsigned long paddr, char *buf, int buflen)
144 spin_lock_irqsave(&dimm_handler_lock, flags);
146 ret = dimm_handler(synd_code, paddr, buf, buflen);
147 } else if (tlb_type == spitfire) {
148 if (prom_getunumber(synd_code, paddr, buf, buflen) == -1)
154 spin_unlock_irqrestore(&dimm_handler_lock, flags);
159 int register_dimm_printer(dimm_printer_t func)
164 spin_lock_irqsave(&dimm_handler_lock, flags);
169 spin_unlock_irqrestore(&dimm_handler_lock, flags);
173 EXPORT_SYMBOL_GPL(register_dimm_printer);
175 void unregister_dimm_printer(dimm_printer_t func)
179 spin_lock_irqsave(&dimm_handler_lock, flags);
180 if (dimm_handler == func)
182 spin_unlock_irqrestore(&dimm_handler_lock, flags);
184 EXPORT_SYMBOL_GPL(unregister_dimm_printer);
186 void spitfire_insn_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
188 enum ctx_state prev_state = exception_enter();
190 if (notify_die(DIE_TRAP, "instruction access exception", regs,
191 0, 0x8, SIGTRAP) == NOTIFY_STOP)
194 if (regs->tstate & TSTATE_PRIV) {
195 printk("spitfire_insn_access_exception: SFSR[%016lx] "
196 "SFAR[%016lx], going.\n", sfsr, sfar);
197 die_if_kernel("Iax", regs);
199 if (test_thread_flag(TIF_32BIT)) {
200 regs->tpc &= 0xffffffff;
201 regs->tnpc &= 0xffffffff;
203 force_sig_fault(SIGSEGV, SEGV_MAPERR,
204 (void __user *)regs->tpc, 0, current);
206 exception_exit(prev_state);
209 void spitfire_insn_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
211 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
212 0, 0x8, SIGTRAP) == NOTIFY_STOP)
215 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
216 spitfire_insn_access_exception(regs, sfsr, sfar);
219 void sun4v_insn_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
221 unsigned short type = (type_ctx >> 16);
222 unsigned short ctx = (type_ctx & 0xffff);
224 if (notify_die(DIE_TRAP, "instruction access exception", regs,
225 0, 0x8, SIGTRAP) == NOTIFY_STOP)
228 if (regs->tstate & TSTATE_PRIV) {
229 printk("sun4v_insn_access_exception: ADDR[%016lx] "
230 "CTX[%04x] TYPE[%04x], going.\n",
232 die_if_kernel("Iax", regs);
235 if (test_thread_flag(TIF_32BIT)) {
236 regs->tpc &= 0xffffffff;
237 regs->tnpc &= 0xffffffff;
239 force_sig_fault(SIGSEGV, SEGV_MAPERR, (void __user *) addr, 0, current);
242 void sun4v_insn_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
244 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
245 0, 0x8, SIGTRAP) == NOTIFY_STOP)
248 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
249 sun4v_insn_access_exception(regs, addr, type_ctx);
252 bool is_no_fault_exception(struct pt_regs *regs)
257 if (get_user(insn, (u32 __user *)regs->tpc) == -EFAULT)
261 * Must do a little instruction decoding here in order to
262 * decide on a course of action. The bits of interest are:
263 * insn[31:30] = op, where 3 indicates the load/store group
264 * insn[24:19] = op3, which identifies individual opcodes
265 * insn[13] indicates an immediate offset
266 * op3[4]=1 identifies alternate space instructions
267 * op3[5:4]=3 identifies floating point instructions
268 * op3[2]=1 identifies stores
269 * See "Opcode Maps" in the appendix of any Sparc V9
270 * architecture spec for full details.
272 if ((insn & 0xc0800000) == 0xc0800000) { /* op=3, op3[4]=1 */
273 if (insn & 0x2000) /* immediate offset */
274 asi = (regs->tstate >> 24); /* saved %asi */
276 asi = (insn >> 5); /* immediate asi */
277 if ((asi & 0xf6) == ASI_PNF) {
278 if (insn & 0x200000) /* op3[2], stores */
280 if (insn & 0x1000000) /* op3[5:4]=3 (fp) */
281 handle_ldf_stq(insn, regs);
283 handle_ld_nf(insn, regs);
290 void spitfire_data_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
292 enum ctx_state prev_state = exception_enter();
294 if (notify_die(DIE_TRAP, "data access exception", regs,
295 0, 0x30, SIGTRAP) == NOTIFY_STOP)
298 if (regs->tstate & TSTATE_PRIV) {
299 /* Test if this comes from uaccess places. */
300 const struct exception_table_entry *entry;
302 entry = search_exception_tables(regs->tpc);
304 /* Ouch, somebody is trying VM hole tricks on us... */
305 #ifdef DEBUG_EXCEPTIONS
306 printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
307 printk("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
308 regs->tpc, entry->fixup);
310 regs->tpc = entry->fixup;
311 regs->tnpc = regs->tpc + 4;
315 printk("spitfire_data_access_exception: SFSR[%016lx] "
316 "SFAR[%016lx], going.\n", sfsr, sfar);
317 die_if_kernel("Dax", regs);
320 if (is_no_fault_exception(regs))
323 force_sig_fault(SIGSEGV, SEGV_MAPERR, (void __user *)sfar, 0, current);
325 exception_exit(prev_state);
328 void spitfire_data_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
330 if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
331 0, 0x30, SIGTRAP) == NOTIFY_STOP)
334 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
335 spitfire_data_access_exception(regs, sfsr, sfar);
338 void sun4v_data_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
340 unsigned short type = (type_ctx >> 16);
341 unsigned short ctx = (type_ctx & 0xffff);
343 if (notify_die(DIE_TRAP, "data access exception", regs,
344 0, 0x8, SIGTRAP) == NOTIFY_STOP)
347 if (regs->tstate & TSTATE_PRIV) {
348 /* Test if this comes from uaccess places. */
349 const struct exception_table_entry *entry;
351 entry = search_exception_tables(regs->tpc);
353 /* Ouch, somebody is trying VM hole tricks on us... */
354 #ifdef DEBUG_EXCEPTIONS
355 printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
356 printk("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
357 regs->tpc, entry->fixup);
359 regs->tpc = entry->fixup;
360 regs->tnpc = regs->tpc + 4;
363 printk("sun4v_data_access_exception: ADDR[%016lx] "
364 "CTX[%04x] TYPE[%04x], going.\n",
366 die_if_kernel("Dax", regs);
369 if (test_thread_flag(TIF_32BIT)) {
370 regs->tpc &= 0xffffffff;
371 regs->tnpc &= 0xffffffff;
373 if (is_no_fault_exception(regs))
376 /* MCD (Memory Corruption Detection) disabled trap (TT=0x19) in HV
377 * is vectored thorugh data access exception trap with fault type
378 * set to HV_FAULT_TYPE_MCD_DIS. Check for MCD disabled trap.
379 * Accessing an address with invalid ASI for the address, for
380 * example setting an ADI tag on an address with ASI_MCD_PRIMARY
381 * when TTE.mcd is not set for the VA, is also vectored into
382 * kerbel by HV as data access exception with fault type set to
383 * HV_FAULT_TYPE_INV_ASI.
386 case HV_FAULT_TYPE_INV_ASI:
387 force_sig_fault(SIGILL, ILL_ILLADR, (void __user *)addr, 0,
390 case HV_FAULT_TYPE_MCD_DIS:
391 force_sig_fault(SIGSEGV, SEGV_ACCADI, (void __user *)addr, 0,
395 force_sig_fault(SIGSEGV, SEGV_MAPERR, (void __user *)addr, 0,
401 void sun4v_data_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
403 if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
404 0, 0x8, SIGTRAP) == NOTIFY_STOP)
407 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
408 sun4v_data_access_exception(regs, addr, type_ctx);
412 #include "pci_impl.h"
415 /* When access exceptions happen, we must do this. */
416 static void spitfire_clean_and_reenable_l1_caches(void)
420 if (tlb_type != spitfire)
424 for (va = 0; va < (PAGE_SIZE << 1); va += 32) {
425 spitfire_put_icache_tag(va, 0x0);
426 spitfire_put_dcache_tag(va, 0x0);
429 /* Re-enable in LSU. */
430 __asm__ __volatile__("flush %%g6\n\t"
432 "stxa %0, [%%g0] %1\n\t"
435 : "r" (LSU_CONTROL_IC | LSU_CONTROL_DC |
436 LSU_CONTROL_IM | LSU_CONTROL_DM),
437 "i" (ASI_LSU_CONTROL)
441 static void spitfire_enable_estate_errors(void)
443 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
446 : "r" (ESTATE_ERR_ALL),
447 "i" (ASI_ESTATE_ERROR_EN));
450 static char ecc_syndrome_table[] = {
451 0x4c, 0x40, 0x41, 0x48, 0x42, 0x48, 0x48, 0x49,
452 0x43, 0x48, 0x48, 0x49, 0x48, 0x49, 0x49, 0x4a,
453 0x44, 0x48, 0x48, 0x20, 0x48, 0x39, 0x4b, 0x48,
454 0x48, 0x25, 0x31, 0x48, 0x28, 0x48, 0x48, 0x2c,
455 0x45, 0x48, 0x48, 0x21, 0x48, 0x3d, 0x04, 0x48,
456 0x48, 0x4b, 0x35, 0x48, 0x2d, 0x48, 0x48, 0x29,
457 0x48, 0x00, 0x01, 0x48, 0x0a, 0x48, 0x48, 0x4b,
458 0x0f, 0x48, 0x48, 0x4b, 0x48, 0x49, 0x49, 0x48,
459 0x46, 0x48, 0x48, 0x2a, 0x48, 0x3b, 0x27, 0x48,
460 0x48, 0x4b, 0x33, 0x48, 0x22, 0x48, 0x48, 0x2e,
461 0x48, 0x19, 0x1d, 0x48, 0x1b, 0x4a, 0x48, 0x4b,
462 0x1f, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
463 0x48, 0x4b, 0x24, 0x48, 0x07, 0x48, 0x48, 0x36,
464 0x4b, 0x48, 0x48, 0x3e, 0x48, 0x30, 0x38, 0x48,
465 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x16, 0x48,
466 0x48, 0x12, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
467 0x47, 0x48, 0x48, 0x2f, 0x48, 0x3f, 0x4b, 0x48,
468 0x48, 0x06, 0x37, 0x48, 0x23, 0x48, 0x48, 0x2b,
469 0x48, 0x05, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x32,
470 0x26, 0x48, 0x48, 0x3a, 0x48, 0x34, 0x3c, 0x48,
471 0x48, 0x11, 0x15, 0x48, 0x13, 0x4a, 0x48, 0x4b,
472 0x17, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
473 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x1e, 0x48,
474 0x48, 0x1a, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
475 0x48, 0x08, 0x0d, 0x48, 0x02, 0x48, 0x48, 0x49,
476 0x03, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x4b, 0x48,
477 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x10, 0x48,
478 0x48, 0x14, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
479 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x18, 0x48,
480 0x48, 0x1c, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
481 0x4a, 0x0c, 0x09, 0x48, 0x0e, 0x48, 0x48, 0x4b,
482 0x0b, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x4b, 0x4a
485 static char *syndrome_unknown = "<Unknown>";
487 static void spitfire_log_udb_syndrome(unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long bit)
489 unsigned short scode;
490 char memmod_str[64], *p;
493 scode = ecc_syndrome_table[udbl & 0xff];
494 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0)
495 p = syndrome_unknown;
498 printk(KERN_WARNING "CPU[%d]: UDBL Syndrome[%x] "
499 "Memory Module \"%s\"\n",
500 smp_processor_id(), scode, p);
504 scode = ecc_syndrome_table[udbh & 0xff];
505 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0)
506 p = syndrome_unknown;
509 printk(KERN_WARNING "CPU[%d]: UDBH Syndrome[%x] "
510 "Memory Module \"%s\"\n",
511 smp_processor_id(), scode, p);
516 static void spitfire_cee_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, int tl1, struct pt_regs *regs)
519 printk(KERN_WARNING "CPU[%d]: Correctable ECC Error "
520 "AFSR[%lx] AFAR[%016lx] UDBL[%lx] UDBH[%lx] TL>1[%d]\n",
521 smp_processor_id(), afsr, afar, udbl, udbh, tl1);
523 spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_CE);
525 /* We always log it, even if someone is listening for this
528 notify_die(DIE_TRAP, "Correctable ECC Error", regs,
529 0, TRAP_TYPE_CEE, SIGTRAP);
531 /* The Correctable ECC Error trap does not disable I/D caches. So
532 * we only have to restore the ESTATE Error Enable register.
534 spitfire_enable_estate_errors();
537 static void spitfire_ue_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long tt, int tl1, struct pt_regs *regs)
539 printk(KERN_WARNING "CPU[%d]: Uncorrectable Error AFSR[%lx] "
540 "AFAR[%lx] UDBL[%lx] UDBH[%ld] TT[%lx] TL>1[%d]\n",
541 smp_processor_id(), afsr, afar, udbl, udbh, tt, tl1);
543 /* XXX add more human friendly logging of the error status
544 * XXX as is implemented for cheetah
547 spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_UE);
549 /* We always log it, even if someone is listening for this
552 notify_die(DIE_TRAP, "Uncorrectable Error", regs,
555 if (regs->tstate & TSTATE_PRIV) {
557 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
558 die_if_kernel("UE", regs);
561 /* XXX need more intelligent processing here, such as is implemented
562 * XXX for cheetah errors, in fact if the E-cache still holds the
563 * XXX line with bad parity this will loop
566 spitfire_clean_and_reenable_l1_caches();
567 spitfire_enable_estate_errors();
569 if (test_thread_flag(TIF_32BIT)) {
570 regs->tpc &= 0xffffffff;
571 regs->tnpc &= 0xffffffff;
573 force_sig_fault(SIGBUS, BUS_OBJERR, (void *)0, 0, current);
576 void spitfire_access_error(struct pt_regs *regs, unsigned long status_encoded, unsigned long afar)
578 unsigned long afsr, tt, udbh, udbl;
581 afsr = (status_encoded & SFSTAT_AFSR_MASK) >> SFSTAT_AFSR_SHIFT;
582 tt = (status_encoded & SFSTAT_TRAP_TYPE) >> SFSTAT_TRAP_TYPE_SHIFT;
583 tl1 = (status_encoded & SFSTAT_TL_GT_ONE) ? 1 : 0;
584 udbl = (status_encoded & SFSTAT_UDBL_MASK) >> SFSTAT_UDBL_SHIFT;
585 udbh = (status_encoded & SFSTAT_UDBH_MASK) >> SFSTAT_UDBH_SHIFT;
588 if (tt == TRAP_TYPE_DAE &&
589 pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
590 spitfire_clean_and_reenable_l1_caches();
591 spitfire_enable_estate_errors();
593 pci_poke_faulted = 1;
594 regs->tnpc = regs->tpc + 4;
599 if (afsr & SFAFSR_UE)
600 spitfire_ue_log(afsr, afar, udbh, udbl, tt, tl1, regs);
602 if (tt == TRAP_TYPE_CEE) {
603 /* Handle the case where we took a CEE trap, but ACK'd
604 * only the UE state in the UDB error registers.
606 if (afsr & SFAFSR_UE) {
607 if (udbh & UDBE_CE) {
608 __asm__ __volatile__(
609 "stxa %0, [%1] %2\n\t"
612 : "r" (udbh & UDBE_CE),
613 "r" (0x0), "i" (ASI_UDB_ERROR_W));
615 if (udbl & UDBE_CE) {
616 __asm__ __volatile__(
617 "stxa %0, [%1] %2\n\t"
620 : "r" (udbl & UDBE_CE),
621 "r" (0x18), "i" (ASI_UDB_ERROR_W));
625 spitfire_cee_log(afsr, afar, udbh, udbl, tl1, regs);
629 int cheetah_pcache_forced_on;
631 void cheetah_enable_pcache(void)
635 printk("CHEETAH: Enabling P-Cache on cpu %d.\n",
638 __asm__ __volatile__("ldxa [%%g0] %1, %0"
640 : "i" (ASI_DCU_CONTROL_REG));
641 dcr |= (DCU_PE | DCU_HPE | DCU_SPE | DCU_SL);
642 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
645 : "r" (dcr), "i" (ASI_DCU_CONTROL_REG));
648 /* Cheetah error trap handling. */
649 static unsigned long ecache_flush_physbase;
650 static unsigned long ecache_flush_linesize;
651 static unsigned long ecache_flush_size;
653 /* This table is ordered in priority of errors and matches the
654 * AFAR overwrite policy as well.
657 struct afsr_error_table {
662 static const char CHAFSR_PERR_msg[] =
663 "System interface protocol error";
664 static const char CHAFSR_IERR_msg[] =
665 "Internal processor error";
666 static const char CHAFSR_ISAP_msg[] =
667 "System request parity error on incoming address";
668 static const char CHAFSR_UCU_msg[] =
669 "Uncorrectable E-cache ECC error for ifetch/data";
670 static const char CHAFSR_UCC_msg[] =
671 "SW Correctable E-cache ECC error for ifetch/data";
672 static const char CHAFSR_UE_msg[] =
673 "Uncorrectable system bus data ECC error for read";
674 static const char CHAFSR_EDU_msg[] =
675 "Uncorrectable E-cache ECC error for stmerge/blkld";
676 static const char CHAFSR_EMU_msg[] =
677 "Uncorrectable system bus MTAG error";
678 static const char CHAFSR_WDU_msg[] =
679 "Uncorrectable E-cache ECC error for writeback";
680 static const char CHAFSR_CPU_msg[] =
681 "Uncorrectable ECC error for copyout";
682 static const char CHAFSR_CE_msg[] =
683 "HW corrected system bus data ECC error for read";
684 static const char CHAFSR_EDC_msg[] =
685 "HW corrected E-cache ECC error for stmerge/blkld";
686 static const char CHAFSR_EMC_msg[] =
687 "HW corrected system bus MTAG ECC error";
688 static const char CHAFSR_WDC_msg[] =
689 "HW corrected E-cache ECC error for writeback";
690 static const char CHAFSR_CPC_msg[] =
691 "HW corrected ECC error for copyout";
692 static const char CHAFSR_TO_msg[] =
693 "Unmapped error from system bus";
694 static const char CHAFSR_BERR_msg[] =
695 "Bus error response from system bus";
696 static const char CHAFSR_IVC_msg[] =
697 "HW corrected system bus data ECC error for ivec read";
698 static const char CHAFSR_IVU_msg[] =
699 "Uncorrectable system bus data ECC error for ivec read";
700 static struct afsr_error_table __cheetah_error_table[] = {
701 { CHAFSR_PERR, CHAFSR_PERR_msg },
702 { CHAFSR_IERR, CHAFSR_IERR_msg },
703 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
704 { CHAFSR_UCU, CHAFSR_UCU_msg },
705 { CHAFSR_UCC, CHAFSR_UCC_msg },
706 { CHAFSR_UE, CHAFSR_UE_msg },
707 { CHAFSR_EDU, CHAFSR_EDU_msg },
708 { CHAFSR_EMU, CHAFSR_EMU_msg },
709 { CHAFSR_WDU, CHAFSR_WDU_msg },
710 { CHAFSR_CPU, CHAFSR_CPU_msg },
711 { CHAFSR_CE, CHAFSR_CE_msg },
712 { CHAFSR_EDC, CHAFSR_EDC_msg },
713 { CHAFSR_EMC, CHAFSR_EMC_msg },
714 { CHAFSR_WDC, CHAFSR_WDC_msg },
715 { CHAFSR_CPC, CHAFSR_CPC_msg },
716 { CHAFSR_TO, CHAFSR_TO_msg },
717 { CHAFSR_BERR, CHAFSR_BERR_msg },
718 /* These two do not update the AFAR. */
719 { CHAFSR_IVC, CHAFSR_IVC_msg },
720 { CHAFSR_IVU, CHAFSR_IVU_msg },
723 static const char CHPAFSR_DTO_msg[] =
724 "System bus unmapped error for prefetch/storequeue-read";
725 static const char CHPAFSR_DBERR_msg[] =
726 "System bus error for prefetch/storequeue-read";
727 static const char CHPAFSR_THCE_msg[] =
728 "Hardware corrected E-cache Tag ECC error";
729 static const char CHPAFSR_TSCE_msg[] =
730 "SW handled correctable E-cache Tag ECC error";
731 static const char CHPAFSR_TUE_msg[] =
732 "Uncorrectable E-cache Tag ECC error";
733 static const char CHPAFSR_DUE_msg[] =
734 "System bus uncorrectable data ECC error due to prefetch/store-fill";
735 static struct afsr_error_table __cheetah_plus_error_table[] = {
736 { CHAFSR_PERR, CHAFSR_PERR_msg },
737 { CHAFSR_IERR, CHAFSR_IERR_msg },
738 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
739 { CHAFSR_UCU, CHAFSR_UCU_msg },
740 { CHAFSR_UCC, CHAFSR_UCC_msg },
741 { CHAFSR_UE, CHAFSR_UE_msg },
742 { CHAFSR_EDU, CHAFSR_EDU_msg },
743 { CHAFSR_EMU, CHAFSR_EMU_msg },
744 { CHAFSR_WDU, CHAFSR_WDU_msg },
745 { CHAFSR_CPU, CHAFSR_CPU_msg },
746 { CHAFSR_CE, CHAFSR_CE_msg },
747 { CHAFSR_EDC, CHAFSR_EDC_msg },
748 { CHAFSR_EMC, CHAFSR_EMC_msg },
749 { CHAFSR_WDC, CHAFSR_WDC_msg },
750 { CHAFSR_CPC, CHAFSR_CPC_msg },
751 { CHAFSR_TO, CHAFSR_TO_msg },
752 { CHAFSR_BERR, CHAFSR_BERR_msg },
753 { CHPAFSR_DTO, CHPAFSR_DTO_msg },
754 { CHPAFSR_DBERR, CHPAFSR_DBERR_msg },
755 { CHPAFSR_THCE, CHPAFSR_THCE_msg },
756 { CHPAFSR_TSCE, CHPAFSR_TSCE_msg },
757 { CHPAFSR_TUE, CHPAFSR_TUE_msg },
758 { CHPAFSR_DUE, CHPAFSR_DUE_msg },
759 /* These two do not update the AFAR. */
760 { CHAFSR_IVC, CHAFSR_IVC_msg },
761 { CHAFSR_IVU, CHAFSR_IVU_msg },
764 static const char JPAFSR_JETO_msg[] =
765 "System interface protocol error, hw timeout caused";
766 static const char JPAFSR_SCE_msg[] =
767 "Parity error on system snoop results";
768 static const char JPAFSR_JEIC_msg[] =
769 "System interface protocol error, illegal command detected";
770 static const char JPAFSR_JEIT_msg[] =
771 "System interface protocol error, illegal ADTYPE detected";
772 static const char JPAFSR_OM_msg[] =
773 "Out of range memory error has occurred";
774 static const char JPAFSR_ETP_msg[] =
775 "Parity error on L2 cache tag SRAM";
776 static const char JPAFSR_UMS_msg[] =
777 "Error due to unsupported store";
778 static const char JPAFSR_RUE_msg[] =
779 "Uncorrectable ECC error from remote cache/memory";
780 static const char JPAFSR_RCE_msg[] =
781 "Correctable ECC error from remote cache/memory";
782 static const char JPAFSR_BP_msg[] =
783 "JBUS parity error on returned read data";
784 static const char JPAFSR_WBP_msg[] =
785 "JBUS parity error on data for writeback or block store";
786 static const char JPAFSR_FRC_msg[] =
787 "Foreign read to DRAM incurring correctable ECC error";
788 static const char JPAFSR_FRU_msg[] =
789 "Foreign read to DRAM incurring uncorrectable ECC error";
790 static struct afsr_error_table __jalapeno_error_table[] = {
791 { JPAFSR_JETO, JPAFSR_JETO_msg },
792 { JPAFSR_SCE, JPAFSR_SCE_msg },
793 { JPAFSR_JEIC, JPAFSR_JEIC_msg },
794 { JPAFSR_JEIT, JPAFSR_JEIT_msg },
795 { CHAFSR_PERR, CHAFSR_PERR_msg },
796 { CHAFSR_IERR, CHAFSR_IERR_msg },
797 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
798 { CHAFSR_UCU, CHAFSR_UCU_msg },
799 { CHAFSR_UCC, CHAFSR_UCC_msg },
800 { CHAFSR_UE, CHAFSR_UE_msg },
801 { CHAFSR_EDU, CHAFSR_EDU_msg },
802 { JPAFSR_OM, JPAFSR_OM_msg },
803 { CHAFSR_WDU, CHAFSR_WDU_msg },
804 { CHAFSR_CPU, CHAFSR_CPU_msg },
805 { CHAFSR_CE, CHAFSR_CE_msg },
806 { CHAFSR_EDC, CHAFSR_EDC_msg },
807 { JPAFSR_ETP, JPAFSR_ETP_msg },
808 { CHAFSR_WDC, CHAFSR_WDC_msg },
809 { CHAFSR_CPC, CHAFSR_CPC_msg },
810 { CHAFSR_TO, CHAFSR_TO_msg },
811 { CHAFSR_BERR, CHAFSR_BERR_msg },
812 { JPAFSR_UMS, JPAFSR_UMS_msg },
813 { JPAFSR_RUE, JPAFSR_RUE_msg },
814 { JPAFSR_RCE, JPAFSR_RCE_msg },
815 { JPAFSR_BP, JPAFSR_BP_msg },
816 { JPAFSR_WBP, JPAFSR_WBP_msg },
817 { JPAFSR_FRC, JPAFSR_FRC_msg },
818 { JPAFSR_FRU, JPAFSR_FRU_msg },
819 /* These two do not update the AFAR. */
820 { CHAFSR_IVU, CHAFSR_IVU_msg },
823 static struct afsr_error_table *cheetah_error_table;
824 static unsigned long cheetah_afsr_errors;
826 struct cheetah_err_info *cheetah_error_log;
828 static inline struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr)
830 struct cheetah_err_info *p;
831 int cpu = smp_processor_id();
833 if (!cheetah_error_log)
836 p = cheetah_error_log + (cpu * 2);
837 if ((afsr & CHAFSR_TL1) != 0UL)
843 extern unsigned int tl0_icpe[], tl1_icpe[];
844 extern unsigned int tl0_dcpe[], tl1_dcpe[];
845 extern unsigned int tl0_fecc[], tl1_fecc[];
846 extern unsigned int tl0_cee[], tl1_cee[];
847 extern unsigned int tl0_iae[], tl1_iae[];
848 extern unsigned int tl0_dae[], tl1_dae[];
849 extern unsigned int cheetah_plus_icpe_trap_vector[], cheetah_plus_icpe_trap_vector_tl1[];
850 extern unsigned int cheetah_plus_dcpe_trap_vector[], cheetah_plus_dcpe_trap_vector_tl1[];
851 extern unsigned int cheetah_fecc_trap_vector[], cheetah_fecc_trap_vector_tl1[];
852 extern unsigned int cheetah_cee_trap_vector[], cheetah_cee_trap_vector_tl1[];
853 extern unsigned int cheetah_deferred_trap_vector[], cheetah_deferred_trap_vector_tl1[];
855 void __init cheetah_ecache_flush_init(void)
857 unsigned long largest_size, smallest_linesize, order, ver;
860 /* Scan all cpu device tree nodes, note two values:
861 * 1) largest E-cache size
862 * 2) smallest E-cache line size
865 smallest_linesize = ~0UL;
867 for (i = 0; i < NR_CPUS; i++) {
870 val = cpu_data(i).ecache_size;
874 if (val > largest_size)
877 val = cpu_data(i).ecache_line_size;
878 if (val < smallest_linesize)
879 smallest_linesize = val;
883 if (largest_size == 0UL || smallest_linesize == ~0UL) {
884 prom_printf("cheetah_ecache_flush_init: Cannot probe cpu E-cache "
889 ecache_flush_size = (2 * largest_size);
890 ecache_flush_linesize = smallest_linesize;
892 ecache_flush_physbase = find_ecache_flush_span(ecache_flush_size);
894 if (ecache_flush_physbase == ~0UL) {
895 prom_printf("cheetah_ecache_flush_init: Cannot find %ld byte "
896 "contiguous physical memory.\n",
901 /* Now allocate error trap reporting scoreboard. */
902 sz = NR_CPUS * (2 * sizeof(struct cheetah_err_info));
903 for (order = 0; order < MAX_ORDER; order++) {
904 if ((PAGE_SIZE << order) >= sz)
907 cheetah_error_log = (struct cheetah_err_info *)
908 __get_free_pages(GFP_KERNEL, order);
909 if (!cheetah_error_log) {
910 prom_printf("cheetah_ecache_flush_init: Failed to allocate "
911 "error logging scoreboard (%d bytes).\n", sz);
914 memset(cheetah_error_log, 0, PAGE_SIZE << order);
916 /* Mark all AFSRs as invalid so that the trap handler will
917 * log new new information there.
919 for (i = 0; i < 2 * NR_CPUS; i++)
920 cheetah_error_log[i].afsr = CHAFSR_INVALID;
922 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
923 if ((ver >> 32) == __JALAPENO_ID ||
924 (ver >> 32) == __SERRANO_ID) {
925 cheetah_error_table = &__jalapeno_error_table[0];
926 cheetah_afsr_errors = JPAFSR_ERRORS;
927 } else if ((ver >> 32) == 0x003e0015) {
928 cheetah_error_table = &__cheetah_plus_error_table[0];
929 cheetah_afsr_errors = CHPAFSR_ERRORS;
931 cheetah_error_table = &__cheetah_error_table[0];
932 cheetah_afsr_errors = CHAFSR_ERRORS;
935 /* Now patch trap tables. */
936 memcpy(tl0_fecc, cheetah_fecc_trap_vector, (8 * 4));
937 memcpy(tl1_fecc, cheetah_fecc_trap_vector_tl1, (8 * 4));
938 memcpy(tl0_cee, cheetah_cee_trap_vector, (8 * 4));
939 memcpy(tl1_cee, cheetah_cee_trap_vector_tl1, (8 * 4));
940 memcpy(tl0_iae, cheetah_deferred_trap_vector, (8 * 4));
941 memcpy(tl1_iae, cheetah_deferred_trap_vector_tl1, (8 * 4));
942 memcpy(tl0_dae, cheetah_deferred_trap_vector, (8 * 4));
943 memcpy(tl1_dae, cheetah_deferred_trap_vector_tl1, (8 * 4));
944 if (tlb_type == cheetah_plus) {
945 memcpy(tl0_dcpe, cheetah_plus_dcpe_trap_vector, (8 * 4));
946 memcpy(tl1_dcpe, cheetah_plus_dcpe_trap_vector_tl1, (8 * 4));
947 memcpy(tl0_icpe, cheetah_plus_icpe_trap_vector, (8 * 4));
948 memcpy(tl1_icpe, cheetah_plus_icpe_trap_vector_tl1, (8 * 4));
953 static void cheetah_flush_ecache(void)
955 unsigned long flush_base = ecache_flush_physbase;
956 unsigned long flush_linesize = ecache_flush_linesize;
957 unsigned long flush_size = ecache_flush_size;
959 __asm__ __volatile__("1: subcc %0, %4, %0\n\t"
960 " bne,pt %%xcc, 1b\n\t"
961 " ldxa [%2 + %0] %3, %%g0\n\t"
963 : "0" (flush_size), "r" (flush_base),
964 "i" (ASI_PHYS_USE_EC), "r" (flush_linesize));
967 static void cheetah_flush_ecache_line(unsigned long physaddr)
971 physaddr &= ~(8UL - 1UL);
972 physaddr = (ecache_flush_physbase +
973 (physaddr & ((ecache_flush_size>>1UL) - 1UL)));
974 alias = physaddr + (ecache_flush_size >> 1UL);
975 __asm__ __volatile__("ldxa [%0] %2, %%g0\n\t"
976 "ldxa [%1] %2, %%g0\n\t"
979 : "r" (physaddr), "r" (alias),
980 "i" (ASI_PHYS_USE_EC));
983 /* Unfortunately, the diagnostic access to the I-cache tags we need to
984 * use to clear the thing interferes with I-cache coherency transactions.
986 * So we must only flush the I-cache when it is disabled.
988 static void __cheetah_flush_icache(void)
990 unsigned int icache_size, icache_line_size;
993 icache_size = local_cpu_data().icache_size;
994 icache_line_size = local_cpu_data().icache_line_size;
996 /* Clear the valid bits in all the tags. */
997 for (addr = 0; addr < icache_size; addr += icache_line_size) {
998 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1001 : "r" (addr | (2 << 3)),
1006 static void cheetah_flush_icache(void)
1008 unsigned long dcu_save;
1010 /* Save current DCU, disable I-cache. */
1011 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1012 "or %0, %2, %%g1\n\t"
1013 "stxa %%g1, [%%g0] %1\n\t"
1016 : "i" (ASI_DCU_CONTROL_REG), "i" (DCU_IC)
1019 __cheetah_flush_icache();
1021 /* Restore DCU register */
1022 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1025 : "r" (dcu_save), "i" (ASI_DCU_CONTROL_REG));
1028 static void cheetah_flush_dcache(void)
1030 unsigned int dcache_size, dcache_line_size;
1033 dcache_size = local_cpu_data().dcache_size;
1034 dcache_line_size = local_cpu_data().dcache_line_size;
1036 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
1037 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1040 : "r" (addr), "i" (ASI_DCACHE_TAG));
1044 /* In order to make the even parity correct we must do two things.
1045 * First, we clear DC_data_parity and set DC_utag to an appropriate value.
1046 * Next, we clear out all 32-bytes of data for that line. Data of
1047 * all-zero + tag parity value of zero == correct parity.
1049 static void cheetah_plus_zap_dcache_parity(void)
1051 unsigned int dcache_size, dcache_line_size;
1054 dcache_size = local_cpu_data().dcache_size;
1055 dcache_line_size = local_cpu_data().dcache_line_size;
1057 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
1058 unsigned long tag = (addr >> 14);
1061 __asm__ __volatile__("membar #Sync\n\t"
1062 "stxa %0, [%1] %2\n\t"
1065 : "r" (tag), "r" (addr),
1066 "i" (ASI_DCACHE_UTAG));
1067 for (line = addr; line < addr + dcache_line_size; line += 8)
1068 __asm__ __volatile__("membar #Sync\n\t"
1069 "stxa %%g0, [%0] %1\n\t"
1073 "i" (ASI_DCACHE_DATA));
1077 /* Conversion tables used to frob Cheetah AFSR syndrome values into
1078 * something palatable to the memory controller driver get_unumber
1102 static unsigned char cheetah_ecc_syntab[] = {
1103 /*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
1104 /*01*/C4, M, M, 50, M2, 38, 25, M2, M2, 33, 24, M2, 11, M, M2, 16,
1105 /*02*/C5, M, M, 46, M2, 37, 19, M2, M, 31, 32, M, 7, M2, M2, 10,
1106 /*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M,
1107 /*04*/C6, M, M, 43, M, 36, 18, M, M2, 49, 15, M, 63, M2, M2, 6,
1108 /*05*/M2, 44, 28, M2, M, M2, M2, 52, 68, M2, M2, 62, M2, M3, M3, M4,
1109 /*06*/M2, 26, 106, M2, 64, M, M2, 2, 120, M, M2, M3, M, M3, M3, M4,
1110 /*07*/116, M2, M2, M3, M2, M3, M, M4, M2, 58, 54, M2, M, M4, M4, M3,
1111 /*08*/C7, M2, M, 42, M, 35, 17, M2, M, 45, 14, M2, 21, M2, M2, 5,
1112 /*09*/M, 27, M, M, 99, M, M, 3, 114, M2, M2, 20, M2, M3, M3, M,
1113 /*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2,
1114 /*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3,
1115 /*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M,
1116 /*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3,
1117 /*0e*/98, M, M2, M3, M2, M, M3, M4, M2, M3, M3, M4, M3, M, M, M,
1118 /*0f*/M2, M3, M3, M, M3, M, M, M, 56, M4, M, M3, M4, M, M, M,
1119 /*10*/C8, M, M2, 39, M, 34, 105, M2, M, 30, 104, M, 101, M, M, 4,
1120 /*11*/M, M, 100, M, 83, M, M2, 12, 87, M, M, 57, M2, M, M3, M,
1121 /*12*/M2, 97, 82, M2, 78, M2, M2, 1, 96, M, M, M, M, M, M3, M2,
1122 /*13*/94, M, M2, M3, M2, M, M3, M, M2, M, 79, M, 69, M, M4, M,
1123 /*14*/M2, 93, 92, M, 91, M, M2, 8, 90, M2, M2, M, M, M, M, M4,
1124 /*15*/89, M, M, M3, M2, M3, M3, M, M, M, M3, M2, M3, M2, M, M3,
1125 /*16*/86, M, M2, M3, M2, M, M3, M, M2, M, M3, M, M3, M, M, M3,
1126 /*17*/M, M, M3, M2, M3, M2, M4, M, 60, M, M2, M3, M4, M, M, M2,
1127 /*18*/M2, 88, 85, M2, 84, M, M2, 55, 81, M2, M2, M3, M2, M3, M3, M4,
1128 /*19*/77, M, M, M, M2, M3, M, M, M2, M3, M3, M4, M3, M2, M, M,
1129 /*1a*/74, M, M2, M3, M, M, M3, M, M, M, M3, M, M3, M, M4, M3,
1130 /*1b*/M2, 70, 107, M4, 65, M2, M2, M, 127, M, M, M, M2, M3, M3, M,
1131 /*1c*/80, M2, M2, 72, M, 119, 118, M, M2, 126, 76, M, 125, M, M4, M3,
1132 /*1d*/M2, 115, 124, M, 75, M, M, M3, 61, M, M4, M, M4, M, M, M,
1133 /*1e*/M, 123, 122, M4, 121, M4, M, M3, 117, M2, M2, M3, M4, M3, M, M,
1134 /*1f*/111, M, M, M, M4, M3, M3, M, M, M, M3, M, M3, M2, M, M
1136 static unsigned char cheetah_mtag_syntab[] = {
1147 /* Return the highest priority error conditon mentioned. */
1148 static inline unsigned long cheetah_get_hipri(unsigned long afsr)
1150 unsigned long tmp = 0;
1153 for (i = 0; cheetah_error_table[i].mask; i++) {
1154 if ((tmp = (afsr & cheetah_error_table[i].mask)) != 0UL)
1160 static const char *cheetah_get_string(unsigned long bit)
1164 for (i = 0; cheetah_error_table[i].mask; i++) {
1165 if ((bit & cheetah_error_table[i].mask) != 0UL)
1166 return cheetah_error_table[i].name;
1171 static void cheetah_log_errors(struct pt_regs *regs, struct cheetah_err_info *info,
1172 unsigned long afsr, unsigned long afar, int recoverable)
1174 unsigned long hipri;
1177 printk("%s" "ERROR(%d): Cheetah error trap taken afsr[%016lx] afar[%016lx] TL1(%d)\n",
1178 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1180 (afsr & CHAFSR_TL1) ? 1 : 0);
1181 printk("%s" "ERROR(%d): TPC[%lx] TNPC[%lx] O7[%lx] TSTATE[%lx]\n",
1182 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1183 regs->tpc, regs->tnpc, regs->u_regs[UREG_I7], regs->tstate);
1184 printk("%s" "ERROR(%d): ",
1185 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id());
1186 printk("TPC<%pS>\n", (void *) regs->tpc);
1187 printk("%s" "ERROR(%d): M_SYND(%lx), E_SYND(%lx)%s%s\n",
1188 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1189 (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT,
1190 (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT,
1191 (afsr & CHAFSR_ME) ? ", Multiple Errors" : "",
1192 (afsr & CHAFSR_PRIV) ? ", Privileged" : "");
1193 hipri = cheetah_get_hipri(afsr);
1194 printk("%s" "ERROR(%d): Highest priority error (%016lx) \"%s\"\n",
1195 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1196 hipri, cheetah_get_string(hipri));
1198 /* Try to get unumber if relevant. */
1199 #define ESYND_ERRORS (CHAFSR_IVC | CHAFSR_IVU | \
1200 CHAFSR_CPC | CHAFSR_CPU | \
1201 CHAFSR_UE | CHAFSR_CE | \
1202 CHAFSR_EDC | CHAFSR_EDU | \
1203 CHAFSR_UCC | CHAFSR_UCU | \
1204 CHAFSR_WDU | CHAFSR_WDC)
1205 #define MSYND_ERRORS (CHAFSR_EMC | CHAFSR_EMU)
1206 if (afsr & ESYND_ERRORS) {
1210 syndrome = (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT;
1211 syndrome = cheetah_ecc_syntab[syndrome];
1212 ret = sprintf_dimm(syndrome, afar, unum, sizeof(unum));
1214 printk("%s" "ERROR(%d): AFAR E-syndrome [%s]\n",
1215 (recoverable ? KERN_WARNING : KERN_CRIT),
1216 smp_processor_id(), unum);
1217 } else if (afsr & MSYND_ERRORS) {
1221 syndrome = (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT;
1222 syndrome = cheetah_mtag_syntab[syndrome];
1223 ret = sprintf_dimm(syndrome, afar, unum, sizeof(unum));
1225 printk("%s" "ERROR(%d): AFAR M-syndrome [%s]\n",
1226 (recoverable ? KERN_WARNING : KERN_CRIT),
1227 smp_processor_id(), unum);
1230 /* Now dump the cache snapshots. */
1231 printk("%s" "ERROR(%d): D-cache idx[%x] tag[%016llx] utag[%016llx] stag[%016llx]\n",
1232 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1233 (int) info->dcache_index,
1237 printk("%s" "ERROR(%d): D-cache data0[%016llx] data1[%016llx] data2[%016llx] data3[%016llx]\n",
1238 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1239 info->dcache_data[0],
1240 info->dcache_data[1],
1241 info->dcache_data[2],
1242 info->dcache_data[3]);
1243 printk("%s" "ERROR(%d): I-cache idx[%x] tag[%016llx] utag[%016llx] stag[%016llx] "
1244 "u[%016llx] l[%016llx]\n",
1245 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1246 (int) info->icache_index,
1251 info->icache_lower);
1252 printk("%s" "ERROR(%d): I-cache INSN0[%016llx] INSN1[%016llx] INSN2[%016llx] INSN3[%016llx]\n",
1253 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1254 info->icache_data[0],
1255 info->icache_data[1],
1256 info->icache_data[2],
1257 info->icache_data[3]);
1258 printk("%s" "ERROR(%d): I-cache INSN4[%016llx] INSN5[%016llx] INSN6[%016llx] INSN7[%016llx]\n",
1259 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1260 info->icache_data[4],
1261 info->icache_data[5],
1262 info->icache_data[6],
1263 info->icache_data[7]);
1264 printk("%s" "ERROR(%d): E-cache idx[%x] tag[%016llx]\n",
1265 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1266 (int) info->ecache_index, info->ecache_tag);
1267 printk("%s" "ERROR(%d): E-cache data0[%016llx] data1[%016llx] data2[%016llx] data3[%016llx]\n",
1268 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1269 info->ecache_data[0],
1270 info->ecache_data[1],
1271 info->ecache_data[2],
1272 info->ecache_data[3]);
1274 afsr = (afsr & ~hipri) & cheetah_afsr_errors;
1275 while (afsr != 0UL) {
1276 unsigned long bit = cheetah_get_hipri(afsr);
1278 printk("%s" "ERROR: Multiple-error (%016lx) \"%s\"\n",
1279 (recoverable ? KERN_WARNING : KERN_CRIT),
1280 bit, cheetah_get_string(bit));
1286 printk(KERN_CRIT "ERROR: This condition is not recoverable.\n");
1289 static int cheetah_recheck_errors(struct cheetah_err_info *logp)
1291 unsigned long afsr, afar;
1294 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1297 if ((afsr & cheetah_afsr_errors) != 0) {
1299 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1307 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1309 : : "r" (afsr), "i" (ASI_AFSR));
1314 void cheetah_fecc_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1316 struct cheetah_err_info local_snapshot, *p;
1320 cheetah_flush_ecache();
1322 p = cheetah_get_error_log(afsr);
1324 prom_printf("ERROR: Early Fast-ECC error afsr[%016lx] afar[%016lx]\n",
1326 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1327 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1331 /* Grab snapshot of logged error. */
1332 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1334 /* If the current trap snapshot does not match what the
1335 * trap handler passed along into our args, big trouble.
1336 * In such a case, mark the local copy as invalid.
1338 * Else, it matches and we mark the afsr in the non-local
1339 * copy as invalid so we may log new error traps there.
1341 if (p->afsr != afsr || p->afar != afar)
1342 local_snapshot.afsr = CHAFSR_INVALID;
1344 p->afsr = CHAFSR_INVALID;
1346 cheetah_flush_icache();
1347 cheetah_flush_dcache();
1349 /* Re-enable I-cache/D-cache */
1350 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1351 "or %%g1, %1, %%g1\n\t"
1352 "stxa %%g1, [%%g0] %0\n\t"
1355 : "i" (ASI_DCU_CONTROL_REG),
1356 "i" (DCU_DC | DCU_IC)
1359 /* Re-enable error reporting */
1360 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1361 "or %%g1, %1, %%g1\n\t"
1362 "stxa %%g1, [%%g0] %0\n\t"
1365 : "i" (ASI_ESTATE_ERROR_EN),
1366 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1369 /* Decide if we can continue after handling this trap and
1370 * logging the error.
1373 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1376 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1377 * error was logged while we had error reporting traps disabled.
1379 if (cheetah_recheck_errors(&local_snapshot)) {
1380 unsigned long new_afsr = local_snapshot.afsr;
1382 /* If we got a new asynchronous error, die... */
1383 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1384 CHAFSR_WDU | CHAFSR_CPU |
1385 CHAFSR_IVU | CHAFSR_UE |
1386 CHAFSR_BERR | CHAFSR_TO))
1391 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1394 panic("Irrecoverable Fast-ECC error trap.\n");
1396 /* Flush E-cache to kick the error trap handlers out. */
1397 cheetah_flush_ecache();
1400 /* Try to fix a correctable error by pushing the line out from
1401 * the E-cache. Recheck error reporting registers to see if the
1402 * problem is intermittent.
1404 static int cheetah_fix_ce(unsigned long physaddr)
1406 unsigned long orig_estate;
1407 unsigned long alias1, alias2;
1410 /* Make sure correctable error traps are disabled. */
1411 __asm__ __volatile__("ldxa [%%g0] %2, %0\n\t"
1412 "andn %0, %1, %%g1\n\t"
1413 "stxa %%g1, [%%g0] %2\n\t"
1415 : "=&r" (orig_estate)
1416 : "i" (ESTATE_ERROR_CEEN),
1417 "i" (ASI_ESTATE_ERROR_EN)
1420 /* We calculate alias addresses that will force the
1421 * cache line in question out of the E-cache. Then
1422 * we bring it back in with an atomic instruction so
1423 * that we get it in some modified/exclusive state,
1424 * then we displace it again to try and get proper ECC
1425 * pushed back into the system.
1427 physaddr &= ~(8UL - 1UL);
1428 alias1 = (ecache_flush_physbase +
1429 (physaddr & ((ecache_flush_size >> 1) - 1)));
1430 alias2 = alias1 + (ecache_flush_size >> 1);
1431 __asm__ __volatile__("ldxa [%0] %3, %%g0\n\t"
1432 "ldxa [%1] %3, %%g0\n\t"
1433 "casxa [%2] %3, %%g0, %%g0\n\t"
1434 "ldxa [%0] %3, %%g0\n\t"
1435 "ldxa [%1] %3, %%g0\n\t"
1438 : "r" (alias1), "r" (alias2),
1439 "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1441 /* Did that trigger another error? */
1442 if (cheetah_recheck_errors(NULL)) {
1443 /* Try one more time. */
1444 __asm__ __volatile__("ldxa [%0] %1, %%g0\n\t"
1446 : : "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1447 if (cheetah_recheck_errors(NULL))
1452 /* No new error, intermittent problem. */
1456 /* Restore error enables. */
1457 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1459 : : "r" (orig_estate), "i" (ASI_ESTATE_ERROR_EN));
1464 /* Return non-zero if PADDR is a valid physical memory address. */
1465 static int cheetah_check_main_memory(unsigned long paddr)
1467 unsigned long vaddr = PAGE_OFFSET + paddr;
1469 if (vaddr > (unsigned long) high_memory)
1472 return kern_addr_valid(vaddr);
1475 void cheetah_cee_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1477 struct cheetah_err_info local_snapshot, *p;
1478 int recoverable, is_memory;
1480 p = cheetah_get_error_log(afsr);
1482 prom_printf("ERROR: Early CEE error afsr[%016lx] afar[%016lx]\n",
1484 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1485 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1489 /* Grab snapshot of logged error. */
1490 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1492 /* If the current trap snapshot does not match what the
1493 * trap handler passed along into our args, big trouble.
1494 * In such a case, mark the local copy as invalid.
1496 * Else, it matches and we mark the afsr in the non-local
1497 * copy as invalid so we may log new error traps there.
1499 if (p->afsr != afsr || p->afar != afar)
1500 local_snapshot.afsr = CHAFSR_INVALID;
1502 p->afsr = CHAFSR_INVALID;
1504 is_memory = cheetah_check_main_memory(afar);
1506 if (is_memory && (afsr & CHAFSR_CE) != 0UL) {
1507 /* XXX Might want to log the results of this operation
1508 * XXX somewhere... -DaveM
1510 cheetah_fix_ce(afar);
1514 int flush_all, flush_line;
1516 flush_all = flush_line = 0;
1517 if ((afsr & CHAFSR_EDC) != 0UL) {
1518 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDC)
1522 } else if ((afsr & CHAFSR_CPC) != 0UL) {
1523 if ((afsr & cheetah_afsr_errors) == CHAFSR_CPC)
1529 /* Trap handler only disabled I-cache, flush it. */
1530 cheetah_flush_icache();
1532 /* Re-enable I-cache */
1533 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1534 "or %%g1, %1, %%g1\n\t"
1535 "stxa %%g1, [%%g0] %0\n\t"
1538 : "i" (ASI_DCU_CONTROL_REG),
1543 cheetah_flush_ecache();
1544 else if (flush_line)
1545 cheetah_flush_ecache_line(afar);
1548 /* Re-enable error reporting */
1549 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1550 "or %%g1, %1, %%g1\n\t"
1551 "stxa %%g1, [%%g0] %0\n\t"
1554 : "i" (ASI_ESTATE_ERROR_EN),
1555 "i" (ESTATE_ERROR_CEEN)
1558 /* Decide if we can continue after handling this trap and
1559 * logging the error.
1562 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1565 /* Re-check AFSR/AFAR */
1566 (void) cheetah_recheck_errors(&local_snapshot);
1569 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1572 panic("Irrecoverable Correctable-ECC error trap.\n");
1575 void cheetah_deferred_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1577 struct cheetah_err_info local_snapshot, *p;
1578 int recoverable, is_memory;
1581 /* Check for the special PCI poke sequence. */
1582 if (pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
1583 cheetah_flush_icache();
1584 cheetah_flush_dcache();
1586 /* Re-enable I-cache/D-cache */
1587 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1588 "or %%g1, %1, %%g1\n\t"
1589 "stxa %%g1, [%%g0] %0\n\t"
1592 : "i" (ASI_DCU_CONTROL_REG),
1593 "i" (DCU_DC | DCU_IC)
1596 /* Re-enable error reporting */
1597 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1598 "or %%g1, %1, %%g1\n\t"
1599 "stxa %%g1, [%%g0] %0\n\t"
1602 : "i" (ASI_ESTATE_ERROR_EN),
1603 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1606 (void) cheetah_recheck_errors(NULL);
1608 pci_poke_faulted = 1;
1610 regs->tnpc = regs->tpc + 4;
1615 p = cheetah_get_error_log(afsr);
1617 prom_printf("ERROR: Early deferred error afsr[%016lx] afar[%016lx]\n",
1619 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1620 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1624 /* Grab snapshot of logged error. */
1625 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1627 /* If the current trap snapshot does not match what the
1628 * trap handler passed along into our args, big trouble.
1629 * In such a case, mark the local copy as invalid.
1631 * Else, it matches and we mark the afsr in the non-local
1632 * copy as invalid so we may log new error traps there.
1634 if (p->afsr != afsr || p->afar != afar)
1635 local_snapshot.afsr = CHAFSR_INVALID;
1637 p->afsr = CHAFSR_INVALID;
1639 is_memory = cheetah_check_main_memory(afar);
1642 int flush_all, flush_line;
1644 flush_all = flush_line = 0;
1645 if ((afsr & CHAFSR_EDU) != 0UL) {
1646 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDU)
1650 } else if ((afsr & CHAFSR_BERR) != 0UL) {
1651 if ((afsr & cheetah_afsr_errors) == CHAFSR_BERR)
1657 cheetah_flush_icache();
1658 cheetah_flush_dcache();
1660 /* Re-enable I/D caches */
1661 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1662 "or %%g1, %1, %%g1\n\t"
1663 "stxa %%g1, [%%g0] %0\n\t"
1666 : "i" (ASI_DCU_CONTROL_REG),
1667 "i" (DCU_IC | DCU_DC)
1671 cheetah_flush_ecache();
1672 else if (flush_line)
1673 cheetah_flush_ecache_line(afar);
1676 /* Re-enable error reporting */
1677 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1678 "or %%g1, %1, %%g1\n\t"
1679 "stxa %%g1, [%%g0] %0\n\t"
1682 : "i" (ASI_ESTATE_ERROR_EN),
1683 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1686 /* Decide if we can continue after handling this trap and
1687 * logging the error.
1690 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1693 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1694 * error was logged while we had error reporting traps disabled.
1696 if (cheetah_recheck_errors(&local_snapshot)) {
1697 unsigned long new_afsr = local_snapshot.afsr;
1699 /* If we got a new asynchronous error, die... */
1700 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1701 CHAFSR_WDU | CHAFSR_CPU |
1702 CHAFSR_IVU | CHAFSR_UE |
1703 CHAFSR_BERR | CHAFSR_TO))
1708 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1710 /* "Recoverable" here means we try to yank the page from ever
1711 * being newly used again. This depends upon a few things:
1712 * 1) Must be main memory, and AFAR must be valid.
1713 * 2) If we trapped from user, OK.
1714 * 3) Else, if we trapped from kernel we must find exception
1715 * table entry (ie. we have to have been accessing user
1718 * If AFAR is not in main memory, or we trapped from kernel
1719 * and cannot find an exception table entry, it is unacceptable
1720 * to try and continue.
1722 if (recoverable && is_memory) {
1723 if ((regs->tstate & TSTATE_PRIV) == 0UL) {
1724 /* OK, usermode access. */
1727 const struct exception_table_entry *entry;
1729 entry = search_exception_tables(regs->tpc);
1731 /* OK, kernel access to userspace. */
1735 /* BAD, privileged state is corrupted. */
1740 if (pfn_valid(afar >> PAGE_SHIFT))
1741 get_page(pfn_to_page(afar >> PAGE_SHIFT));
1745 /* Only perform fixup if we still have a
1746 * recoverable condition.
1749 regs->tpc = entry->fixup;
1750 regs->tnpc = regs->tpc + 4;
1759 panic("Irrecoverable deferred error trap.\n");
1762 /* Handle a D/I cache parity error trap. TYPE is encoded as:
1764 * Bit0: 0=dcache,1=icache
1765 * Bit1: 0=recoverable,1=unrecoverable
1767 * The hardware has disabled both the I-cache and D-cache in
1768 * the %dcr register.
1770 void cheetah_plus_parity_error(int type, struct pt_regs *regs)
1773 __cheetah_flush_icache();
1775 cheetah_plus_zap_dcache_parity();
1776 cheetah_flush_dcache();
1778 /* Re-enable I-cache/D-cache */
1779 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1780 "or %%g1, %1, %%g1\n\t"
1781 "stxa %%g1, [%%g0] %0\n\t"
1784 : "i" (ASI_DCU_CONTROL_REG),
1785 "i" (DCU_DC | DCU_IC)
1789 printk(KERN_EMERG "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1791 (type & 0x1) ? 'I' : 'D',
1793 printk(KERN_EMERG "TPC<%pS>\n", (void *) regs->tpc);
1794 panic("Irrecoverable Cheetah+ parity error.");
1797 printk(KERN_WARNING "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1799 (type & 0x1) ? 'I' : 'D',
1801 printk(KERN_WARNING "TPC<%pS>\n", (void *) regs->tpc);
1804 struct sun4v_error_entry {
1805 /* Unique error handle */
1806 /*0x00*/u64 err_handle;
1808 /* %stick value at the time of the error */
1809 /*0x08*/u64 err_stick;
1811 /*0x10*/u8 reserved_1[3];
1814 /*0x13*/u8 err_type;
1815 #define SUN4V_ERR_TYPE_UNDEFINED 0
1816 #define SUN4V_ERR_TYPE_UNCORRECTED_RES 1
1817 #define SUN4V_ERR_TYPE_PRECISE_NONRES 2
1818 #define SUN4V_ERR_TYPE_DEFERRED_NONRES 3
1819 #define SUN4V_ERR_TYPE_SHUTDOWN_RQST 4
1820 #define SUN4V_ERR_TYPE_DUMP_CORE 5
1821 #define SUN4V_ERR_TYPE_SP_STATE_CHANGE 6
1822 #define SUN4V_ERR_TYPE_NUM 7
1824 /* Error attributes */
1825 /*0x14*/u32 err_attrs;
1826 #define SUN4V_ERR_ATTRS_PROCESSOR 0x00000001
1827 #define SUN4V_ERR_ATTRS_MEMORY 0x00000002
1828 #define SUN4V_ERR_ATTRS_PIO 0x00000004
1829 #define SUN4V_ERR_ATTRS_INT_REGISTERS 0x00000008
1830 #define SUN4V_ERR_ATTRS_FPU_REGISTERS 0x00000010
1831 #define SUN4V_ERR_ATTRS_SHUTDOWN_RQST 0x00000020
1832 #define SUN4V_ERR_ATTRS_ASR 0x00000040
1833 #define SUN4V_ERR_ATTRS_ASI 0x00000080
1834 #define SUN4V_ERR_ATTRS_PRIV_REG 0x00000100
1835 #define SUN4V_ERR_ATTRS_SPSTATE_MSK 0x00000600
1836 #define SUN4V_ERR_ATTRS_MCD 0x00000800
1837 #define SUN4V_ERR_ATTRS_SPSTATE_SHFT 9
1838 #define SUN4V_ERR_ATTRS_MODE_MSK 0x03000000
1839 #define SUN4V_ERR_ATTRS_MODE_SHFT 24
1840 #define SUN4V_ERR_ATTRS_RES_QUEUE_FULL 0x80000000
1842 #define SUN4V_ERR_SPSTATE_FAULTED 0
1843 #define SUN4V_ERR_SPSTATE_AVAILABLE 1
1844 #define SUN4V_ERR_SPSTATE_NOT_PRESENT 2
1846 #define SUN4V_ERR_MODE_USER 1
1847 #define SUN4V_ERR_MODE_PRIV 2
1849 /* Real address of the memory region or PIO transaction */
1850 /*0x18*/u64 err_raddr;
1852 /* Size of the operation triggering the error, in bytes */
1853 /*0x20*/u32 err_size;
1856 /*0x24*/u16 err_cpu;
1858 /* Grace periof for shutdown, in seconds */
1859 /*0x26*/u16 err_secs;
1861 /* Value of the %asi register */
1864 /*0x29*/u8 reserved_2;
1866 /* Value of the ASR register number */
1867 /*0x2a*/u16 err_asr;
1868 #define SUN4V_ERR_ASR_VALID 0x8000
1870 /*0x2c*/u32 reserved_3;
1871 /*0x30*/u64 reserved_4;
1872 /*0x38*/u64 reserved_5;
1875 static atomic_t sun4v_resum_oflow_cnt = ATOMIC_INIT(0);
1876 static atomic_t sun4v_nonresum_oflow_cnt = ATOMIC_INIT(0);
1878 static const char *sun4v_err_type_to_str(u8 type)
1880 static const char *types[SUN4V_ERR_TYPE_NUM] = {
1882 "uncorrected resumable",
1883 "precise nonresumable",
1884 "deferred nonresumable",
1890 if (type < SUN4V_ERR_TYPE_NUM)
1896 static void sun4v_emit_err_attr_strings(u32 attrs)
1898 static const char *attr_names[] = {
1909 static const char *sp_states[] = {
1913 "sp-state-reserved",
1915 static const char *modes[] = {
1924 for (i = 0; i < ARRAY_SIZE(attr_names); i++) {
1925 if (attrs & (1U << i)) {
1926 const char *s = attr_names[i];
1932 sp_state = ((attrs & SUN4V_ERR_ATTRS_SPSTATE_MSK) >>
1933 SUN4V_ERR_ATTRS_SPSTATE_SHFT);
1934 pr_cont("%s ", sp_states[sp_state]);
1936 mode = ((attrs & SUN4V_ERR_ATTRS_MODE_MSK) >>
1937 SUN4V_ERR_ATTRS_MODE_SHFT);
1938 pr_cont("%s ", modes[mode]);
1940 if (attrs & SUN4V_ERR_ATTRS_RES_QUEUE_FULL)
1941 pr_cont("res-queue-full ");
1944 /* When the report contains a real-address of "-1" it means that the
1945 * hardware did not provide the address. So we compute the effective
1946 * address of the load or store instruction at regs->tpc and report
1947 * that. Usually when this happens it's a PIO and in such a case we
1948 * are using physical addresses with bypass ASIs anyways, so what we
1949 * report here is exactly what we want.
1951 static void sun4v_report_real_raddr(const char *pfx, struct pt_regs *regs)
1956 if (!(regs->tstate & TSTATE_PRIV))
1959 insn = *(unsigned int *) regs->tpc;
1961 addr = compute_effective_address(regs, insn, 0);
1963 printk("%s: insn effective address [0x%016llx]\n",
1967 static void sun4v_log_error(struct pt_regs *regs, struct sun4v_error_entry *ent,
1968 int cpu, const char *pfx, atomic_t *ocnt)
1970 u64 *raw_ptr = (u64 *) ent;
1974 printk("%s: Reporting on cpu %d\n", pfx, cpu);
1975 printk("%s: TPC [0x%016lx] <%pS>\n",
1976 pfx, regs->tpc, (void *) regs->tpc);
1978 printk("%s: RAW [%016llx:%016llx:%016llx:%016llx\n",
1979 pfx, raw_ptr[0], raw_ptr[1], raw_ptr[2], raw_ptr[3]);
1980 printk("%s: %016llx:%016llx:%016llx:%016llx]\n",
1981 pfx, raw_ptr[4], raw_ptr[5], raw_ptr[6], raw_ptr[7]);
1983 printk("%s: handle [0x%016llx] stick [0x%016llx]\n",
1984 pfx, ent->err_handle, ent->err_stick);
1986 printk("%s: type [%s]\n", pfx, sun4v_err_type_to_str(ent->err_type));
1988 attrs = ent->err_attrs;
1989 printk("%s: attrs [0x%08x] < ", pfx, attrs);
1990 sun4v_emit_err_attr_strings(attrs);
1993 /* Various fields in the error report are only valid if
1994 * certain attribute bits are set.
1996 if (attrs & (SUN4V_ERR_ATTRS_MEMORY |
1997 SUN4V_ERR_ATTRS_PIO |
1998 SUN4V_ERR_ATTRS_ASI)) {
1999 printk("%s: raddr [0x%016llx]\n", pfx, ent->err_raddr);
2001 if (ent->err_raddr == ~(u64)0)
2002 sun4v_report_real_raddr(pfx, regs);
2005 if (attrs & (SUN4V_ERR_ATTRS_MEMORY | SUN4V_ERR_ATTRS_ASI))
2006 printk("%s: size [0x%x]\n", pfx, ent->err_size);
2008 if (attrs & (SUN4V_ERR_ATTRS_PROCESSOR |
2009 SUN4V_ERR_ATTRS_INT_REGISTERS |
2010 SUN4V_ERR_ATTRS_FPU_REGISTERS |
2011 SUN4V_ERR_ATTRS_PRIV_REG))
2012 printk("%s: cpu[%u]\n", pfx, ent->err_cpu);
2014 if (attrs & SUN4V_ERR_ATTRS_ASI)
2015 printk("%s: asi [0x%02x]\n", pfx, ent->err_asi);
2017 if ((attrs & (SUN4V_ERR_ATTRS_INT_REGISTERS |
2018 SUN4V_ERR_ATTRS_FPU_REGISTERS |
2019 SUN4V_ERR_ATTRS_PRIV_REG)) &&
2020 (ent->err_asr & SUN4V_ERR_ASR_VALID) != 0)
2021 printk("%s: reg [0x%04x]\n",
2022 pfx, ent->err_asr & ~SUN4V_ERR_ASR_VALID);
2026 if ((cnt = atomic_read(ocnt)) != 0) {
2027 atomic_set(ocnt, 0);
2029 printk("%s: Queue overflowed %d times.\n",
2034 /* Handle memory corruption detected error which is vectored in
2035 * through resumable error trap.
2037 void do_mcd_err(struct pt_regs *regs, struct sun4v_error_entry ent)
2039 if (notify_die(DIE_TRAP, "MCD error", regs, 0, 0x34,
2040 SIGSEGV) == NOTIFY_STOP)
2043 if (regs->tstate & TSTATE_PRIV) {
2044 /* MCD exception could happen because the task was
2045 * running a system call with MCD enabled and passed a
2046 * non-versioned pointer or pointer with bad version
2047 * tag to the system call. In such cases, hypervisor
2048 * places the address of offending instruction in the
2049 * resumable error report. This is a deferred error,
2050 * so the read/write that caused the trap was potentially
2051 * retired long time back and we may have no choice
2052 * but to send SIGSEGV to the process.
2054 const struct exception_table_entry *entry;
2056 entry = search_exception_tables(regs->tpc);
2058 /* Looks like a bad syscall parameter */
2059 #ifdef DEBUG_EXCEPTIONS
2060 pr_emerg("Exception: PC<%016lx> faddr<UNKNOWN>\n",
2062 pr_emerg("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
2063 ent.err_raddr, entry->fixup);
2065 regs->tpc = entry->fixup;
2066 regs->tnpc = regs->tpc + 4;
2071 /* Send SIGSEGV to the userspace process with the right signal
2074 force_sig_fault(SIGSEGV, SEGV_ADIDERR, (void __user *)ent.err_raddr,
2078 /* We run with %pil set to PIL_NORMAL_MAX and PSTATE_IE enabled in %pstate.
2079 * Log the event and clear the first word of the entry.
2081 void sun4v_resum_error(struct pt_regs *regs, unsigned long offset)
2083 enum ctx_state prev_state = exception_enter();
2084 struct sun4v_error_entry *ent, local_copy;
2085 struct trap_per_cpu *tb;
2086 unsigned long paddr;
2091 tb = &trap_block[cpu];
2092 paddr = tb->resum_kernel_buf_pa + offset;
2095 memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
2097 /* We have a local copy now, so release the entry. */
2098 ent->err_handle = 0;
2103 if (local_copy.err_type == SUN4V_ERR_TYPE_SHUTDOWN_RQST) {
2104 /* We should really take the seconds field of
2105 * the error report and use it for the shutdown
2106 * invocation, but for now do the same thing we
2107 * do for a DS shutdown request.
2109 pr_info("Shutdown request, %u seconds...\n",
2110 local_copy.err_secs);
2111 orderly_poweroff(true);
2115 /* If this is a memory corruption detected error vectored in
2116 * by HV through resumable error trap, call the handler
2118 if (local_copy.err_attrs & SUN4V_ERR_ATTRS_MCD) {
2119 do_mcd_err(regs, local_copy);
2123 sun4v_log_error(regs, &local_copy, cpu,
2124 KERN_ERR "RESUMABLE ERROR",
2125 &sun4v_resum_oflow_cnt);
2127 exception_exit(prev_state);
2130 /* If we try to printk() we'll probably make matters worse, by trying
2131 * to retake locks this cpu already holds or causing more errors. So
2132 * just bump a counter, and we'll report these counter bumps above.
2134 void sun4v_resum_overflow(struct pt_regs *regs)
2136 atomic_inc(&sun4v_resum_oflow_cnt);
2139 /* Given a set of registers, get the virtual addressi that was being accessed
2140 * by the faulting instructions at tpc.
2142 static unsigned long sun4v_get_vaddr(struct pt_regs *regs)
2146 if (!copy_from_user(&insn, (void __user *)regs->tpc, 4)) {
2147 return compute_effective_address(regs, insn,
2148 (insn >> 25) & 0x1f);
2153 /* Attempt to handle non-resumable errors generated from userspace.
2154 * Returns true if the signal was handled, false otherwise.
2156 bool sun4v_nonresum_error_user_handled(struct pt_regs *regs,
2157 struct sun4v_error_entry *ent) {
2159 unsigned int attrs = ent->err_attrs;
2161 if (attrs & SUN4V_ERR_ATTRS_MEMORY) {
2162 unsigned long addr = ent->err_raddr;
2164 if (addr == ~(u64)0) {
2165 /* This seems highly unlikely to ever occur */
2166 pr_emerg("SUN4V NON-RECOVERABLE ERROR: Memory error detected in unknown location!\n");
2168 unsigned long page_cnt = DIV_ROUND_UP(ent->err_size,
2171 /* Break the unfortunate news. */
2172 pr_emerg("SUN4V NON-RECOVERABLE ERROR: Memory failed at %016lX\n",
2174 pr_emerg("SUN4V NON-RECOVERABLE ERROR: Claiming %lu ages.\n",
2177 while (page_cnt-- > 0) {
2178 if (pfn_valid(addr >> PAGE_SHIFT))
2179 get_page(pfn_to_page(addr >> PAGE_SHIFT));
2183 force_sig(SIGKILL, current);
2187 if (attrs & SUN4V_ERR_ATTRS_PIO) {
2188 force_sig_fault(SIGBUS, BUS_ADRERR,
2189 (void __user *)sun4v_get_vaddr(regs), 0, current);
2193 /* Default to doing nothing */
2197 /* We run with %pil set to PIL_NORMAL_MAX and PSTATE_IE enabled in %pstate.
2198 * Log the event, clear the first word of the entry, and die.
2200 void sun4v_nonresum_error(struct pt_regs *regs, unsigned long offset)
2202 struct sun4v_error_entry *ent, local_copy;
2203 struct trap_per_cpu *tb;
2204 unsigned long paddr;
2209 tb = &trap_block[cpu];
2210 paddr = tb->nonresum_kernel_buf_pa + offset;
2213 memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
2215 /* We have a local copy now, so release the entry. */
2216 ent->err_handle = 0;
2221 if (!(regs->tstate & TSTATE_PRIV) &&
2222 sun4v_nonresum_error_user_handled(regs, &local_copy)) {
2223 /* DON'T PANIC: This userspace error was handled. */
2228 /* Check for the special PCI poke sequence. */
2229 if (pci_poke_in_progress && pci_poke_cpu == cpu) {
2230 pci_poke_faulted = 1;
2232 regs->tnpc = regs->tpc + 4;
2237 sun4v_log_error(regs, &local_copy, cpu,
2238 KERN_EMERG "NON-RESUMABLE ERROR",
2239 &sun4v_nonresum_oflow_cnt);
2241 panic("Non-resumable error.");
2244 /* If we try to printk() we'll probably make matters worse, by trying
2245 * to retake locks this cpu already holds or causing more errors. So
2246 * just bump a counter, and we'll report these counter bumps above.
2248 void sun4v_nonresum_overflow(struct pt_regs *regs)
2250 /* XXX Actually even this can make not that much sense. Perhaps
2251 * XXX we should just pull the plug and panic directly from here?
2253 atomic_inc(&sun4v_nonresum_oflow_cnt);
2256 static void sun4v_tlb_error(struct pt_regs *regs)
2258 die_if_kernel("TLB/TSB error", regs);
2261 unsigned long sun4v_err_itlb_vaddr;
2262 unsigned long sun4v_err_itlb_ctx;
2263 unsigned long sun4v_err_itlb_pte;
2264 unsigned long sun4v_err_itlb_error;
2266 void sun4v_itlb_error_report(struct pt_regs *regs, int tl)
2268 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2270 printk(KERN_EMERG "SUN4V-ITLB: Error at TPC[%lx], tl %d\n",
2272 printk(KERN_EMERG "SUN4V-ITLB: TPC<%pS>\n", (void *) regs->tpc);
2273 printk(KERN_EMERG "SUN4V-ITLB: O7[%lx]\n", regs->u_regs[UREG_I7]);
2274 printk(KERN_EMERG "SUN4V-ITLB: O7<%pS>\n",
2275 (void *) regs->u_regs[UREG_I7]);
2276 printk(KERN_EMERG "SUN4V-ITLB: vaddr[%lx] ctx[%lx] "
2277 "pte[%lx] error[%lx]\n",
2278 sun4v_err_itlb_vaddr, sun4v_err_itlb_ctx,
2279 sun4v_err_itlb_pte, sun4v_err_itlb_error);
2281 sun4v_tlb_error(regs);
2284 unsigned long sun4v_err_dtlb_vaddr;
2285 unsigned long sun4v_err_dtlb_ctx;
2286 unsigned long sun4v_err_dtlb_pte;
2287 unsigned long sun4v_err_dtlb_error;
2289 void sun4v_dtlb_error_report(struct pt_regs *regs, int tl)
2291 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2293 printk(KERN_EMERG "SUN4V-DTLB: Error at TPC[%lx], tl %d\n",
2295 printk(KERN_EMERG "SUN4V-DTLB: TPC<%pS>\n", (void *) regs->tpc);
2296 printk(KERN_EMERG "SUN4V-DTLB: O7[%lx]\n", regs->u_regs[UREG_I7]);
2297 printk(KERN_EMERG "SUN4V-DTLB: O7<%pS>\n",
2298 (void *) regs->u_regs[UREG_I7]);
2299 printk(KERN_EMERG "SUN4V-DTLB: vaddr[%lx] ctx[%lx] "
2300 "pte[%lx] error[%lx]\n",
2301 sun4v_err_dtlb_vaddr, sun4v_err_dtlb_ctx,
2302 sun4v_err_dtlb_pte, sun4v_err_dtlb_error);
2304 sun4v_tlb_error(regs);
2307 void hypervisor_tlbop_error(unsigned long err, unsigned long op)
2309 printk(KERN_CRIT "SUN4V: TLB hv call error %lu for op %lu\n",
2313 void hypervisor_tlbop_error_xcall(unsigned long err, unsigned long op)
2315 printk(KERN_CRIT "SUN4V: XCALL TLB hv call error %lu for op %lu\n",
2319 static void do_fpe_common(struct pt_regs *regs)
2321 if (regs->tstate & TSTATE_PRIV) {
2322 regs->tpc = regs->tnpc;
2325 unsigned long fsr = current_thread_info()->xfsr[0];
2328 if (test_thread_flag(TIF_32BIT)) {
2329 regs->tpc &= 0xffffffff;
2330 regs->tnpc &= 0xffffffff;
2333 if ((fsr & 0x1c000) == (1 << 14)) {
2336 else if (fsr & 0x08)
2338 else if (fsr & 0x04)
2340 else if (fsr & 0x02)
2342 else if (fsr & 0x01)
2345 force_sig_fault(SIGFPE, code,
2346 (void __user *)regs->tpc, 0, current);
2350 void do_fpieee(struct pt_regs *regs)
2352 enum ctx_state prev_state = exception_enter();
2354 if (notify_die(DIE_TRAP, "fpu exception ieee", regs,
2355 0, 0x24, SIGFPE) == NOTIFY_STOP)
2358 do_fpe_common(regs);
2360 exception_exit(prev_state);
2363 void do_fpother(struct pt_regs *regs)
2365 enum ctx_state prev_state = exception_enter();
2366 struct fpustate *f = FPUSTATE;
2369 if (notify_die(DIE_TRAP, "fpu exception other", regs,
2370 0, 0x25, SIGFPE) == NOTIFY_STOP)
2373 switch ((current_thread_info()->xfsr[0] & 0x1c000)) {
2374 case (2 << 14): /* unfinished_FPop */
2375 case (3 << 14): /* unimplemented_FPop */
2376 ret = do_mathemu(regs, f, false);
2381 do_fpe_common(regs);
2383 exception_exit(prev_state);
2386 void do_tof(struct pt_regs *regs)
2388 enum ctx_state prev_state = exception_enter();
2390 if (notify_die(DIE_TRAP, "tagged arithmetic overflow", regs,
2391 0, 0x26, SIGEMT) == NOTIFY_STOP)
2394 if (regs->tstate & TSTATE_PRIV)
2395 die_if_kernel("Penguin overflow trap from kernel mode", regs);
2396 if (test_thread_flag(TIF_32BIT)) {
2397 regs->tpc &= 0xffffffff;
2398 regs->tnpc &= 0xffffffff;
2400 force_sig_fault(SIGEMT, EMT_TAGOVF,
2401 (void __user *)regs->tpc, 0, current);
2403 exception_exit(prev_state);
2406 void do_div0(struct pt_regs *regs)
2408 enum ctx_state prev_state = exception_enter();
2410 if (notify_die(DIE_TRAP, "integer division by zero", regs,
2411 0, 0x28, SIGFPE) == NOTIFY_STOP)
2414 if (regs->tstate & TSTATE_PRIV)
2415 die_if_kernel("TL0: Kernel divide by zero.", regs);
2416 if (test_thread_flag(TIF_32BIT)) {
2417 regs->tpc &= 0xffffffff;
2418 regs->tnpc &= 0xffffffff;
2420 force_sig_fault(SIGFPE, FPE_INTDIV,
2421 (void __user *)regs->tpc, 0, current);
2423 exception_exit(prev_state);
2426 static void instruction_dump(unsigned int *pc)
2430 if ((((unsigned long) pc) & 3))
2433 printk("Instruction DUMP:");
2434 for (i = -3; i < 6; i++)
2435 printk("%c%08x%c",i?' ':'<',pc[i],i?' ':'>');
2439 static void user_instruction_dump(unsigned int __user *pc)
2442 unsigned int buf[9];
2444 if ((((unsigned long) pc) & 3))
2447 if (copy_from_user(buf, pc - 3, sizeof(buf)))
2450 printk("Instruction DUMP:");
2451 for (i = 0; i < 9; i++)
2452 printk("%c%08x%c",i==3?' ':'<',buf[i],i==3?' ':'>');
2456 void show_stack(struct task_struct *tsk, unsigned long *_ksp)
2458 unsigned long fp, ksp;
2459 struct thread_info *tp;
2461 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2465 ksp = (unsigned long) _ksp;
2468 tp = task_thread_info(tsk);
2471 asm("mov %%fp, %0" : "=r" (ksp));
2475 if (tp == current_thread_info())
2478 fp = ksp + STACK_BIAS;
2480 printk("Call Trace:\n");
2482 struct sparc_stackf *sf;
2483 struct pt_regs *regs;
2486 if (!kstack_valid(tp, fp))
2488 sf = (struct sparc_stackf *) fp;
2489 regs = (struct pt_regs *) (sf + 1);
2491 if (kstack_is_trap_frame(tp, regs)) {
2492 if (!(regs->tstate & TSTATE_PRIV))
2495 fp = regs->u_regs[UREG_I6] + STACK_BIAS;
2497 pc = sf->callers_pc;
2498 fp = (unsigned long)sf->fp + STACK_BIAS;
2501 printk(" [%016lx] %pS\n", pc, (void *) pc);
2502 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2503 if ((pc + 8UL) == (unsigned long) &return_to_handler) {
2504 int index = tsk->curr_ret_stack;
2505 if (tsk->ret_stack && index >= graph) {
2506 pc = tsk->ret_stack[index - graph].ret;
2507 printk(" [%016lx] %pS\n", pc, (void *) pc);
2512 } while (++count < 16);
2515 static inline struct reg_window *kernel_stack_up(struct reg_window *rw)
2517 unsigned long fp = rw->ins[6];
2522 return (struct reg_window *) (fp + STACK_BIAS);
2525 void __noreturn die_if_kernel(char *str, struct pt_regs *regs)
2527 static int die_counter;
2530 /* Amuse the user. */
2533 " \"@'/ .. \\`@\"\n"
2537 printk("%s(%d): %s [#%d]\n", current->comm, task_pid_nr(current), str, ++die_counter);
2538 notify_die(DIE_OOPS, str, regs, 0, 255, SIGSEGV);
2539 __asm__ __volatile__("flushw");
2541 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
2542 if (regs->tstate & TSTATE_PRIV) {
2543 struct thread_info *tp = current_thread_info();
2544 struct reg_window *rw = (struct reg_window *)
2545 (regs->u_regs[UREG_FP] + STACK_BIAS);
2547 /* Stop the back trace when we hit userland or we
2548 * find some badly aligned kernel stack.
2552 kstack_valid(tp, (unsigned long) rw)) {
2553 printk("Caller[%016lx]: %pS\n", rw->ins[7],
2554 (void *) rw->ins[7]);
2556 rw = kernel_stack_up(rw);
2558 instruction_dump ((unsigned int *) regs->tpc);
2560 if (test_thread_flag(TIF_32BIT)) {
2561 regs->tpc &= 0xffffffff;
2562 regs->tnpc &= 0xffffffff;
2564 user_instruction_dump ((unsigned int __user *) regs->tpc);
2567 panic("Fatal exception");
2568 if (regs->tstate & TSTATE_PRIV)
2572 EXPORT_SYMBOL(die_if_kernel);
2574 #define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19))
2575 #define VIS_OPCODE_VAL ((0x2 << 30) | (0x36 << 19))
2577 void do_illegal_instruction(struct pt_regs *regs)
2579 enum ctx_state prev_state = exception_enter();
2580 unsigned long pc = regs->tpc;
2581 unsigned long tstate = regs->tstate;
2584 if (notify_die(DIE_TRAP, "illegal instruction", regs,
2585 0, 0x10, SIGILL) == NOTIFY_STOP)
2588 if (tstate & TSTATE_PRIV)
2589 die_if_kernel("Kernel illegal instruction", regs);
2590 if (test_thread_flag(TIF_32BIT))
2592 if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
2593 if ((insn & 0xc1ffc000) == 0x81700000) /* POPC */ {
2594 if (handle_popc(insn, regs))
2596 } else if ((insn & 0xc1580000) == 0xc1100000) /* LDQ/STQ */ {
2597 if (handle_ldf_stq(insn, regs))
2599 } else if (tlb_type == hypervisor) {
2600 if ((insn & VIS_OPCODE_MASK) == VIS_OPCODE_VAL) {
2601 if (!vis_emul(regs, insn))
2604 struct fpustate *f = FPUSTATE;
2606 /* On UltraSPARC T2 and later, FPU insns which
2607 * are not implemented in HW signal an illegal
2608 * instruction trap and do not set the FP Trap
2609 * Trap in the %fsr to unimplemented_FPop.
2611 if (do_mathemu(regs, f, true))
2616 force_sig_fault(SIGILL, ILL_ILLOPC, (void __user *)pc, 0, current);
2618 exception_exit(prev_state);
2621 void mem_address_unaligned(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
2623 enum ctx_state prev_state = exception_enter();
2625 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2626 0, 0x34, SIGSEGV) == NOTIFY_STOP)
2629 if (regs->tstate & TSTATE_PRIV) {
2630 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2633 if (is_no_fault_exception(regs))
2636 force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)sfar, 0, current);
2638 exception_exit(prev_state);
2641 void sun4v_do_mna(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
2643 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2644 0, 0x34, SIGSEGV) == NOTIFY_STOP)
2647 if (regs->tstate & TSTATE_PRIV) {
2648 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2651 if (is_no_fault_exception(regs))
2654 force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *) addr, 0, current);
2657 /* sun4v_mem_corrupt_detect_precise() - Handle precise exception on an ADI
2660 * ADI version tag mismatch on a load from memory always results in a
2661 * precise exception. Tag mismatch on a store to memory will result in
2662 * precise exception if MCDPER or PMCDPER is set to 1.
2664 void sun4v_mem_corrupt_detect_precise(struct pt_regs *regs, unsigned long addr,
2665 unsigned long context)
2667 if (notify_die(DIE_TRAP, "memory corruption precise exception", regs,
2668 0, 0x8, SIGSEGV) == NOTIFY_STOP)
2671 if (regs->tstate & TSTATE_PRIV) {
2672 /* MCD exception could happen because the task was running
2673 * a system call with MCD enabled and passed a non-versioned
2674 * pointer or pointer with bad version tag to the system
2677 const struct exception_table_entry *entry;
2679 entry = search_exception_tables(regs->tpc);
2681 /* Looks like a bad syscall parameter */
2682 #ifdef DEBUG_EXCEPTIONS
2683 pr_emerg("Exception: PC<%016lx> faddr<UNKNOWN>\n",
2685 pr_emerg("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
2686 regs->tpc, entry->fixup);
2688 regs->tpc = entry->fixup;
2689 regs->tnpc = regs->tpc + 4;
2692 pr_emerg("%s: ADDR[%016lx] CTX[%lx], going.\n",
2693 __func__, addr, context);
2694 die_if_kernel("MCD precise", regs);
2697 if (test_thread_flag(TIF_32BIT)) {
2698 regs->tpc &= 0xffffffff;
2699 regs->tnpc &= 0xffffffff;
2701 force_sig_fault(SIGSEGV, SEGV_ADIPERR, (void __user *)addr, 0, current);
2704 void do_privop(struct pt_regs *regs)
2706 enum ctx_state prev_state = exception_enter();
2708 if (notify_die(DIE_TRAP, "privileged operation", regs,
2709 0, 0x11, SIGILL) == NOTIFY_STOP)
2712 if (test_thread_flag(TIF_32BIT)) {
2713 regs->tpc &= 0xffffffff;
2714 regs->tnpc &= 0xffffffff;
2716 force_sig_fault(SIGILL, ILL_PRVOPC,
2717 (void __user *)regs->tpc, 0, current);
2719 exception_exit(prev_state);
2722 void do_privact(struct pt_regs *regs)
2727 /* Trap level 1 stuff or other traps we should never see... */
2728 void do_cee(struct pt_regs *regs)
2731 die_if_kernel("TL0: Cache Error Exception", regs);
2734 void do_div0_tl1(struct pt_regs *regs)
2737 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2738 die_if_kernel("TL1: DIV0 Exception", regs);
2741 void do_fpieee_tl1(struct pt_regs *regs)
2744 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2745 die_if_kernel("TL1: FPU IEEE Exception", regs);
2748 void do_fpother_tl1(struct pt_regs *regs)
2751 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2752 die_if_kernel("TL1: FPU Other Exception", regs);
2755 void do_ill_tl1(struct pt_regs *regs)
2758 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2759 die_if_kernel("TL1: Illegal Instruction Exception", regs);
2762 void do_irq_tl1(struct pt_regs *regs)
2765 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2766 die_if_kernel("TL1: IRQ Exception", regs);
2769 void do_lddfmna_tl1(struct pt_regs *regs)
2772 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2773 die_if_kernel("TL1: LDDF Exception", regs);
2776 void do_stdfmna_tl1(struct pt_regs *regs)
2779 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2780 die_if_kernel("TL1: STDF Exception", regs);
2783 void do_paw(struct pt_regs *regs)
2786 die_if_kernel("TL0: Phys Watchpoint Exception", regs);
2789 void do_paw_tl1(struct pt_regs *regs)
2792 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2793 die_if_kernel("TL1: Phys Watchpoint Exception", regs);
2796 void do_vaw(struct pt_regs *regs)
2799 die_if_kernel("TL0: Virt Watchpoint Exception", regs);
2802 void do_vaw_tl1(struct pt_regs *regs)
2805 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2806 die_if_kernel("TL1: Virt Watchpoint Exception", regs);
2809 void do_tof_tl1(struct pt_regs *regs)
2812 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2813 die_if_kernel("TL1: Tag Overflow Exception", regs);
2816 void do_getpsr(struct pt_regs *regs)
2818 regs->u_regs[UREG_I0] = tstate_to_psr(regs->tstate);
2819 regs->tpc = regs->tnpc;
2821 if (test_thread_flag(TIF_32BIT)) {
2822 regs->tpc &= 0xffffffff;
2823 regs->tnpc &= 0xffffffff;
2827 u64 cpu_mondo_counter[NR_CPUS] = {0};
2828 struct trap_per_cpu trap_block[NR_CPUS];
2829 EXPORT_SYMBOL(trap_block);
2831 /* This can get invoked before sched_init() so play it super safe
2832 * and use hard_smp_processor_id().
2834 void notrace init_cur_cpu_trap(struct thread_info *t)
2836 int cpu = hard_smp_processor_id();
2837 struct trap_per_cpu *p = &trap_block[cpu];
2843 extern void thread_info_offsets_are_bolixed_dave(void);
2844 extern void trap_per_cpu_offsets_are_bolixed_dave(void);
2845 extern void tsb_config_offsets_are_bolixed_dave(void);
2847 /* Only invoked on boot processor. */
2848 void __init trap_init(void)
2850 /* Compile time sanity check. */
2851 BUILD_BUG_ON(TI_TASK != offsetof(struct thread_info, task) ||
2852 TI_FLAGS != offsetof(struct thread_info, flags) ||
2853 TI_CPU != offsetof(struct thread_info, cpu) ||
2854 TI_FPSAVED != offsetof(struct thread_info, fpsaved) ||
2855 TI_KSP != offsetof(struct thread_info, ksp) ||
2856 TI_FAULT_ADDR != offsetof(struct thread_info,
2858 TI_KREGS != offsetof(struct thread_info, kregs) ||
2859 TI_UTRAPS != offsetof(struct thread_info, utraps) ||
2860 TI_REG_WINDOW != offsetof(struct thread_info,
2862 TI_RWIN_SPTRS != offsetof(struct thread_info,
2864 TI_GSR != offsetof(struct thread_info, gsr) ||
2865 TI_XFSR != offsetof(struct thread_info, xfsr) ||
2866 TI_PRE_COUNT != offsetof(struct thread_info,
2868 TI_NEW_CHILD != offsetof(struct thread_info, new_child) ||
2869 TI_CURRENT_DS != offsetof(struct thread_info,
2871 TI_KUNA_REGS != offsetof(struct thread_info,
2873 TI_KUNA_INSN != offsetof(struct thread_info,
2875 TI_FPREGS != offsetof(struct thread_info, fpregs) ||
2876 (TI_FPREGS & (64 - 1)));
2878 BUILD_BUG_ON(TRAP_PER_CPU_THREAD != offsetof(struct trap_per_cpu,
2880 (TRAP_PER_CPU_PGD_PADDR !=
2881 offsetof(struct trap_per_cpu, pgd_paddr)) ||
2882 (TRAP_PER_CPU_CPU_MONDO_PA !=
2883 offsetof(struct trap_per_cpu, cpu_mondo_pa)) ||
2884 (TRAP_PER_CPU_DEV_MONDO_PA !=
2885 offsetof(struct trap_per_cpu, dev_mondo_pa)) ||
2886 (TRAP_PER_CPU_RESUM_MONDO_PA !=
2887 offsetof(struct trap_per_cpu, resum_mondo_pa)) ||
2888 (TRAP_PER_CPU_RESUM_KBUF_PA !=
2889 offsetof(struct trap_per_cpu, resum_kernel_buf_pa)) ||
2890 (TRAP_PER_CPU_NONRESUM_MONDO_PA !=
2891 offsetof(struct trap_per_cpu, nonresum_mondo_pa)) ||
2892 (TRAP_PER_CPU_NONRESUM_KBUF_PA !=
2893 offsetof(struct trap_per_cpu, nonresum_kernel_buf_pa)) ||
2894 (TRAP_PER_CPU_FAULT_INFO !=
2895 offsetof(struct trap_per_cpu, fault_info)) ||
2896 (TRAP_PER_CPU_CPU_MONDO_BLOCK_PA !=
2897 offsetof(struct trap_per_cpu, cpu_mondo_block_pa)) ||
2898 (TRAP_PER_CPU_CPU_LIST_PA !=
2899 offsetof(struct trap_per_cpu, cpu_list_pa)) ||
2900 (TRAP_PER_CPU_TSB_HUGE !=
2901 offsetof(struct trap_per_cpu, tsb_huge)) ||
2902 (TRAP_PER_CPU_TSB_HUGE_TEMP !=
2903 offsetof(struct trap_per_cpu, tsb_huge_temp)) ||
2904 (TRAP_PER_CPU_IRQ_WORKLIST_PA !=
2905 offsetof(struct trap_per_cpu, irq_worklist_pa)) ||
2906 (TRAP_PER_CPU_CPU_MONDO_QMASK !=
2907 offsetof(struct trap_per_cpu, cpu_mondo_qmask)) ||
2908 (TRAP_PER_CPU_DEV_MONDO_QMASK !=
2909 offsetof(struct trap_per_cpu, dev_mondo_qmask)) ||
2910 (TRAP_PER_CPU_RESUM_QMASK !=
2911 offsetof(struct trap_per_cpu, resum_qmask)) ||
2912 (TRAP_PER_CPU_NONRESUM_QMASK !=
2913 offsetof(struct trap_per_cpu, nonresum_qmask)) ||
2914 (TRAP_PER_CPU_PER_CPU_BASE !=
2915 offsetof(struct trap_per_cpu, __per_cpu_base)));
2917 BUILD_BUG_ON((TSB_CONFIG_TSB !=
2918 offsetof(struct tsb_config, tsb)) ||
2919 (TSB_CONFIG_RSS_LIMIT !=
2920 offsetof(struct tsb_config, tsb_rss_limit)) ||
2921 (TSB_CONFIG_NENTRIES !=
2922 offsetof(struct tsb_config, tsb_nentries)) ||
2923 (TSB_CONFIG_REG_VAL !=
2924 offsetof(struct tsb_config, tsb_reg_val)) ||
2925 (TSB_CONFIG_MAP_VADDR !=
2926 offsetof(struct tsb_config, tsb_map_vaddr)) ||
2927 (TSB_CONFIG_MAP_PTE !=
2928 offsetof(struct tsb_config, tsb_map_pte)));
2930 /* Attach to the address space of init_task. On SMP we
2931 * do this in smp.c:smp_callin for other cpus.
2934 current->active_mm = &init_mm;