1 // SPDX-License-Identifier: GPL-2.0-only
3 * Based on arch/arm/kernel/traps.c
5 * Copyright (C) 1995-2009 Russell King
6 * Copyright (C) 2012 ARM Ltd.
10 #include <linux/context_tracking.h>
11 #include <linux/signal.h>
12 #include <linux/personality.h>
13 #include <linux/kallsyms.h>
14 #include <linux/kprobes.h>
15 #include <linux/spinlock.h>
16 #include <linux/uaccess.h>
17 #include <linux/hardirq.h>
18 #include <linux/kdebug.h>
19 #include <linux/module.h>
20 #include <linux/kexec.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/sched/signal.h>
24 #include <linux/sched/debug.h>
25 #include <linux/sched/task_stack.h>
26 #include <linux/sizes.h>
27 #include <linux/syscalls.h>
28 #include <linux/mm_types.h>
29 #include <linux/kasan.h>
31 #include <asm/atomic.h>
33 #include <asm/cpufeature.h>
34 #include <asm/daifflags.h>
35 #include <asm/debug-monitors.h>
38 #include <asm/traps.h>
40 #include <asm/stack_pointer.h>
41 #include <asm/stacktrace.h>
42 #include <asm/exception.h>
43 #include <asm/system_misc.h>
44 #include <asm/sysreg.h>
46 static const char *handler[]= {
53 int show_unhandled_signals = 0;
55 static void dump_backtrace_entry(unsigned long where)
57 printk(" %pS\n", (void *)where);
60 static void dump_kernel_instr(const char *lvl, struct pt_regs *regs)
62 unsigned long addr = instruction_pointer(regs);
63 char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str;
69 for (i = -4; i < 1; i++) {
70 unsigned int val, bad;
72 bad = aarch64_insn_read(&((u32 *)addr)[i], &val);
75 p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val);
77 p += sprintf(p, "bad PC value");
82 printk("%sCode: %s\n", lvl, str);
85 void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk)
87 struct stackframe frame;
90 pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk);
101 if (!try_get_task_stack(tsk))
104 if (tsk == current) {
105 start_backtrace(&frame,
106 (unsigned long)__builtin_frame_address(0),
107 (unsigned long)dump_backtrace);
110 * task blocked in __switch_to
112 start_backtrace(&frame,
113 thread_saved_fp(tsk),
114 thread_saved_pc(tsk));
117 printk("Call trace:\n");
119 /* skip until specified stack frame */
121 dump_backtrace_entry(frame.pc);
122 } else if (frame.fp == regs->regs[29]) {
125 * Mostly, this is the case where this function is
126 * called in panic/abort. As exception handler's
127 * stack frame does not contain the corresponding pc
128 * at which an exception has taken place, use regs->pc
131 dump_backtrace_entry(regs->pc);
133 } while (!unwind_frame(tsk, &frame));
138 void show_stack(struct task_struct *tsk, unsigned long *sp)
140 dump_backtrace(NULL, tsk);
144 #ifdef CONFIG_PREEMPT
145 #define S_PREEMPT " PREEMPT"
151 static int __die(const char *str, int err, struct pt_regs *regs)
153 static int die_counter;
156 pr_emerg("Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n",
157 str, err, ++die_counter);
159 /* trap and error numbers are mostly meaningless on ARM */
160 ret = notify_die(DIE_OOPS, str, regs, err, 0, SIGSEGV);
161 if (ret == NOTIFY_STOP)
167 dump_kernel_instr(KERN_EMERG, regs);
172 static DEFINE_RAW_SPINLOCK(die_lock);
175 * This function is protected against re-entrancy.
177 void die(const char *str, struct pt_regs *regs, int err)
182 raw_spin_lock_irqsave(&die_lock, flags);
188 ret = __die(str, err, regs);
190 if (regs && kexec_should_crash(current))
194 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
198 panic("Fatal exception in interrupt");
200 panic("Fatal exception");
202 raw_spin_unlock_irqrestore(&die_lock, flags);
204 if (ret != NOTIFY_STOP)
205 make_task_dead(SIGSEGV);
208 static void arm64_show_signal(int signo, const char *str)
210 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
211 DEFAULT_RATELIMIT_BURST);
212 struct task_struct *tsk = current;
213 unsigned int esr = tsk->thread.fault_code;
214 struct pt_regs *regs = task_pt_regs(tsk);
216 /* Leave if the signal won't be shown */
217 if (!show_unhandled_signals ||
218 !unhandled_signal(tsk, signo) ||
222 pr_info("%s[%d]: unhandled exception: ", tsk->comm, task_pid_nr(tsk));
224 pr_cont("%s, ESR 0x%08x, ", esr_get_class_string(esr), esr);
227 print_vma_addr(KERN_CONT " in ", regs->pc);
232 void arm64_force_sig_fault(int signo, int code, void __user *addr,
235 arm64_show_signal(signo, str);
236 if (signo == SIGKILL)
239 force_sig_fault(signo, code, addr);
242 void arm64_force_sig_mceerr(int code, void __user *addr, short lsb,
245 arm64_show_signal(SIGBUS, str);
246 force_sig_mceerr(code, addr, lsb);
249 void arm64_force_sig_ptrace_errno_trap(int errno, void __user *addr,
252 arm64_show_signal(SIGTRAP, str);
253 force_sig_ptrace_errno_trap(errno, addr);
256 void arm64_notify_die(const char *str, struct pt_regs *regs,
257 int signo, int sicode, void __user *addr,
260 if (user_mode(regs)) {
261 WARN_ON(regs != current_pt_regs());
262 current->thread.fault_address = 0;
263 current->thread.fault_code = err;
265 arm64_force_sig_fault(signo, sicode, addr, str);
271 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size)
276 * If we were single stepping, we want to get the step exception after
277 * we return from the trap.
280 user_fastforward_single_step(current);
283 static LIST_HEAD(undef_hook);
284 static DEFINE_RAW_SPINLOCK(undef_lock);
286 void register_undef_hook(struct undef_hook *hook)
290 raw_spin_lock_irqsave(&undef_lock, flags);
291 list_add(&hook->node, &undef_hook);
292 raw_spin_unlock_irqrestore(&undef_lock, flags);
295 void unregister_undef_hook(struct undef_hook *hook)
299 raw_spin_lock_irqsave(&undef_lock, flags);
300 list_del(&hook->node);
301 raw_spin_unlock_irqrestore(&undef_lock, flags);
304 static int call_undef_hook(struct pt_regs *regs)
306 struct undef_hook *hook;
309 int (*fn)(struct pt_regs *regs, u32 instr) = NULL;
310 void __user *pc = (void __user *)instruction_pointer(regs);
312 if (!user_mode(regs)) {
314 if (probe_kernel_address((__force __le32 *)pc, instr_le))
316 instr = le32_to_cpu(instr_le);
317 } else if (compat_thumb_mode(regs)) {
318 /* 16-bit Thumb instruction */
320 if (get_user(instr_le, (__le16 __user *)pc))
322 instr = le16_to_cpu(instr_le);
323 if (aarch32_insn_is_wide(instr)) {
326 if (get_user(instr_le, (__le16 __user *)(pc + 2)))
328 instr2 = le16_to_cpu(instr_le);
329 instr = (instr << 16) | instr2;
332 /* 32-bit ARM instruction */
334 if (get_user(instr_le, (__le32 __user *)pc))
336 instr = le32_to_cpu(instr_le);
339 raw_spin_lock_irqsave(&undef_lock, flags);
340 list_for_each_entry(hook, &undef_hook, node)
341 if ((instr & hook->instr_mask) == hook->instr_val &&
342 (regs->pstate & hook->pstate_mask) == hook->pstate_val)
345 raw_spin_unlock_irqrestore(&undef_lock, flags);
347 return fn ? fn(regs, instr) : 1;
350 void force_signal_inject(int signal, int code, unsigned long address)
353 struct pt_regs *regs = current_pt_regs();
355 if (WARN_ON(!user_mode(regs)))
360 desc = "undefined instruction";
363 desc = "illegal memory access";
366 desc = "unknown or unrecoverable error";
370 /* Force signals we don't understand to SIGKILL */
371 if (WARN_ON(signal != SIGKILL &&
372 siginfo_layout(signal, code) != SIL_FAULT)) {
376 arm64_notify_die(desc, regs, signal, code, (void __user *)address, 0);
380 * Set up process info to signal segmentation fault - called on access error.
382 void arm64_notify_segfault(unsigned long addr)
386 down_read(¤t->mm->mmap_sem);
387 if (find_vma(current->mm, addr) == NULL)
391 up_read(¤t->mm->mmap_sem);
393 force_signal_inject(SIGSEGV, code, addr);
396 asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
398 /* check for AArch32 breakpoint instructions */
399 if (!aarch32_break_handler(regs))
402 if (call_undef_hook(regs) == 0)
405 BUG_ON(!user_mode(regs));
406 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc);
409 #define __user_cache_maint(insn, address, res) \
410 if (address >= user_addr_max()) { \
413 uaccess_ttbr0_enable(); \
415 "1: " insn ", %1\n" \
418 " .pushsection .fixup,\"ax\"\n" \
420 "3: mov %w0, %w2\n" \
423 _ASM_EXTABLE(1b, 3b) \
425 : "r" (address), "i" (-EFAULT)); \
426 uaccess_ttbr0_disable(); \
429 static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs)
431 unsigned long address;
432 int rt = ESR_ELx_SYS64_ISS_RT(esr);
433 int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT;
436 address = untagged_addr(pt_regs_read_reg(regs, rt));
439 case ESR_ELx_SYS64_ISS_CRM_DC_CVAU: /* DC CVAU, gets promoted */
440 __user_cache_maint("dc civac", address, ret);
442 case ESR_ELx_SYS64_ISS_CRM_DC_CVAC: /* DC CVAC, gets promoted */
443 __user_cache_maint("dc civac", address, ret);
445 case ESR_ELx_SYS64_ISS_CRM_DC_CVADP: /* DC CVADP */
446 __user_cache_maint("sys 3, c7, c13, 1", address, ret);
448 case ESR_ELx_SYS64_ISS_CRM_DC_CVAP: /* DC CVAP */
449 __user_cache_maint("sys 3, c7, c12, 1", address, ret);
451 case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC: /* DC CIVAC */
452 __user_cache_maint("dc civac", address, ret);
454 case ESR_ELx_SYS64_ISS_CRM_IC_IVAU: /* IC IVAU */
455 __user_cache_maint("ic ivau", address, ret);
458 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc);
463 arm64_notify_segfault(address);
465 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
468 static void ctr_read_handler(unsigned int esr, struct pt_regs *regs)
470 int rt = ESR_ELx_SYS64_ISS_RT(esr);
471 unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0);
473 if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) {
474 /* Hide DIC so that we can trap the unnecessary maintenance...*/
475 val &= ~BIT(CTR_DIC_SHIFT);
477 /* ... and fake IminLine to reduce the number of traps. */
478 val &= ~CTR_IMINLINE_MASK;
479 val |= (PAGE_SHIFT - 2) & CTR_IMINLINE_MASK;
482 pt_regs_write_reg(regs, rt, val);
484 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
487 static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs)
489 int rt = ESR_ELx_SYS64_ISS_RT(esr);
491 pt_regs_write_reg(regs, rt, arch_timer_read_counter());
492 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
495 static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs)
497 int rt = ESR_ELx_SYS64_ISS_RT(esr);
499 pt_regs_write_reg(regs, rt, arch_timer_get_rate());
500 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
503 static void mrs_handler(unsigned int esr, struct pt_regs *regs)
507 rt = ESR_ELx_SYS64_ISS_RT(esr);
508 sysreg = esr_sys64_to_sysreg(esr);
510 if (do_emulate_mrs(regs, sysreg, rt) != 0)
511 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc);
514 static void wfi_handler(unsigned int esr, struct pt_regs *regs)
516 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
520 unsigned int esr_mask;
521 unsigned int esr_val;
522 void (*handler)(unsigned int esr, struct pt_regs *regs);
525 static const struct sys64_hook sys64_hooks[] = {
527 .esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK,
528 .esr_val = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL,
529 .handler = user_cache_maint_handler,
532 /* Trap read access to CTR_EL0 */
533 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
534 .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ,
535 .handler = ctr_read_handler,
538 /* Trap read access to CNTVCT_EL0 */
539 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
540 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT,
541 .handler = cntvct_read_handler,
544 /* Trap read access to CNTFRQ_EL0 */
545 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
546 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTFRQ,
547 .handler = cntfrq_read_handler,
550 /* Trap read access to CPUID registers */
551 .esr_mask = ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK,
552 .esr_val = ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL,
553 .handler = mrs_handler,
556 /* Trap WFI instructions executed in userspace */
557 .esr_mask = ESR_ELx_WFx_MASK,
558 .esr_val = ESR_ELx_WFx_WFI_VAL,
559 .handler = wfi_handler,
566 #define PSTATE_IT_1_0_SHIFT 25
567 #define PSTATE_IT_1_0_MASK (0x3 << PSTATE_IT_1_0_SHIFT)
568 #define PSTATE_IT_7_2_SHIFT 10
569 #define PSTATE_IT_7_2_MASK (0x3f << PSTATE_IT_7_2_SHIFT)
571 static u32 compat_get_it_state(struct pt_regs *regs)
573 u32 it, pstate = regs->pstate;
575 it = (pstate & PSTATE_IT_1_0_MASK) >> PSTATE_IT_1_0_SHIFT;
576 it |= ((pstate & PSTATE_IT_7_2_MASK) >> PSTATE_IT_7_2_SHIFT) << 2;
581 static void compat_set_it_state(struct pt_regs *regs, u32 it)
585 pstate_it = (it << PSTATE_IT_1_0_SHIFT) & PSTATE_IT_1_0_MASK;
586 pstate_it |= ((it >> 2) << PSTATE_IT_7_2_SHIFT) & PSTATE_IT_7_2_MASK;
588 regs->pstate &= ~PSR_AA32_IT_MASK;
589 regs->pstate |= pstate_it;
592 static bool cp15_cond_valid(unsigned int esr, struct pt_regs *regs)
596 /* Only a T32 instruction can trap without CV being set */
597 if (!(esr & ESR_ELx_CV)) {
600 it = compat_get_it_state(regs);
606 cond = (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT;
609 return aarch32_opcode_cond_checks[cond](regs->pstate);
612 static void advance_itstate(struct pt_regs *regs)
617 if (!(regs->pstate & PSR_AA32_T_BIT) ||
618 !(regs->pstate & PSR_AA32_IT_MASK))
621 it = compat_get_it_state(regs);
624 * If this is the last instruction of the block, wipe the IT
625 * state. Otherwise advance it.
630 it = (it & 0xe0) | ((it << 1) & 0x1f);
632 compat_set_it_state(regs, it);
635 static void arm64_compat_skip_faulting_instruction(struct pt_regs *regs,
638 advance_itstate(regs);
639 arm64_skip_faulting_instruction(regs, sz);
642 static void compat_cntfrq_read_handler(unsigned int esr, struct pt_regs *regs)
644 int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT;
646 pt_regs_write_reg(regs, reg, arch_timer_get_rate());
647 arm64_compat_skip_faulting_instruction(regs, 4);
650 static const struct sys64_hook cp15_32_hooks[] = {
652 .esr_mask = ESR_ELx_CP15_32_ISS_SYS_MASK,
653 .esr_val = ESR_ELx_CP15_32_ISS_SYS_CNTFRQ,
654 .handler = compat_cntfrq_read_handler,
659 static void compat_cntvct_read_handler(unsigned int esr, struct pt_regs *regs)
661 int rt = (esr & ESR_ELx_CP15_64_ISS_RT_MASK) >> ESR_ELx_CP15_64_ISS_RT_SHIFT;
662 int rt2 = (esr & ESR_ELx_CP15_64_ISS_RT2_MASK) >> ESR_ELx_CP15_64_ISS_RT2_SHIFT;
663 u64 val = arch_timer_read_counter();
665 pt_regs_write_reg(regs, rt, lower_32_bits(val));
666 pt_regs_write_reg(regs, rt2, upper_32_bits(val));
667 arm64_compat_skip_faulting_instruction(regs, 4);
670 static const struct sys64_hook cp15_64_hooks[] = {
672 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK,
673 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCT,
674 .handler = compat_cntvct_read_handler,
679 asmlinkage void __exception do_cp15instr(unsigned int esr, struct pt_regs *regs)
681 const struct sys64_hook *hook, *hook_base;
683 if (!cp15_cond_valid(esr, regs)) {
685 * There is no T16 variant of a CP access, so we
686 * always advance PC by 4 bytes.
688 arm64_compat_skip_faulting_instruction(regs, 4);
692 switch (ESR_ELx_EC(esr)) {
693 case ESR_ELx_EC_CP15_32:
694 hook_base = cp15_32_hooks;
696 case ESR_ELx_EC_CP15_64:
697 hook_base = cp15_64_hooks;
704 for (hook = hook_base; hook->handler; hook++)
705 if ((hook->esr_mask & esr) == hook->esr_val) {
706 hook->handler(esr, regs);
711 * New cp15 instructions may previously have been undefined at
712 * EL0. Fall back to our usual undefined instruction handler
713 * so that we handle these consistently.
719 asmlinkage void __exception do_sysinstr(unsigned int esr, struct pt_regs *regs)
721 const struct sys64_hook *hook;
723 for (hook = sys64_hooks; hook->handler; hook++)
724 if ((hook->esr_mask & esr) == hook->esr_val) {
725 hook->handler(esr, regs);
730 * New SYS instructions may previously have been undefined at EL0. Fall
731 * back to our usual undefined instruction handler so that we handle
732 * these consistently.
737 static const char *esr_class_str[] = {
738 [0 ... ESR_ELx_EC_MAX] = "UNRECOGNIZED EC",
739 [ESR_ELx_EC_UNKNOWN] = "Unknown/Uncategorized",
740 [ESR_ELx_EC_WFx] = "WFI/WFE",
741 [ESR_ELx_EC_CP15_32] = "CP15 MCR/MRC",
742 [ESR_ELx_EC_CP15_64] = "CP15 MCRR/MRRC",
743 [ESR_ELx_EC_CP14_MR] = "CP14 MCR/MRC",
744 [ESR_ELx_EC_CP14_LS] = "CP14 LDC/STC",
745 [ESR_ELx_EC_FP_ASIMD] = "ASIMD",
746 [ESR_ELx_EC_CP10_ID] = "CP10 MRC/VMRS",
747 [ESR_ELx_EC_PAC] = "PAC",
748 [ESR_ELx_EC_CP14_64] = "CP14 MCRR/MRRC",
749 [ESR_ELx_EC_ILL] = "PSTATE.IL",
750 [ESR_ELx_EC_SVC32] = "SVC (AArch32)",
751 [ESR_ELx_EC_HVC32] = "HVC (AArch32)",
752 [ESR_ELx_EC_SMC32] = "SMC (AArch32)",
753 [ESR_ELx_EC_SVC64] = "SVC (AArch64)",
754 [ESR_ELx_EC_HVC64] = "HVC (AArch64)",
755 [ESR_ELx_EC_SMC64] = "SMC (AArch64)",
756 [ESR_ELx_EC_SYS64] = "MSR/MRS (AArch64)",
757 [ESR_ELx_EC_SVE] = "SVE",
758 [ESR_ELx_EC_ERET] = "ERET/ERETAA/ERETAB",
759 [ESR_ELx_EC_IMP_DEF] = "EL3 IMP DEF",
760 [ESR_ELx_EC_IABT_LOW] = "IABT (lower EL)",
761 [ESR_ELx_EC_IABT_CUR] = "IABT (current EL)",
762 [ESR_ELx_EC_PC_ALIGN] = "PC Alignment",
763 [ESR_ELx_EC_DABT_LOW] = "DABT (lower EL)",
764 [ESR_ELx_EC_DABT_CUR] = "DABT (current EL)",
765 [ESR_ELx_EC_SP_ALIGN] = "SP Alignment",
766 [ESR_ELx_EC_FP_EXC32] = "FP (AArch32)",
767 [ESR_ELx_EC_FP_EXC64] = "FP (AArch64)",
768 [ESR_ELx_EC_SERROR] = "SError",
769 [ESR_ELx_EC_BREAKPT_LOW] = "Breakpoint (lower EL)",
770 [ESR_ELx_EC_BREAKPT_CUR] = "Breakpoint (current EL)",
771 [ESR_ELx_EC_SOFTSTP_LOW] = "Software Step (lower EL)",
772 [ESR_ELx_EC_SOFTSTP_CUR] = "Software Step (current EL)",
773 [ESR_ELx_EC_WATCHPT_LOW] = "Watchpoint (lower EL)",
774 [ESR_ELx_EC_WATCHPT_CUR] = "Watchpoint (current EL)",
775 [ESR_ELx_EC_BKPT32] = "BKPT (AArch32)",
776 [ESR_ELx_EC_VECTOR32] = "Vector catch (AArch32)",
777 [ESR_ELx_EC_BRK64] = "BRK (AArch64)",
780 const char *esr_get_class_string(u32 esr)
782 return esr_class_str[ESR_ELx_EC(esr)];
786 * bad_mode handles the impossible case in the exception vector. This is always
789 asmlinkage void bad_mode(struct pt_regs *regs, int reason, unsigned int esr)
793 pr_crit("Bad mode in %s handler detected on CPU%d, code 0x%08x -- %s\n",
794 handler[reason], smp_processor_id(), esr,
795 esr_get_class_string(esr));
802 * bad_el0_sync handles unexpected, but potentially recoverable synchronous
803 * exceptions taken from EL0. Unlike bad_mode, this returns.
805 asmlinkage void bad_el0_sync(struct pt_regs *regs, int reason, unsigned int esr)
807 void __user *pc = (void __user *)instruction_pointer(regs);
809 current->thread.fault_address = 0;
810 current->thread.fault_code = esr;
812 arm64_force_sig_fault(SIGILL, ILL_ILLOPC, pc,
813 "Bad EL0 synchronous exception");
816 #ifdef CONFIG_VMAP_STACK
818 DEFINE_PER_CPU(unsigned long [OVERFLOW_STACK_SIZE/sizeof(long)], overflow_stack)
821 asmlinkage void handle_bad_stack(struct pt_regs *regs)
823 unsigned long tsk_stk = (unsigned long)current->stack;
824 unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr);
825 unsigned long ovf_stk = (unsigned long)this_cpu_ptr(overflow_stack);
826 unsigned int esr = read_sysreg(esr_el1);
827 unsigned long far = read_sysreg(far_el1);
830 pr_emerg("Insufficient stack space to handle exception!");
832 pr_emerg("ESR: 0x%08x -- %s\n", esr, esr_get_class_string(esr));
833 pr_emerg("FAR: 0x%016lx\n", far);
835 pr_emerg("Task stack: [0x%016lx..0x%016lx]\n",
836 tsk_stk, tsk_stk + THREAD_SIZE);
837 pr_emerg("IRQ stack: [0x%016lx..0x%016lx]\n",
838 irq_stk, irq_stk + THREAD_SIZE);
839 pr_emerg("Overflow stack: [0x%016lx..0x%016lx]\n",
840 ovf_stk, ovf_stk + OVERFLOW_STACK_SIZE);
845 * We use nmi_panic to limit the potential for recusive overflows, and
846 * to get a better stack trace.
848 nmi_panic(NULL, "kernel stack overflow");
853 void __noreturn arm64_serror_panic(struct pt_regs *regs, u32 esr)
857 pr_crit("SError Interrupt on CPU%d, code 0x%08x -- %s\n",
858 smp_processor_id(), esr, esr_get_class_string(esr));
862 nmi_panic(regs, "Asynchronous SError Interrupt");
868 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned int esr)
870 u32 aet = arm64_ras_serror_get_severity(esr);
873 case ESR_ELx_AET_CE: /* corrected error */
874 case ESR_ELx_AET_UEO: /* restartable, not yet consumed */
876 * The CPU can make progress. We may take UEO again as
877 * a more severe error.
881 case ESR_ELx_AET_UEU: /* Uncorrected Unrecoverable */
882 case ESR_ELx_AET_UER: /* Uncorrected Recoverable */
884 * The CPU can't make progress. The exception may have
887 * Neoverse-N1 #1349291 means a non-KVM SError reported as
888 * Unrecoverable should be treated as Uncontainable. We
889 * call arm64_serror_panic() in both cases.
893 case ESR_ELx_AET_UC: /* Uncontainable or Uncategorized error */
895 /* Error has been silently propagated */
896 arm64_serror_panic(regs, esr);
900 asmlinkage void do_serror(struct pt_regs *regs, unsigned int esr)
902 const bool was_in_nmi = in_nmi();
907 /* non-RAS errors are not containable */
908 if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(regs, esr))
909 arm64_serror_panic(regs, esr);
915 asmlinkage void enter_from_user_mode(void)
917 CT_WARN_ON(ct_state() != CONTEXT_USER);
920 NOKPROBE_SYMBOL(enter_from_user_mode);
922 void __pte_error(const char *file, int line, unsigned long val)
924 pr_err("%s:%d: bad pte %016lx.\n", file, line, val);
927 void __pmd_error(const char *file, int line, unsigned long val)
929 pr_err("%s:%d: bad pmd %016lx.\n", file, line, val);
932 void __pud_error(const char *file, int line, unsigned long val)
934 pr_err("%s:%d: bad pud %016lx.\n", file, line, val);
937 void __pgd_error(const char *file, int line, unsigned long val)
939 pr_err("%s:%d: bad pgd %016lx.\n", file, line, val);
942 /* GENERIC_BUG traps */
944 int is_valid_bugaddr(unsigned long addr)
947 * bug_handler() only called for BRK #BUG_BRK_IMM.
948 * So the answer is trivial -- any spurious instances with no
949 * bug table entry will be rejected by report_bug() and passed
950 * back to the debug-monitors code and handled as a fatal
951 * unexpected debug exception.
956 static int bug_handler(struct pt_regs *regs, unsigned int esr)
958 switch (report_bug(regs->pc, regs)) {
959 case BUG_TRAP_TYPE_BUG:
960 die("Oops - BUG", regs, 0);
963 case BUG_TRAP_TYPE_WARN:
967 /* unknown/unrecognised bug trap type */
968 return DBG_HOOK_ERROR;
971 /* If thread survives, skip over the BUG instruction and continue: */
972 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
973 return DBG_HOOK_HANDLED;
976 static struct break_hook bug_break_hook = {
981 #ifdef CONFIG_KASAN_SW_TAGS
983 #define KASAN_ESR_RECOVER 0x20
984 #define KASAN_ESR_WRITE 0x10
985 #define KASAN_ESR_SIZE_MASK 0x0f
986 #define KASAN_ESR_SIZE(esr) (1 << ((esr) & KASAN_ESR_SIZE_MASK))
988 static int kasan_handler(struct pt_regs *regs, unsigned int esr)
990 bool recover = esr & KASAN_ESR_RECOVER;
991 bool write = esr & KASAN_ESR_WRITE;
992 size_t size = KASAN_ESR_SIZE(esr);
993 u64 addr = regs->regs[0];
996 kasan_report(addr, size, write, pc);
999 * The instrumentation allows to control whether we can proceed after
1000 * a crash was detected. This is done by passing the -recover flag to
1001 * the compiler. Disabling recovery allows to generate more compact
1004 * Unfortunately disabling recovery doesn't work for the kernel right
1005 * now. KASAN reporting is disabled in some contexts (for example when
1006 * the allocator accesses slab object metadata; this is controlled by
1007 * current->kasan_depth). All these accesses are detected by the tool,
1008 * even though the reports for them are not printed.
1010 * This is something that might be fixed at some point in the future.
1013 die("Oops - KASAN", regs, 0);
1015 /* If thread survives, skip over the brk instruction and continue: */
1016 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
1017 return DBG_HOOK_HANDLED;
1020 static struct break_hook kasan_break_hook = {
1021 .fn = kasan_handler,
1022 .imm = KASAN_BRK_IMM,
1023 .mask = KASAN_BRK_MASK,
1028 * Initial handler for AArch64 BRK exceptions
1029 * This handler only used until debug_traps_init().
1031 int __init early_brk64(unsigned long addr, unsigned int esr,
1032 struct pt_regs *regs)
1034 #ifdef CONFIG_KASAN_SW_TAGS
1035 unsigned int comment = esr & ESR_ELx_BRK64_ISS_COMMENT_MASK;
1037 if ((comment & ~KASAN_BRK_MASK) == KASAN_BRK_IMM)
1038 return kasan_handler(regs, esr) != DBG_HOOK_HANDLED;
1040 return bug_handler(regs, esr) != DBG_HOOK_HANDLED;
1043 /* This registration must happen early, before debug_traps_init(). */
1044 void __init trap_init(void)
1046 register_kernel_break_hook(&bug_break_hook);
1047 #ifdef CONFIG_KASAN_SW_TAGS
1048 register_kernel_break_hook(&kasan_break_hook);