1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
5 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
6 #include <linux/platform_device.h>
7 #include <linux/dma-mapping.h>
8 #include <linux/workqueue.h>
9 #include <linux/libnvdimm.h>
10 #include <linux/genalloc.h>
11 #include <linux/vmalloc.h>
12 #include <linux/device.h>
13 #include <linux/module.h>
14 #include <linux/mutex.h>
15 #include <linux/ndctl.h>
16 #include <linux/sizes.h>
17 #include <linux/list.h>
18 #include <linux/slab.h>
23 #include "nfit_test.h"
24 #include "../watermark.h"
26 #include <asm/copy_mc_test.h>
30 * Generate an NFIT table to describe the following topology:
32 * BUS0: Interleaved PMEM regions, and aliasing with BLK regions
34 * (a) (b) DIMM BLK-REGION
35 * +----------+--------------+----------+---------+
36 * +------+ | blk2.0 | pm0.0 | blk2.1 | pm1.0 | 0 region2
37 * | imc0 +--+- - - - - region0 - - - -+----------+ +
38 * +--+---+ | blk3.0 | pm0.0 | blk3.1 | pm1.0 | 1 region3
39 * | +----------+--------------v----------v v
43 * | +-------------------------^----------^ ^
44 * +--+---+ | blk4.0 | pm1.0 | 2 region4
45 * | imc1 +--+-------------------------+----------+ +
46 * +------+ | blk5.0 | pm1.0 | 3 region5
47 * +-------------------------+----------+-+-------+
51 * +--+---+ (Hotplug DIMM)
52 * | +----------------------------------------------+
53 * +--+---+ | blk6.0/pm7.0 | 4 region6/7
54 * | imc0 +--+----------------------------------------------+
58 * *) In this layout we have four dimms and two memory controllers in one
59 * socket. Each unique interface (BLK or PMEM) to DPA space
60 * is identified by a region device with a dynamically assigned id.
62 * *) The first portion of dimm0 and dimm1 are interleaved as REGION0.
63 * A single PMEM namespace "pm0.0" is created using half of the
64 * REGION0 SPA-range. REGION0 spans dimm0 and dimm1. PMEM namespace
65 * allocate from from the bottom of a region. The unallocated
66 * portion of REGION0 aliases with REGION2 and REGION3. That
67 * unallacted capacity is reclaimed as BLK namespaces ("blk2.0" and
68 * "blk3.0") starting at the base of each DIMM to offset (a) in those
69 * DIMMs. "pm0.0", "blk2.0" and "blk3.0" are free-form readable
70 * names that can be assigned to a namespace.
72 * *) In the last portion of dimm0 and dimm1 we have an interleaved
73 * SPA range, REGION1, that spans those two dimms as well as dimm2
74 * and dimm3. Some of REGION1 allocated to a PMEM namespace named
75 * "pm1.0" the rest is reclaimed in 4 BLK namespaces (for each
76 * dimm in the interleave set), "blk2.1", "blk3.1", "blk4.0", and
79 * *) The portion of dimm2 and dimm3 that do not participate in the
80 * REGION1 interleaved SPA range (i.e. the DPA address below offset
81 * (b) are also included in the "blk4.0" and "blk5.0" namespaces.
82 * Note, that BLK namespaces need not be contiguous in DPA-space, and
83 * can consume aliased capacity from multiple interleave sets.
85 * BUS1: Legacy NVDIMM (single contiguous range)
88 * +---------------------+
89 * |---------------------|
91 * |---------------------|
92 * +---------------------+
94 * *) A NFIT-table may describe a simple system-physical-address range
95 * with no BLK aliasing. This type of region may optionally
96 * reference an NVDIMM.
103 NUM_SPA = NUM_PM + NUM_DCR + NUM_BDW,
104 NUM_MEM = NUM_DCR + NUM_BDW + 2 /* spa0 iset */
105 + 4 /* spa1 iset */ + 1 /* spa11 iset */,
107 LABEL_SIZE = SZ_128K,
108 SPA_VCD_SIZE = SZ_4M,
109 SPA0_SIZE = DIMM_SIZE,
110 SPA1_SIZE = DIMM_SIZE*2,
111 SPA2_SIZE = DIMM_SIZE,
114 NUM_NFITS = 2, /* permit testing multiple NFITs per system */
117 struct nfit_test_dcr {
120 __u8 aperature[BDW_SIZE];
123 #define NFIT_DIMM_HANDLE(node, socket, imc, chan, dimm) \
124 (((node & 0xfff) << 16) | ((socket & 0xf) << 12) \
125 | ((imc & 0xf) << 8) | ((chan & 0xf) << 4) | (dimm & 0xf))
127 static u32 handle[] = {
128 [0] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 0),
129 [1] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 1),
130 [2] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 0),
131 [3] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 1),
132 [4] = NFIT_DIMM_HANDLE(0, 1, 0, 0, 0),
133 [5] = NFIT_DIMM_HANDLE(1, 0, 0, 0, 0),
134 [6] = NFIT_DIMM_HANDLE(1, 0, 0, 0, 1),
137 static unsigned long dimm_fail_cmd_flags[ARRAY_SIZE(handle)];
138 static int dimm_fail_cmd_code[ARRAY_SIZE(handle)];
139 struct nfit_test_sec {
144 u8 master_passphrase[32];
145 u64 overwrite_end_time;
146 } dimm_sec_info[NUM_DCR];
148 static const struct nd_intel_smart smart_def = {
149 .flags = ND_INTEL_SMART_HEALTH_VALID
150 | ND_INTEL_SMART_SPARES_VALID
151 | ND_INTEL_SMART_ALARM_VALID
152 | ND_INTEL_SMART_USED_VALID
153 | ND_INTEL_SMART_SHUTDOWN_VALID
154 | ND_INTEL_SMART_SHUTDOWN_COUNT_VALID
155 | ND_INTEL_SMART_MTEMP_VALID
156 | ND_INTEL_SMART_CTEMP_VALID,
157 .health = ND_INTEL_SMART_NON_CRITICAL_HEALTH,
158 .media_temperature = 23 * 16,
159 .ctrl_temperature = 25 * 16,
160 .pmic_temperature = 40 * 16,
162 .alarm_flags = ND_INTEL_SMART_SPARE_TRIP
163 | ND_INTEL_SMART_TEMP_TRIP,
167 .shutdown_count = 42,
171 struct nfit_test_fw {
172 enum intel_fw_update_state state;
178 bool missed_activate;
179 unsigned long last_activate;
183 struct acpi_nfit_desc acpi_desc;
184 struct platform_device pdev;
185 struct list_head resources;
194 dma_addr_t *dimm_dma;
196 dma_addr_t *flush_dma;
198 dma_addr_t *label_dma;
200 dma_addr_t *spa_set_dma;
201 struct nfit_test_dcr **dcr;
203 int (*alloc)(struct nfit_test *t);
204 void (*setup)(struct nfit_test *t);
206 union acpi_object **_fit;
209 struct nd_cmd_ars_status *ars_status;
210 unsigned long deadline;
213 struct device *dimm_dev[ARRAY_SIZE(handle)];
214 struct nd_intel_smart *smart;
215 struct nd_intel_smart_threshold *smart_threshold;
216 struct badrange badrange;
217 struct work_struct work;
218 struct nfit_test_fw *fw;
221 static struct workqueue_struct *nfit_wq;
223 static struct gen_pool *nfit_pool;
225 static const char zero_key[NVDIMM_PASSPHRASE_LEN];
227 static struct nfit_test *to_nfit_test(struct device *dev)
229 struct platform_device *pdev = to_platform_device(dev);
231 return container_of(pdev, struct nfit_test, pdev);
234 static int nd_intel_test_get_fw_info(struct nfit_test *t,
235 struct nd_intel_fw_info *nd_cmd, unsigned int buf_len,
238 struct device *dev = &t->pdev.dev;
239 struct nfit_test_fw *fw = &t->fw[idx];
241 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p, buf_len: %u, idx: %d\n",
242 __func__, t, nd_cmd, buf_len, idx);
244 if (buf_len < sizeof(*nd_cmd))
248 nd_cmd->storage_size = INTEL_FW_STORAGE_SIZE;
249 nd_cmd->max_send_len = INTEL_FW_MAX_SEND_LEN;
250 nd_cmd->query_interval = INTEL_FW_QUERY_INTERVAL;
251 nd_cmd->max_query_time = INTEL_FW_QUERY_MAX_TIME;
252 nd_cmd->update_cap = 0;
253 nd_cmd->fis_version = INTEL_FW_FIS_VERSION;
254 nd_cmd->run_version = 0;
255 nd_cmd->updated_version = fw->version;
260 static int nd_intel_test_start_update(struct nfit_test *t,
261 struct nd_intel_fw_start *nd_cmd, unsigned int buf_len,
264 struct device *dev = &t->pdev.dev;
265 struct nfit_test_fw *fw = &t->fw[idx];
267 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n",
268 __func__, t, nd_cmd, buf_len, idx);
270 if (buf_len < sizeof(*nd_cmd))
273 if (fw->state != FW_STATE_NEW) {
274 /* extended status, FW update in progress */
275 nd_cmd->status = 0x10007;
279 fw->state = FW_STATE_IN_PROGRESS;
281 fw->size_received = 0;
283 nd_cmd->context = fw->context;
285 dev_dbg(dev, "%s: context issued: %#x\n", __func__, nd_cmd->context);
290 static int nd_intel_test_send_data(struct nfit_test *t,
291 struct nd_intel_fw_send_data *nd_cmd, unsigned int buf_len,
294 struct device *dev = &t->pdev.dev;
295 struct nfit_test_fw *fw = &t->fw[idx];
296 u32 *status = (u32 *)&nd_cmd->data[nd_cmd->length];
298 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n",
299 __func__, t, nd_cmd, buf_len, idx);
301 if (buf_len < sizeof(*nd_cmd))
305 dev_dbg(dev, "%s: cmd->status: %#x\n", __func__, *status);
306 dev_dbg(dev, "%s: cmd->data[0]: %#x\n", __func__, nd_cmd->data[0]);
307 dev_dbg(dev, "%s: cmd->data[%u]: %#x\n", __func__, nd_cmd->length-1,
308 nd_cmd->data[nd_cmd->length-1]);
310 if (fw->state != FW_STATE_IN_PROGRESS) {
311 dev_dbg(dev, "%s: not in IN_PROGRESS state\n", __func__);
316 if (nd_cmd->context != fw->context) {
317 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n",
318 __func__, nd_cmd->context, fw->context);
324 * check offset + len > size of fw storage
325 * check length is > max send length
327 if (nd_cmd->offset + nd_cmd->length > INTEL_FW_STORAGE_SIZE ||
328 nd_cmd->length > INTEL_FW_MAX_SEND_LEN) {
330 dev_dbg(dev, "%s: buffer boundary violation\n", __func__);
334 fw->size_received += nd_cmd->length;
335 dev_dbg(dev, "%s: copying %u bytes, %u bytes so far\n",
336 __func__, nd_cmd->length, fw->size_received);
341 static int nd_intel_test_finish_fw(struct nfit_test *t,
342 struct nd_intel_fw_finish_update *nd_cmd,
343 unsigned int buf_len, int idx)
345 struct device *dev = &t->pdev.dev;
346 struct nfit_test_fw *fw = &t->fw[idx];
348 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n",
349 __func__, t, nd_cmd, buf_len, idx);
351 if (fw->state == FW_STATE_UPDATED) {
352 /* update already done, need activation */
353 nd_cmd->status = 0x20007;
357 dev_dbg(dev, "%s: context: %#x ctrl_flags: %#x\n",
358 __func__, nd_cmd->context, nd_cmd->ctrl_flags);
360 switch (nd_cmd->ctrl_flags) {
362 if (nd_cmd->context != fw->context) {
363 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n",
364 __func__, nd_cmd->context,
366 nd_cmd->status = 0x10007;
370 fw->state = FW_STATE_VERIFY;
371 /* set 1 second of time for firmware "update" */
372 fw->end_time = jiffies + HZ;
376 fw->size_received = 0;
377 /* successfully aborted status */
378 nd_cmd->status = 0x40007;
379 fw->state = FW_STATE_NEW;
380 dev_dbg(dev, "%s: abort successful\n", __func__);
383 default: /* bad control flag */
384 dev_warn(dev, "%s: unknown control flag: %#x\n",
385 __func__, nd_cmd->ctrl_flags);
392 static int nd_intel_test_finish_query(struct nfit_test *t,
393 struct nd_intel_fw_finish_query *nd_cmd,
394 unsigned int buf_len, int idx)
396 struct device *dev = &t->pdev.dev;
397 struct nfit_test_fw *fw = &t->fw[idx];
399 dev_dbg(dev, "%s(nfit_test: %p nd_cmd: %p buf_len: %u idx: %d)\n",
400 __func__, t, nd_cmd, buf_len, idx);
402 if (buf_len < sizeof(*nd_cmd))
405 if (nd_cmd->context != fw->context) {
406 dev_dbg(dev, "%s: incorrect context: in: %#x correct: %#x\n",
407 __func__, nd_cmd->context, fw->context);
408 nd_cmd->status = 0x10007;
412 dev_dbg(dev, "%s context: %#x\n", __func__, nd_cmd->context);
416 nd_cmd->updated_fw_rev = 0;
418 dev_dbg(dev, "%s: new state\n", __func__);
421 case FW_STATE_IN_PROGRESS:
422 /* sequencing error */
423 nd_cmd->status = 0x40007;
424 nd_cmd->updated_fw_rev = 0;
425 dev_dbg(dev, "%s: sequence error\n", __func__);
428 case FW_STATE_VERIFY:
429 if (time_is_after_jiffies64(fw->end_time)) {
430 nd_cmd->updated_fw_rev = 0;
431 nd_cmd->status = 0x20007;
432 dev_dbg(dev, "%s: still verifying\n", __func__);
435 dev_dbg(dev, "%s: transition out verify\n", __func__);
436 fw->state = FW_STATE_UPDATED;
437 fw->missed_activate = false;
439 case FW_STATE_UPDATED:
441 /* bogus test version */
442 fw->version = nd_cmd->updated_fw_rev =
443 INTEL_FW_FAKE_VERSION;
444 dev_dbg(dev, "%s: updated\n", __func__);
447 default: /* we should never get here */
454 static int nfit_test_cmd_get_config_size(struct nd_cmd_get_config_size *nd_cmd,
455 unsigned int buf_len)
457 if (buf_len < sizeof(*nd_cmd))
461 nd_cmd->config_size = LABEL_SIZE;
462 nd_cmd->max_xfer = SZ_4K;
467 static int nfit_test_cmd_get_config_data(struct nd_cmd_get_config_data_hdr
468 *nd_cmd, unsigned int buf_len, void *label)
470 unsigned int len, offset = nd_cmd->in_offset;
473 if (buf_len < sizeof(*nd_cmd))
475 if (offset >= LABEL_SIZE)
477 if (nd_cmd->in_length + sizeof(*nd_cmd) > buf_len)
481 len = min(nd_cmd->in_length, LABEL_SIZE - offset);
482 memcpy(nd_cmd->out_buf, label + offset, len);
483 rc = buf_len - sizeof(*nd_cmd) - len;
488 static int nfit_test_cmd_set_config_data(struct nd_cmd_set_config_hdr *nd_cmd,
489 unsigned int buf_len, void *label)
491 unsigned int len, offset = nd_cmd->in_offset;
495 if (buf_len < sizeof(*nd_cmd))
497 if (offset >= LABEL_SIZE)
499 if (nd_cmd->in_length + sizeof(*nd_cmd) + 4 > buf_len)
502 status = (void *)nd_cmd + nd_cmd->in_length + sizeof(*nd_cmd);
504 len = min(nd_cmd->in_length, LABEL_SIZE - offset);
505 memcpy(label + offset, nd_cmd->in_buf, len);
506 rc = buf_len - sizeof(*nd_cmd) - (len + 4);
511 #define NFIT_TEST_CLEAR_ERR_UNIT 256
513 static int nfit_test_cmd_ars_cap(struct nd_cmd_ars_cap *nd_cmd,
514 unsigned int buf_len)
518 if (buf_len < sizeof(*nd_cmd))
521 /* for testing, only store up to n records that fit within 4k */
522 ars_recs = SZ_4K / sizeof(struct nd_ars_record);
524 nd_cmd->max_ars_out = sizeof(struct nd_cmd_ars_status)
525 + ars_recs * sizeof(struct nd_ars_record);
526 nd_cmd->status = (ND_ARS_PERSISTENT | ND_ARS_VOLATILE) << 16;
527 nd_cmd->clear_err_unit = NFIT_TEST_CLEAR_ERR_UNIT;
532 static void post_ars_status(struct ars_state *ars_state,
533 struct badrange *badrange, u64 addr, u64 len)
535 struct nd_cmd_ars_status *ars_status;
536 struct nd_ars_record *ars_record;
537 struct badrange_entry *be;
538 u64 end = addr + len - 1;
541 ars_state->deadline = jiffies + 1*HZ;
542 ars_status = ars_state->ars_status;
543 ars_status->status = 0;
544 ars_status->address = addr;
545 ars_status->length = len;
546 ars_status->type = ND_ARS_PERSISTENT;
548 spin_lock(&badrange->lock);
549 list_for_each_entry(be, &badrange->list, list) {
550 u64 be_end = be->start + be->length - 1;
553 /* skip entries outside the range */
554 if (be_end < addr || be->start > end)
557 rstart = (be->start < addr) ? addr : be->start;
558 rend = (be_end < end) ? be_end : end;
559 ars_record = &ars_status->records[i];
560 ars_record->handle = 0;
561 ars_record->err_address = rstart;
562 ars_record->length = rend - rstart + 1;
565 spin_unlock(&badrange->lock);
566 ars_status->num_records = i;
567 ars_status->out_length = sizeof(struct nd_cmd_ars_status)
568 + i * sizeof(struct nd_ars_record);
571 static int nfit_test_cmd_ars_start(struct nfit_test *t,
572 struct ars_state *ars_state,
573 struct nd_cmd_ars_start *ars_start, unsigned int buf_len,
576 if (buf_len < sizeof(*ars_start))
579 spin_lock(&ars_state->lock);
580 if (time_before(jiffies, ars_state->deadline)) {
581 ars_start->status = NFIT_ARS_START_BUSY;
584 ars_start->status = 0;
585 ars_start->scrub_time = 1;
586 post_ars_status(ars_state, &t->badrange, ars_start->address,
590 spin_unlock(&ars_state->lock);
595 static int nfit_test_cmd_ars_status(struct ars_state *ars_state,
596 struct nd_cmd_ars_status *ars_status, unsigned int buf_len,
599 if (buf_len < ars_state->ars_status->out_length)
602 spin_lock(&ars_state->lock);
603 if (time_before(jiffies, ars_state->deadline)) {
604 memset(ars_status, 0, buf_len);
605 ars_status->status = NFIT_ARS_STATUS_BUSY;
606 ars_status->out_length = sizeof(*ars_status);
609 memcpy(ars_status, ars_state->ars_status,
610 ars_state->ars_status->out_length);
613 spin_unlock(&ars_state->lock);
617 static int nfit_test_cmd_clear_error(struct nfit_test *t,
618 struct nd_cmd_clear_error *clear_err,
619 unsigned int buf_len, int *cmd_rc)
621 const u64 mask = NFIT_TEST_CLEAR_ERR_UNIT - 1;
622 if (buf_len < sizeof(*clear_err))
625 if ((clear_err->address & mask) || (clear_err->length & mask))
628 badrange_forget(&t->badrange, clear_err->address, clear_err->length);
629 clear_err->status = 0;
630 clear_err->cleared = clear_err->length;
635 struct region_search_spa {
637 struct nd_region *region;
640 static int is_region_device(struct device *dev)
642 return !strncmp(dev->kobj.name, "region", 6);
645 static int nfit_test_search_region_spa(struct device *dev, void *data)
647 struct region_search_spa *ctx = data;
648 struct nd_region *nd_region;
649 resource_size_t ndr_end;
651 if (!is_region_device(dev))
654 nd_region = to_nd_region(dev);
655 ndr_end = nd_region->ndr_start + nd_region->ndr_size;
657 if (ctx->addr >= nd_region->ndr_start && ctx->addr < ndr_end) {
658 ctx->region = nd_region;
665 static int nfit_test_search_spa(struct nvdimm_bus *bus,
666 struct nd_cmd_translate_spa *spa)
669 struct nd_region *nd_region = NULL;
670 struct nvdimm *nvdimm = NULL;
671 struct nd_mapping *nd_mapping = NULL;
672 struct region_search_spa ctx = {
678 ret = device_for_each_child(&bus->dev, &ctx,
679 nfit_test_search_region_spa);
684 nd_region = ctx.region;
686 dpa = ctx.addr - nd_region->ndr_start;
689 * last dimm is selected for test
691 nd_mapping = &nd_region->mapping[nd_region->ndr_mappings - 1];
692 nvdimm = nd_mapping->nvdimm;
694 spa->devices[0].nfit_device_handle = handle[nvdimm->id];
695 spa->num_nvdimms = 1;
696 spa->devices[0].dpa = dpa;
701 static int nfit_test_cmd_translate_spa(struct nvdimm_bus *bus,
702 struct nd_cmd_translate_spa *spa, unsigned int buf_len)
704 if (buf_len < spa->translate_length)
707 if (nfit_test_search_spa(bus, spa) < 0 || !spa->num_nvdimms)
713 static int nfit_test_cmd_smart(struct nd_intel_smart *smart, unsigned int buf_len,
714 struct nd_intel_smart *smart_data)
716 if (buf_len < sizeof(*smart))
718 memcpy(smart, smart_data, sizeof(*smart));
722 static int nfit_test_cmd_smart_threshold(
723 struct nd_intel_smart_threshold *out,
724 unsigned int buf_len,
725 struct nd_intel_smart_threshold *smart_t)
727 if (buf_len < sizeof(*smart_t))
729 memcpy(out, smart_t, sizeof(*smart_t));
733 static void smart_notify(struct device *bus_dev,
734 struct device *dimm_dev, struct nd_intel_smart *smart,
735 struct nd_intel_smart_threshold *thresh)
737 dev_dbg(dimm_dev, "%s: alarm: %#x spares: %d (%d) mtemp: %d (%d) ctemp: %d (%d)\n",
738 __func__, thresh->alarm_control, thresh->spares,
739 smart->spares, thresh->media_temperature,
740 smart->media_temperature, thresh->ctrl_temperature,
741 smart->ctrl_temperature);
742 if (((thresh->alarm_control & ND_INTEL_SMART_SPARE_TRIP)
745 || ((thresh->alarm_control & ND_INTEL_SMART_TEMP_TRIP)
746 && smart->media_temperature
747 >= thresh->media_temperature)
748 || ((thresh->alarm_control & ND_INTEL_SMART_CTEMP_TRIP)
749 && smart->ctrl_temperature
750 >= thresh->ctrl_temperature)
751 || (smart->health != ND_INTEL_SMART_NON_CRITICAL_HEALTH)
752 || (smart->shutdown_state != 0)) {
753 device_lock(bus_dev);
754 __acpi_nvdimm_notify(dimm_dev, 0x81);
755 device_unlock(bus_dev);
759 static int nfit_test_cmd_smart_set_threshold(
760 struct nd_intel_smart_set_threshold *in,
761 unsigned int buf_len,
762 struct nd_intel_smart_threshold *thresh,
763 struct nd_intel_smart *smart,
764 struct device *bus_dev, struct device *dimm_dev)
768 size = sizeof(*in) - 4;
771 memcpy(thresh->data, in, size);
773 smart_notify(bus_dev, dimm_dev, smart, thresh);
778 static int nfit_test_cmd_smart_inject(
779 struct nd_intel_smart_inject *inj,
780 unsigned int buf_len,
781 struct nd_intel_smart_threshold *thresh,
782 struct nd_intel_smart *smart,
783 struct device *bus_dev, struct device *dimm_dev)
785 if (buf_len != sizeof(*inj))
788 if (inj->flags & ND_INTEL_SMART_INJECT_MTEMP) {
789 if (inj->mtemp_enable)
790 smart->media_temperature = inj->media_temperature;
792 smart->media_temperature = smart_def.media_temperature;
794 if (inj->flags & ND_INTEL_SMART_INJECT_SPARE) {
795 if (inj->spare_enable)
796 smart->spares = inj->spares;
798 smart->spares = smart_def.spares;
800 if (inj->flags & ND_INTEL_SMART_INJECT_FATAL) {
801 if (inj->fatal_enable)
802 smart->health = ND_INTEL_SMART_FATAL_HEALTH;
804 smart->health = ND_INTEL_SMART_NON_CRITICAL_HEALTH;
806 if (inj->flags & ND_INTEL_SMART_INJECT_SHUTDOWN) {
807 if (inj->unsafe_shutdown_enable) {
808 smart->shutdown_state = 1;
809 smart->shutdown_count++;
811 smart->shutdown_state = 0;
814 smart_notify(bus_dev, dimm_dev, smart, thresh);
819 static void uc_error_notify(struct work_struct *work)
821 struct nfit_test *t = container_of(work, typeof(*t), work);
823 __acpi_nfit_notify(&t->pdev.dev, t, NFIT_NOTIFY_UC_MEMORY_ERROR);
826 static int nfit_test_cmd_ars_error_inject(struct nfit_test *t,
827 struct nd_cmd_ars_err_inj *err_inj, unsigned int buf_len)
831 if (buf_len != sizeof(*err_inj)) {
836 if (err_inj->err_inj_spa_range_length <= 0) {
841 rc = badrange_add(&t->badrange, err_inj->err_inj_spa_range_base,
842 err_inj->err_inj_spa_range_length);
846 if (err_inj->err_inj_options & (1 << ND_ARS_ERR_INJ_OPT_NOTIFY))
847 queue_work(nfit_wq, &t->work);
853 err_inj->status = NFIT_ARS_INJECT_INVALID;
857 static int nfit_test_cmd_ars_inject_clear(struct nfit_test *t,
858 struct nd_cmd_ars_err_inj_clr *err_clr, unsigned int buf_len)
862 if (buf_len != sizeof(*err_clr)) {
867 if (err_clr->err_inj_clr_spa_range_length <= 0) {
872 badrange_forget(&t->badrange, err_clr->err_inj_clr_spa_range_base,
873 err_clr->err_inj_clr_spa_range_length);
879 err_clr->status = NFIT_ARS_INJECT_INVALID;
883 static int nfit_test_cmd_ars_inject_status(struct nfit_test *t,
884 struct nd_cmd_ars_err_inj_stat *err_stat,
885 unsigned int buf_len)
887 struct badrange_entry *be;
888 int max = SZ_4K / sizeof(struct nd_error_stat_query_record);
891 err_stat->status = 0;
892 spin_lock(&t->badrange.lock);
893 list_for_each_entry(be, &t->badrange.list, list) {
894 err_stat->record[i].err_inj_stat_spa_range_base = be->start;
895 err_stat->record[i].err_inj_stat_spa_range_length = be->length;
900 spin_unlock(&t->badrange.lock);
901 err_stat->inj_err_rec_count = i;
906 static int nd_intel_test_cmd_set_lss_status(struct nfit_test *t,
907 struct nd_intel_lss *nd_cmd, unsigned int buf_len)
909 struct device *dev = &t->pdev.dev;
911 if (buf_len < sizeof(*nd_cmd))
914 switch (nd_cmd->enable) {
917 dev_dbg(dev, "%s: Latch System Shutdown Status disabled\n",
922 dev_dbg(dev, "%s: Latch System Shutdown Status enabled\n",
926 dev_warn(dev, "Unknown enable value: %#x\n", nd_cmd->enable);
927 nd_cmd->status = 0x3;
935 static int override_return_code(int dimm, unsigned int func, int rc)
937 if ((1 << func) & dimm_fail_cmd_flags[dimm]) {
938 if (dimm_fail_cmd_code[dimm])
939 return dimm_fail_cmd_code[dimm];
945 static int nd_intel_test_cmd_security_status(struct nfit_test *t,
946 struct nd_intel_get_security_state *nd_cmd,
947 unsigned int buf_len, int dimm)
949 struct device *dev = &t->pdev.dev;
950 struct nfit_test_sec *sec = &dimm_sec_info[dimm];
953 nd_cmd->state = sec->state;
954 nd_cmd->extended_state = sec->ext_state;
955 dev_dbg(dev, "security state (%#x) returned\n", nd_cmd->state);
960 static int nd_intel_test_cmd_unlock_unit(struct nfit_test *t,
961 struct nd_intel_unlock_unit *nd_cmd,
962 unsigned int buf_len, int dimm)
964 struct device *dev = &t->pdev.dev;
965 struct nfit_test_sec *sec = &dimm_sec_info[dimm];
967 if (!(sec->state & ND_INTEL_SEC_STATE_LOCKED) ||
968 (sec->state & ND_INTEL_SEC_STATE_FROZEN)) {
969 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
970 dev_dbg(dev, "unlock unit: invalid state: %#x\n",
972 } else if (memcmp(nd_cmd->passphrase, sec->passphrase,
973 ND_INTEL_PASSPHRASE_SIZE) != 0) {
974 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
975 dev_dbg(dev, "unlock unit: invalid passphrase\n");
978 sec->state = ND_INTEL_SEC_STATE_ENABLED;
979 dev_dbg(dev, "Unit unlocked\n");
982 dev_dbg(dev, "unlocking status returned: %#x\n", nd_cmd->status);
986 static int nd_intel_test_cmd_set_pass(struct nfit_test *t,
987 struct nd_intel_set_passphrase *nd_cmd,
988 unsigned int buf_len, int dimm)
990 struct device *dev = &t->pdev.dev;
991 struct nfit_test_sec *sec = &dimm_sec_info[dimm];
993 if (sec->state & ND_INTEL_SEC_STATE_FROZEN) {
994 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
995 dev_dbg(dev, "set passphrase: wrong security state\n");
996 } else if (memcmp(nd_cmd->old_pass, sec->passphrase,
997 ND_INTEL_PASSPHRASE_SIZE) != 0) {
998 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
999 dev_dbg(dev, "set passphrase: wrong passphrase\n");
1001 memcpy(sec->passphrase, nd_cmd->new_pass,
1002 ND_INTEL_PASSPHRASE_SIZE);
1003 sec->state |= ND_INTEL_SEC_STATE_ENABLED;
1005 dev_dbg(dev, "passphrase updated\n");
1011 static int nd_intel_test_cmd_freeze_lock(struct nfit_test *t,
1012 struct nd_intel_freeze_lock *nd_cmd,
1013 unsigned int buf_len, int dimm)
1015 struct device *dev = &t->pdev.dev;
1016 struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1018 if (!(sec->state & ND_INTEL_SEC_STATE_ENABLED)) {
1019 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
1020 dev_dbg(dev, "freeze lock: wrong security state\n");
1022 sec->state |= ND_INTEL_SEC_STATE_FROZEN;
1024 dev_dbg(dev, "security frozen\n");
1030 static int nd_intel_test_cmd_disable_pass(struct nfit_test *t,
1031 struct nd_intel_disable_passphrase *nd_cmd,
1032 unsigned int buf_len, int dimm)
1034 struct device *dev = &t->pdev.dev;
1035 struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1037 if (!(sec->state & ND_INTEL_SEC_STATE_ENABLED) ||
1038 (sec->state & ND_INTEL_SEC_STATE_FROZEN)) {
1039 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
1040 dev_dbg(dev, "disable passphrase: wrong security state\n");
1041 } else if (memcmp(nd_cmd->passphrase, sec->passphrase,
1042 ND_INTEL_PASSPHRASE_SIZE) != 0) {
1043 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
1044 dev_dbg(dev, "disable passphrase: wrong passphrase\n");
1046 memset(sec->passphrase, 0, ND_INTEL_PASSPHRASE_SIZE);
1048 dev_dbg(dev, "disable passphrase: done\n");
1054 static int nd_intel_test_cmd_secure_erase(struct nfit_test *t,
1055 struct nd_intel_secure_erase *nd_cmd,
1056 unsigned int buf_len, int dimm)
1058 struct device *dev = &t->pdev.dev;
1059 struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1061 if (sec->state & ND_INTEL_SEC_STATE_FROZEN) {
1062 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
1063 dev_dbg(dev, "secure erase: wrong security state\n");
1064 } else if (memcmp(nd_cmd->passphrase, sec->passphrase,
1065 ND_INTEL_PASSPHRASE_SIZE) != 0) {
1066 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
1067 dev_dbg(dev, "secure erase: wrong passphrase\n");
1069 if (!(sec->state & ND_INTEL_SEC_STATE_ENABLED)
1070 && (memcmp(nd_cmd->passphrase, zero_key,
1071 ND_INTEL_PASSPHRASE_SIZE) != 0)) {
1072 dev_dbg(dev, "invalid zero key\n");
1075 memset(sec->passphrase, 0, ND_INTEL_PASSPHRASE_SIZE);
1076 memset(sec->master_passphrase, 0, ND_INTEL_PASSPHRASE_SIZE);
1078 sec->ext_state = ND_INTEL_SEC_ESTATE_ENABLED;
1079 dev_dbg(dev, "secure erase: done\n");
1085 static int nd_intel_test_cmd_overwrite(struct nfit_test *t,
1086 struct nd_intel_overwrite *nd_cmd,
1087 unsigned int buf_len, int dimm)
1089 struct device *dev = &t->pdev.dev;
1090 struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1092 if ((sec->state & ND_INTEL_SEC_STATE_ENABLED) &&
1093 memcmp(nd_cmd->passphrase, sec->passphrase,
1094 ND_INTEL_PASSPHRASE_SIZE) != 0) {
1095 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
1096 dev_dbg(dev, "overwrite: wrong passphrase\n");
1100 sec->old_state = sec->state;
1101 sec->state = ND_INTEL_SEC_STATE_OVERWRITE;
1102 dev_dbg(dev, "overwrite progressing.\n");
1103 sec->overwrite_end_time = get_jiffies_64() + 5 * HZ;
1108 static int nd_intel_test_cmd_query_overwrite(struct nfit_test *t,
1109 struct nd_intel_query_overwrite *nd_cmd,
1110 unsigned int buf_len, int dimm)
1112 struct device *dev = &t->pdev.dev;
1113 struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1115 if (!(sec->state & ND_INTEL_SEC_STATE_OVERWRITE)) {
1116 nd_cmd->status = ND_INTEL_STATUS_OQUERY_SEQUENCE_ERR;
1120 if (time_is_before_jiffies64(sec->overwrite_end_time)) {
1121 sec->overwrite_end_time = 0;
1122 sec->state = sec->old_state;
1124 sec->ext_state = ND_INTEL_SEC_ESTATE_ENABLED;
1125 dev_dbg(dev, "overwrite is complete\n");
1127 nd_cmd->status = ND_INTEL_STATUS_OQUERY_INPROGRESS;
1131 static int nd_intel_test_cmd_master_set_pass(struct nfit_test *t,
1132 struct nd_intel_set_master_passphrase *nd_cmd,
1133 unsigned int buf_len, int dimm)
1135 struct device *dev = &t->pdev.dev;
1136 struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1138 if (!(sec->ext_state & ND_INTEL_SEC_ESTATE_ENABLED)) {
1139 nd_cmd->status = ND_INTEL_STATUS_NOT_SUPPORTED;
1140 dev_dbg(dev, "master set passphrase: in wrong state\n");
1141 } else if (sec->ext_state & ND_INTEL_SEC_ESTATE_PLIMIT) {
1142 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
1143 dev_dbg(dev, "master set passphrase: in wrong security state\n");
1144 } else if (memcmp(nd_cmd->old_pass, sec->master_passphrase,
1145 ND_INTEL_PASSPHRASE_SIZE) != 0) {
1146 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
1147 dev_dbg(dev, "master set passphrase: wrong passphrase\n");
1149 memcpy(sec->master_passphrase, nd_cmd->new_pass,
1150 ND_INTEL_PASSPHRASE_SIZE);
1151 sec->ext_state = ND_INTEL_SEC_ESTATE_ENABLED;
1152 dev_dbg(dev, "master passphrase: updated\n");
1158 static int nd_intel_test_cmd_master_secure_erase(struct nfit_test *t,
1159 struct nd_intel_master_secure_erase *nd_cmd,
1160 unsigned int buf_len, int dimm)
1162 struct device *dev = &t->pdev.dev;
1163 struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1165 if (!(sec->ext_state & ND_INTEL_SEC_ESTATE_ENABLED)) {
1166 nd_cmd->status = ND_INTEL_STATUS_NOT_SUPPORTED;
1167 dev_dbg(dev, "master secure erase: in wrong state\n");
1168 } else if (sec->ext_state & ND_INTEL_SEC_ESTATE_PLIMIT) {
1169 nd_cmd->status = ND_INTEL_STATUS_INVALID_STATE;
1170 dev_dbg(dev, "master secure erase: in wrong security state\n");
1171 } else if (memcmp(nd_cmd->passphrase, sec->master_passphrase,
1172 ND_INTEL_PASSPHRASE_SIZE) != 0) {
1173 nd_cmd->status = ND_INTEL_STATUS_INVALID_PASS;
1174 dev_dbg(dev, "master secure erase: wrong passphrase\n");
1176 /* we do not erase master state passphrase ever */
1177 sec->ext_state = ND_INTEL_SEC_ESTATE_ENABLED;
1178 memset(sec->passphrase, 0, ND_INTEL_PASSPHRASE_SIZE);
1180 dev_dbg(dev, "master secure erase: done\n");
1186 static unsigned long last_activate;
1188 static int nvdimm_bus_intel_fw_activate_businfo(struct nfit_test *t,
1189 struct nd_intel_bus_fw_activate_businfo *nd_cmd,
1190 unsigned int buf_len)
1196 for (i = 0; i < NUM_DCR; i++) {
1197 struct nfit_test_fw *fw = &t->fw[i];
1204 * Emulate 3 second activation max, and 1 second incremental
1205 * quiesce time per dimm requiring multiple activates to get all
1209 state = ND_INTEL_FWA_ARMED;
1210 else if (!last_activate || time_after(jiffies, last_activate + 3 * HZ))
1211 state = ND_INTEL_FWA_IDLE;
1213 state = ND_INTEL_FWA_BUSY;
1215 tmo = armed * USEC_PER_SEC;
1216 *nd_cmd = (struct nd_intel_bus_fw_activate_businfo) {
1217 .capability = ND_INTEL_BUS_FWA_CAP_FWQUIESCE
1218 | ND_INTEL_BUS_FWA_CAP_OSQUIESCE
1219 | ND_INTEL_BUS_FWA_CAP_RESET,
1221 .activate_tmo = tmo,
1222 .cpu_quiesce_tmo = tmo,
1223 .io_quiesce_tmo = tmo,
1224 .max_quiesce_tmo = 3 * USEC_PER_SEC,
1230 static int nvdimm_bus_intel_fw_activate(struct nfit_test *t,
1231 struct nd_intel_bus_fw_activate *nd_cmd,
1232 unsigned int buf_len)
1234 struct nd_intel_bus_fw_activate_businfo info;
1238 nvdimm_bus_intel_fw_activate_businfo(t, &info, sizeof(info));
1239 if (info.state == ND_INTEL_FWA_BUSY)
1240 status = ND_INTEL_BUS_FWA_STATUS_BUSY;
1241 else if (info.activate_tmo > info.max_quiesce_tmo)
1242 status = ND_INTEL_BUS_FWA_STATUS_TMO;
1243 else if (info.state == ND_INTEL_FWA_IDLE)
1244 status = ND_INTEL_BUS_FWA_STATUS_NOARM;
1246 dev_dbg(&t->pdev.dev, "status: %d\n", status);
1247 nd_cmd->status = status;
1248 if (status && status != ND_INTEL_BUS_FWA_STATUS_TMO)
1251 last_activate = jiffies;
1252 for (i = 0; i < NUM_DCR; i++) {
1253 struct nfit_test_fw *fw = &t->fw[i];
1257 if (fw->state != FW_STATE_UPDATED)
1258 fw->missed_activate = true;
1260 fw->state = FW_STATE_NEW;
1262 fw->last_activate = last_activate;
1268 static int nd_intel_test_cmd_fw_activate_dimminfo(struct nfit_test *t,
1269 struct nd_intel_fw_activate_dimminfo *nd_cmd,
1270 unsigned int buf_len, int dimm)
1272 struct nd_intel_bus_fw_activate_businfo info;
1273 struct nfit_test_fw *fw = &t->fw[dimm];
1276 nvdimm_bus_intel_fw_activate_businfo(t, &info, sizeof(info));
1278 if (info.state == ND_INTEL_FWA_BUSY)
1279 state = ND_INTEL_FWA_BUSY;
1280 else if (info.state == ND_INTEL_FWA_IDLE)
1281 state = ND_INTEL_FWA_IDLE;
1283 state = ND_INTEL_FWA_ARMED;
1285 state = ND_INTEL_FWA_IDLE;
1287 result = ND_INTEL_DIMM_FWA_NONE;
1288 if (last_activate && fw->last_activate == last_activate &&
1289 state == ND_INTEL_FWA_IDLE) {
1290 if (fw->missed_activate)
1291 result = ND_INTEL_DIMM_FWA_NOTSTAGED;
1293 result = ND_INTEL_DIMM_FWA_SUCCESS;
1296 *nd_cmd = (struct nd_intel_fw_activate_dimminfo) {
1304 static int nd_intel_test_cmd_fw_activate_arm(struct nfit_test *t,
1305 struct nd_intel_fw_activate_arm *nd_cmd,
1306 unsigned int buf_len, int dimm)
1308 struct nfit_test_fw *fw = &t->fw[dimm];
1310 fw->armed = nd_cmd->activate_arm == ND_INTEL_DIMM_FWA_ARM;
1315 static int get_dimm(struct nfit_mem *nfit_mem, unsigned int func)
1319 /* lookup per-dimm data */
1320 for (i = 0; i < ARRAY_SIZE(handle); i++)
1321 if (__to_nfit_memdev(nfit_mem)->device_handle == handle[i])
1323 if (i >= ARRAY_SIZE(handle))
1328 static void nfit_ctl_dbg(struct acpi_nfit_desc *acpi_desc,
1329 struct nvdimm *nvdimm, unsigned int cmd, void *buf,
1332 struct nfit_test *t = container_of(acpi_desc, typeof(*t), acpi_desc);
1333 unsigned int func = cmd;
1334 unsigned int family = 0;
1336 if (cmd == ND_CMD_CALL) {
1337 struct nd_cmd_pkg *pkg = buf;
1339 len = pkg->nd_size_in;
1340 family = pkg->nd_family;
1341 buf = pkg->nd_payload;
1342 func = pkg->nd_command;
1344 dev_dbg(&t->pdev.dev, "%s family: %d cmd: %d: func: %d input length: %d\n",
1345 nvdimm ? nvdimm_name(nvdimm) : "bus", family, cmd, func,
1347 print_hex_dump_debug("nvdimm in ", DUMP_PREFIX_OFFSET, 16, 4,
1348 buf, min(len, 256u), true);
1351 static int nfit_test_ctl(struct nvdimm_bus_descriptor *nd_desc,
1352 struct nvdimm *nvdimm, unsigned int cmd, void *buf,
1353 unsigned int buf_len, int *cmd_rc)
1355 struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
1356 struct nfit_test *t = container_of(acpi_desc, typeof(*t), acpi_desc);
1357 unsigned int func = cmd;
1358 int i, rc = 0, __cmd_rc;
1364 nfit_ctl_dbg(acpi_desc, nvdimm, cmd, buf, buf_len);
1367 struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
1368 unsigned long cmd_mask = nvdimm_cmd_mask(nvdimm);
1373 if (cmd == ND_CMD_CALL) {
1374 struct nd_cmd_pkg *call_pkg = buf;
1376 buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out;
1377 buf = (void *) call_pkg->nd_payload;
1378 func = call_pkg->nd_command;
1379 if (call_pkg->nd_family != nfit_mem->family)
1382 i = get_dimm(nfit_mem, func);
1386 dev_WARN_ONCE(&t->pdev.dev, 1,
1387 "ND_CMD_CALL only valid for nfit_test0\n");
1392 case NVDIMM_INTEL_GET_SECURITY_STATE:
1393 rc = nd_intel_test_cmd_security_status(t,
1396 case NVDIMM_INTEL_UNLOCK_UNIT:
1397 rc = nd_intel_test_cmd_unlock_unit(t,
1400 case NVDIMM_INTEL_SET_PASSPHRASE:
1401 rc = nd_intel_test_cmd_set_pass(t,
1404 case NVDIMM_INTEL_DISABLE_PASSPHRASE:
1405 rc = nd_intel_test_cmd_disable_pass(t,
1408 case NVDIMM_INTEL_FREEZE_LOCK:
1409 rc = nd_intel_test_cmd_freeze_lock(t,
1412 case NVDIMM_INTEL_SECURE_ERASE:
1413 rc = nd_intel_test_cmd_secure_erase(t,
1416 case NVDIMM_INTEL_OVERWRITE:
1417 rc = nd_intel_test_cmd_overwrite(t,
1420 case NVDIMM_INTEL_QUERY_OVERWRITE:
1421 rc = nd_intel_test_cmd_query_overwrite(t,
1424 case NVDIMM_INTEL_SET_MASTER_PASSPHRASE:
1425 rc = nd_intel_test_cmd_master_set_pass(t,
1428 case NVDIMM_INTEL_MASTER_SECURE_ERASE:
1429 rc = nd_intel_test_cmd_master_secure_erase(t,
1432 case NVDIMM_INTEL_FW_ACTIVATE_DIMMINFO:
1433 rc = nd_intel_test_cmd_fw_activate_dimminfo(
1434 t, buf, buf_len, i);
1436 case NVDIMM_INTEL_FW_ACTIVATE_ARM:
1437 rc = nd_intel_test_cmd_fw_activate_arm(
1438 t, buf, buf_len, i);
1440 case ND_INTEL_ENABLE_LSS_STATUS:
1441 rc = nd_intel_test_cmd_set_lss_status(t,
1444 case ND_INTEL_FW_GET_INFO:
1445 rc = nd_intel_test_get_fw_info(t, buf,
1448 case ND_INTEL_FW_START_UPDATE:
1449 rc = nd_intel_test_start_update(t, buf,
1452 case ND_INTEL_FW_SEND_DATA:
1453 rc = nd_intel_test_send_data(t, buf,
1456 case ND_INTEL_FW_FINISH_UPDATE:
1457 rc = nd_intel_test_finish_fw(t, buf,
1460 case ND_INTEL_FW_FINISH_QUERY:
1461 rc = nd_intel_test_finish_query(t, buf,
1464 case ND_INTEL_SMART:
1465 rc = nfit_test_cmd_smart(buf, buf_len,
1468 case ND_INTEL_SMART_THRESHOLD:
1469 rc = nfit_test_cmd_smart_threshold(buf,
1471 &t->smart_threshold[i]);
1473 case ND_INTEL_SMART_SET_THRESHOLD:
1474 rc = nfit_test_cmd_smart_set_threshold(buf,
1476 &t->smart_threshold[i],
1478 &t->pdev.dev, t->dimm_dev[i]);
1480 case ND_INTEL_SMART_INJECT:
1481 rc = nfit_test_cmd_smart_inject(buf,
1483 &t->smart_threshold[i],
1485 &t->pdev.dev, t->dimm_dev[i]);
1490 return override_return_code(i, func, rc);
1493 if (!test_bit(cmd, &cmd_mask)
1494 || !test_bit(func, &nfit_mem->dsm_mask))
1497 i = get_dimm(nfit_mem, func);
1502 case ND_CMD_GET_CONFIG_SIZE:
1503 rc = nfit_test_cmd_get_config_size(buf, buf_len);
1505 case ND_CMD_GET_CONFIG_DATA:
1506 rc = nfit_test_cmd_get_config_data(buf, buf_len,
1507 t->label[i - t->dcr_idx]);
1509 case ND_CMD_SET_CONFIG_DATA:
1510 rc = nfit_test_cmd_set_config_data(buf, buf_len,
1511 t->label[i - t->dcr_idx]);
1516 return override_return_code(i, func, rc);
1518 struct ars_state *ars_state = &t->ars_state;
1519 struct nd_cmd_pkg *call_pkg = buf;
1524 if (cmd == ND_CMD_CALL && call_pkg->nd_family
1525 == NVDIMM_BUS_FAMILY_NFIT) {
1526 func = call_pkg->nd_command;
1527 buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out;
1528 buf = (void *) call_pkg->nd_payload;
1531 case NFIT_CMD_TRANSLATE_SPA:
1532 rc = nfit_test_cmd_translate_spa(
1533 acpi_desc->nvdimm_bus, buf, buf_len);
1535 case NFIT_CMD_ARS_INJECT_SET:
1536 rc = nfit_test_cmd_ars_error_inject(t, buf,
1539 case NFIT_CMD_ARS_INJECT_CLEAR:
1540 rc = nfit_test_cmd_ars_inject_clear(t, buf,
1543 case NFIT_CMD_ARS_INJECT_GET:
1544 rc = nfit_test_cmd_ars_inject_status(t, buf,
1550 } else if (cmd == ND_CMD_CALL && call_pkg->nd_family
1551 == NVDIMM_BUS_FAMILY_INTEL) {
1552 func = call_pkg->nd_command;
1553 buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out;
1554 buf = (void *) call_pkg->nd_payload;
1557 case NVDIMM_BUS_INTEL_FW_ACTIVATE_BUSINFO:
1558 rc = nvdimm_bus_intel_fw_activate_businfo(t,
1561 case NVDIMM_BUS_INTEL_FW_ACTIVATE:
1562 rc = nvdimm_bus_intel_fw_activate(t, buf,
1568 } else if (cmd == ND_CMD_CALL)
1571 if (!nd_desc || !test_bit(cmd, &nd_desc->cmd_mask))
1575 case ND_CMD_ARS_CAP:
1576 rc = nfit_test_cmd_ars_cap(buf, buf_len);
1578 case ND_CMD_ARS_START:
1579 rc = nfit_test_cmd_ars_start(t, ars_state, buf,
1582 case ND_CMD_ARS_STATUS:
1583 rc = nfit_test_cmd_ars_status(ars_state, buf, buf_len,
1586 case ND_CMD_CLEAR_ERROR:
1587 rc = nfit_test_cmd_clear_error(t, buf, buf_len, cmd_rc);
1597 static DEFINE_SPINLOCK(nfit_test_lock);
1598 static struct nfit_test *instances[NUM_NFITS];
1600 static void release_nfit_res(void *data)
1602 struct nfit_test_resource *nfit_res = data;
1604 spin_lock(&nfit_test_lock);
1605 list_del(&nfit_res->list);
1606 spin_unlock(&nfit_test_lock);
1608 if (resource_size(&nfit_res->res) >= DIMM_SIZE)
1609 gen_pool_free(nfit_pool, nfit_res->res.start,
1610 resource_size(&nfit_res->res));
1611 vfree(nfit_res->buf);
1615 static void *__test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma,
1618 struct device *dev = &t->pdev.dev;
1619 struct nfit_test_resource *nfit_res = kzalloc(sizeof(*nfit_res),
1623 if (!buf || !nfit_res || !*dma)
1625 rc = devm_add_action(dev, release_nfit_res, nfit_res);
1628 INIT_LIST_HEAD(&nfit_res->list);
1629 memset(buf, 0, size);
1630 nfit_res->dev = dev;
1631 nfit_res->buf = buf;
1632 nfit_res->res.start = *dma;
1633 nfit_res->res.end = *dma + size - 1;
1634 nfit_res->res.name = "NFIT";
1635 spin_lock_init(&nfit_res->lock);
1636 INIT_LIST_HEAD(&nfit_res->requests);
1637 spin_lock(&nfit_test_lock);
1638 list_add(&nfit_res->list, &t->resources);
1639 spin_unlock(&nfit_test_lock);
1641 return nfit_res->buf;
1643 if (*dma && size >= DIMM_SIZE)
1644 gen_pool_free(nfit_pool, *dma, size);
1651 static void *test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma)
1653 struct genpool_data_align data = {
1656 void *buf = vmalloc(size);
1658 if (size >= DIMM_SIZE)
1659 *dma = gen_pool_alloc_algo(nfit_pool, size,
1660 gen_pool_first_fit_align, &data);
1662 *dma = (unsigned long) buf;
1663 return __test_alloc(t, size, dma, buf);
1666 static struct nfit_test_resource *nfit_test_lookup(resource_size_t addr)
1670 for (i = 0; i < ARRAY_SIZE(instances); i++) {
1671 struct nfit_test_resource *n, *nfit_res = NULL;
1672 struct nfit_test *t = instances[i];
1676 spin_lock(&nfit_test_lock);
1677 list_for_each_entry(n, &t->resources, list) {
1678 if (addr >= n->res.start && (addr < n->res.start
1679 + resource_size(&n->res))) {
1682 } else if (addr >= (unsigned long) n->buf
1683 && (addr < (unsigned long) n->buf
1684 + resource_size(&n->res))) {
1689 spin_unlock(&nfit_test_lock);
1697 static int ars_state_init(struct device *dev, struct ars_state *ars_state)
1699 /* for testing, only store up to n records that fit within 4k */
1700 ars_state->ars_status = devm_kzalloc(dev,
1701 sizeof(struct nd_cmd_ars_status) + SZ_4K, GFP_KERNEL);
1702 if (!ars_state->ars_status)
1704 spin_lock_init(&ars_state->lock);
1708 static void put_dimms(void *data)
1710 struct nfit_test *t = data;
1713 for (i = 0; i < t->num_dcr; i++)
1715 device_unregister(t->dimm_dev[i]);
1718 static struct class *nfit_test_dimm;
1720 static int dimm_name_to_id(struct device *dev)
1724 if (sscanf(dev_name(dev), "test_dimm%d", &dimm) != 1)
1729 static ssize_t handle_show(struct device *dev, struct device_attribute *attr,
1732 int dimm = dimm_name_to_id(dev);
1737 return sprintf(buf, "%#x\n", handle[dimm]);
1739 DEVICE_ATTR_RO(handle);
1741 static ssize_t fail_cmd_show(struct device *dev, struct device_attribute *attr,
1744 int dimm = dimm_name_to_id(dev);
1749 return sprintf(buf, "%#lx\n", dimm_fail_cmd_flags[dimm]);
1752 static ssize_t fail_cmd_store(struct device *dev, struct device_attribute *attr,
1753 const char *buf, size_t size)
1755 int dimm = dimm_name_to_id(dev);
1762 rc = kstrtol(buf, 0, &val);
1766 dimm_fail_cmd_flags[dimm] = val;
1769 static DEVICE_ATTR_RW(fail_cmd);
1771 static ssize_t fail_cmd_code_show(struct device *dev, struct device_attribute *attr,
1774 int dimm = dimm_name_to_id(dev);
1779 return sprintf(buf, "%d\n", dimm_fail_cmd_code[dimm]);
1782 static ssize_t fail_cmd_code_store(struct device *dev, struct device_attribute *attr,
1783 const char *buf, size_t size)
1785 int dimm = dimm_name_to_id(dev);
1792 rc = kstrtol(buf, 0, &val);
1796 dimm_fail_cmd_code[dimm] = val;
1799 static DEVICE_ATTR_RW(fail_cmd_code);
1801 static ssize_t lock_dimm_store(struct device *dev,
1802 struct device_attribute *attr, const char *buf, size_t size)
1804 int dimm = dimm_name_to_id(dev);
1805 struct nfit_test_sec *sec = &dimm_sec_info[dimm];
1807 sec->state = ND_INTEL_SEC_STATE_ENABLED | ND_INTEL_SEC_STATE_LOCKED;
1810 static DEVICE_ATTR_WO(lock_dimm);
1812 static struct attribute *nfit_test_dimm_attributes[] = {
1813 &dev_attr_fail_cmd.attr,
1814 &dev_attr_fail_cmd_code.attr,
1815 &dev_attr_handle.attr,
1816 &dev_attr_lock_dimm.attr,
1820 static struct attribute_group nfit_test_dimm_attribute_group = {
1821 .attrs = nfit_test_dimm_attributes,
1824 static const struct attribute_group *nfit_test_dimm_attribute_groups[] = {
1825 &nfit_test_dimm_attribute_group,
1829 static int nfit_test_dimm_init(struct nfit_test *t)
1833 if (devm_add_action_or_reset(&t->pdev.dev, put_dimms, t))
1835 for (i = 0; i < t->num_dcr; i++) {
1836 t->dimm_dev[i] = device_create_with_groups(nfit_test_dimm,
1837 &t->pdev.dev, 0, NULL,
1838 nfit_test_dimm_attribute_groups,
1839 "test_dimm%d", i + t->dcr_idx);
1840 if (!t->dimm_dev[i])
1846 static void security_init(struct nfit_test *t)
1850 for (i = 0; i < t->num_dcr; i++) {
1851 struct nfit_test_sec *sec = &dimm_sec_info[i];
1853 sec->ext_state = ND_INTEL_SEC_ESTATE_ENABLED;
1857 static void smart_init(struct nfit_test *t)
1860 const struct nd_intel_smart_threshold smart_t_data = {
1861 .alarm_control = ND_INTEL_SMART_SPARE_TRIP
1862 | ND_INTEL_SMART_TEMP_TRIP,
1863 .media_temperature = 40 * 16,
1864 .ctrl_temperature = 30 * 16,
1868 for (i = 0; i < t->num_dcr; i++) {
1869 memcpy(&t->smart[i], &smart_def, sizeof(smart_def));
1870 memcpy(&t->smart_threshold[i], &smart_t_data,
1871 sizeof(smart_t_data));
1875 static int nfit_test0_alloc(struct nfit_test *t)
1877 size_t nfit_size = sizeof(struct acpi_nfit_system_address) * NUM_SPA
1878 + sizeof(struct acpi_nfit_memory_map) * NUM_MEM
1879 + sizeof(struct acpi_nfit_control_region) * NUM_DCR
1880 + offsetof(struct acpi_nfit_control_region,
1881 window_size) * NUM_DCR
1882 + sizeof(struct acpi_nfit_data_region) * NUM_BDW
1883 + (sizeof(struct acpi_nfit_flush_address)
1884 + sizeof(u64) * NUM_HINTS) * NUM_DCR
1885 + sizeof(struct acpi_nfit_capabilities);
1888 t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma);
1891 t->nfit_size = nfit_size;
1893 t->spa_set[0] = test_alloc(t, SPA0_SIZE, &t->spa_set_dma[0]);
1897 t->spa_set[1] = test_alloc(t, SPA1_SIZE, &t->spa_set_dma[1]);
1901 t->spa_set[2] = test_alloc(t, SPA0_SIZE, &t->spa_set_dma[2]);
1905 for (i = 0; i < t->num_dcr; i++) {
1906 t->dimm[i] = test_alloc(t, DIMM_SIZE, &t->dimm_dma[i]);
1910 t->label[i] = test_alloc(t, LABEL_SIZE, &t->label_dma[i]);
1913 sprintf(t->label[i], "label%d", i);
1915 t->flush[i] = test_alloc(t, max(PAGE_SIZE,
1916 sizeof(u64) * NUM_HINTS),
1922 for (i = 0; i < t->num_dcr; i++) {
1923 t->dcr[i] = test_alloc(t, LABEL_SIZE, &t->dcr_dma[i]);
1928 t->_fit = test_alloc(t, sizeof(union acpi_object **), &t->_fit_dma);
1932 if (nfit_test_dimm_init(t))
1936 return ars_state_init(&t->pdev.dev, &t->ars_state);
1939 static int nfit_test1_alloc(struct nfit_test *t)
1941 size_t nfit_size = sizeof(struct acpi_nfit_system_address) * 2
1942 + sizeof(struct acpi_nfit_memory_map) * 2
1943 + offsetof(struct acpi_nfit_control_region, window_size) * 2;
1946 t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma);
1949 t->nfit_size = nfit_size;
1951 t->spa_set[0] = test_alloc(t, SPA2_SIZE, &t->spa_set_dma[0]);
1955 for (i = 0; i < t->num_dcr; i++) {
1956 t->label[i] = test_alloc(t, LABEL_SIZE, &t->label_dma[i]);
1959 sprintf(t->label[i], "label%d", i);
1962 t->spa_set[1] = test_alloc(t, SPA_VCD_SIZE, &t->spa_set_dma[1]);
1966 if (nfit_test_dimm_init(t))
1969 return ars_state_init(&t->pdev.dev, &t->ars_state);
1972 static void dcr_common_init(struct acpi_nfit_control_region *dcr)
1974 dcr->vendor_id = 0xabcd;
1976 dcr->revision_id = 1;
1977 dcr->valid_fields = 1;
1978 dcr->manufacturing_location = 0xa;
1979 dcr->manufacturing_date = cpu_to_be16(2016);
1982 static void nfit_test0_setup(struct nfit_test *t)
1984 const int flush_hint_size = sizeof(struct acpi_nfit_flush_address)
1985 + (sizeof(u64) * NUM_HINTS);
1986 struct acpi_nfit_desc *acpi_desc;
1987 struct acpi_nfit_memory_map *memdev;
1988 void *nfit_buf = t->nfit_buf;
1989 struct acpi_nfit_system_address *spa;
1990 struct acpi_nfit_control_region *dcr;
1991 struct acpi_nfit_data_region *bdw;
1992 struct acpi_nfit_flush_address *flush;
1993 struct acpi_nfit_capabilities *pcap;
1994 unsigned int offset = 0, i;
1995 unsigned long *acpi_mask;
1998 * spa0 (interleave first half of dimm0 and dimm1, note storage
1999 * does not actually alias the related block-data-window
2003 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2004 spa->header.length = sizeof(*spa);
2005 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
2006 spa->range_index = 0+1;
2007 spa->address = t->spa_set_dma[0];
2008 spa->length = SPA0_SIZE;
2009 offset += spa->header.length;
2012 * spa1 (interleave last half of the 4 DIMMS, note storage
2013 * does not actually alias the related block-data-window
2016 spa = nfit_buf + offset;
2017 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2018 spa->header.length = sizeof(*spa);
2019 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
2020 spa->range_index = 1+1;
2021 spa->address = t->spa_set_dma[1];
2022 spa->length = SPA1_SIZE;
2023 offset += spa->header.length;
2025 /* spa2 (dcr0) dimm0 */
2026 spa = nfit_buf + offset;
2027 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2028 spa->header.length = sizeof(*spa);
2029 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
2030 spa->range_index = 2+1;
2031 spa->address = t->dcr_dma[0];
2032 spa->length = DCR_SIZE;
2033 offset += spa->header.length;
2035 /* spa3 (dcr1) dimm1 */
2036 spa = nfit_buf + offset;
2037 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2038 spa->header.length = sizeof(*spa);
2039 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
2040 spa->range_index = 3+1;
2041 spa->address = t->dcr_dma[1];
2042 spa->length = DCR_SIZE;
2043 offset += spa->header.length;
2045 /* spa4 (dcr2) dimm2 */
2046 spa = nfit_buf + offset;
2047 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2048 spa->header.length = sizeof(*spa);
2049 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
2050 spa->range_index = 4+1;
2051 spa->address = t->dcr_dma[2];
2052 spa->length = DCR_SIZE;
2053 offset += spa->header.length;
2055 /* spa5 (dcr3) dimm3 */
2056 spa = nfit_buf + offset;
2057 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2058 spa->header.length = sizeof(*spa);
2059 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
2060 spa->range_index = 5+1;
2061 spa->address = t->dcr_dma[3];
2062 spa->length = DCR_SIZE;
2063 offset += spa->header.length;
2065 /* spa6 (bdw for dcr0) dimm0 */
2066 spa = nfit_buf + offset;
2067 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2068 spa->header.length = sizeof(*spa);
2069 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
2070 spa->range_index = 6+1;
2071 spa->address = t->dimm_dma[0];
2072 spa->length = DIMM_SIZE;
2073 offset += spa->header.length;
2075 /* spa7 (bdw for dcr1) dimm1 */
2076 spa = nfit_buf + offset;
2077 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2078 spa->header.length = sizeof(*spa);
2079 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
2080 spa->range_index = 7+1;
2081 spa->address = t->dimm_dma[1];
2082 spa->length = DIMM_SIZE;
2083 offset += spa->header.length;
2085 /* spa8 (bdw for dcr2) dimm2 */
2086 spa = nfit_buf + offset;
2087 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2088 spa->header.length = sizeof(*spa);
2089 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
2090 spa->range_index = 8+1;
2091 spa->address = t->dimm_dma[2];
2092 spa->length = DIMM_SIZE;
2093 offset += spa->header.length;
2095 /* spa9 (bdw for dcr3) dimm3 */
2096 spa = nfit_buf + offset;
2097 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2098 spa->header.length = sizeof(*spa);
2099 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
2100 spa->range_index = 9+1;
2101 spa->address = t->dimm_dma[3];
2102 spa->length = DIMM_SIZE;
2103 offset += spa->header.length;
2105 /* mem-region0 (spa0, dimm0) */
2106 memdev = nfit_buf + offset;
2107 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2108 memdev->header.length = sizeof(*memdev);
2109 memdev->device_handle = handle[0];
2110 memdev->physical_id = 0;
2111 memdev->region_id = 0;
2112 memdev->range_index = 0+1;
2113 memdev->region_index = 4+1;
2114 memdev->region_size = SPA0_SIZE/2;
2115 memdev->region_offset = 1;
2116 memdev->address = 0;
2117 memdev->interleave_index = 0;
2118 memdev->interleave_ways = 2;
2119 offset += memdev->header.length;
2121 /* mem-region1 (spa0, dimm1) */
2122 memdev = nfit_buf + offset;
2123 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2124 memdev->header.length = sizeof(*memdev);
2125 memdev->device_handle = handle[1];
2126 memdev->physical_id = 1;
2127 memdev->region_id = 0;
2128 memdev->range_index = 0+1;
2129 memdev->region_index = 5+1;
2130 memdev->region_size = SPA0_SIZE/2;
2131 memdev->region_offset = (1 << 8);
2132 memdev->address = 0;
2133 memdev->interleave_index = 0;
2134 memdev->interleave_ways = 2;
2135 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
2136 offset += memdev->header.length;
2138 /* mem-region2 (spa1, dimm0) */
2139 memdev = nfit_buf + offset;
2140 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2141 memdev->header.length = sizeof(*memdev);
2142 memdev->device_handle = handle[0];
2143 memdev->physical_id = 0;
2144 memdev->region_id = 1;
2145 memdev->range_index = 1+1;
2146 memdev->region_index = 4+1;
2147 memdev->region_size = SPA1_SIZE/4;
2148 memdev->region_offset = (1 << 16);
2149 memdev->address = SPA0_SIZE/2;
2150 memdev->interleave_index = 0;
2151 memdev->interleave_ways = 4;
2152 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
2153 offset += memdev->header.length;
2155 /* mem-region3 (spa1, dimm1) */
2156 memdev = nfit_buf + offset;
2157 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2158 memdev->header.length = sizeof(*memdev);
2159 memdev->device_handle = handle[1];
2160 memdev->physical_id = 1;
2161 memdev->region_id = 1;
2162 memdev->range_index = 1+1;
2163 memdev->region_index = 5+1;
2164 memdev->region_size = SPA1_SIZE/4;
2165 memdev->region_offset = (1 << 24);
2166 memdev->address = SPA0_SIZE/2;
2167 memdev->interleave_index = 0;
2168 memdev->interleave_ways = 4;
2169 offset += memdev->header.length;
2171 /* mem-region4 (spa1, dimm2) */
2172 memdev = nfit_buf + offset;
2173 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2174 memdev->header.length = sizeof(*memdev);
2175 memdev->device_handle = handle[2];
2176 memdev->physical_id = 2;
2177 memdev->region_id = 0;
2178 memdev->range_index = 1+1;
2179 memdev->region_index = 6+1;
2180 memdev->region_size = SPA1_SIZE/4;
2181 memdev->region_offset = (1ULL << 32);
2182 memdev->address = SPA0_SIZE/2;
2183 memdev->interleave_index = 0;
2184 memdev->interleave_ways = 4;
2185 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
2186 offset += memdev->header.length;
2188 /* mem-region5 (spa1, dimm3) */
2189 memdev = nfit_buf + offset;
2190 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2191 memdev->header.length = sizeof(*memdev);
2192 memdev->device_handle = handle[3];
2193 memdev->physical_id = 3;
2194 memdev->region_id = 0;
2195 memdev->range_index = 1+1;
2196 memdev->region_index = 7+1;
2197 memdev->region_size = SPA1_SIZE/4;
2198 memdev->region_offset = (1ULL << 40);
2199 memdev->address = SPA0_SIZE/2;
2200 memdev->interleave_index = 0;
2201 memdev->interleave_ways = 4;
2202 offset += memdev->header.length;
2204 /* mem-region6 (spa/dcr0, dimm0) */
2205 memdev = nfit_buf + offset;
2206 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2207 memdev->header.length = sizeof(*memdev);
2208 memdev->device_handle = handle[0];
2209 memdev->physical_id = 0;
2210 memdev->region_id = 0;
2211 memdev->range_index = 2+1;
2212 memdev->region_index = 0+1;
2213 memdev->region_size = 0;
2214 memdev->region_offset = 0;
2215 memdev->address = 0;
2216 memdev->interleave_index = 0;
2217 memdev->interleave_ways = 1;
2218 offset += memdev->header.length;
2220 /* mem-region7 (spa/dcr1, dimm1) */
2221 memdev = nfit_buf + offset;
2222 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2223 memdev->header.length = sizeof(*memdev);
2224 memdev->device_handle = handle[1];
2225 memdev->physical_id = 1;
2226 memdev->region_id = 0;
2227 memdev->range_index = 3+1;
2228 memdev->region_index = 1+1;
2229 memdev->region_size = 0;
2230 memdev->region_offset = 0;
2231 memdev->address = 0;
2232 memdev->interleave_index = 0;
2233 memdev->interleave_ways = 1;
2234 offset += memdev->header.length;
2236 /* mem-region8 (spa/dcr2, dimm2) */
2237 memdev = nfit_buf + offset;
2238 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2239 memdev->header.length = sizeof(*memdev);
2240 memdev->device_handle = handle[2];
2241 memdev->physical_id = 2;
2242 memdev->region_id = 0;
2243 memdev->range_index = 4+1;
2244 memdev->region_index = 2+1;
2245 memdev->region_size = 0;
2246 memdev->region_offset = 0;
2247 memdev->address = 0;
2248 memdev->interleave_index = 0;
2249 memdev->interleave_ways = 1;
2250 offset += memdev->header.length;
2252 /* mem-region9 (spa/dcr3, dimm3) */
2253 memdev = nfit_buf + offset;
2254 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2255 memdev->header.length = sizeof(*memdev);
2256 memdev->device_handle = handle[3];
2257 memdev->physical_id = 3;
2258 memdev->region_id = 0;
2259 memdev->range_index = 5+1;
2260 memdev->region_index = 3+1;
2261 memdev->region_size = 0;
2262 memdev->region_offset = 0;
2263 memdev->address = 0;
2264 memdev->interleave_index = 0;
2265 memdev->interleave_ways = 1;
2266 offset += memdev->header.length;
2268 /* mem-region10 (spa/bdw0, dimm0) */
2269 memdev = nfit_buf + offset;
2270 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2271 memdev->header.length = sizeof(*memdev);
2272 memdev->device_handle = handle[0];
2273 memdev->physical_id = 0;
2274 memdev->region_id = 0;
2275 memdev->range_index = 6+1;
2276 memdev->region_index = 0+1;
2277 memdev->region_size = 0;
2278 memdev->region_offset = 0;
2279 memdev->address = 0;
2280 memdev->interleave_index = 0;
2281 memdev->interleave_ways = 1;
2282 offset += memdev->header.length;
2284 /* mem-region11 (spa/bdw1, dimm1) */
2285 memdev = nfit_buf + offset;
2286 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2287 memdev->header.length = sizeof(*memdev);
2288 memdev->device_handle = handle[1];
2289 memdev->physical_id = 1;
2290 memdev->region_id = 0;
2291 memdev->range_index = 7+1;
2292 memdev->region_index = 1+1;
2293 memdev->region_size = 0;
2294 memdev->region_offset = 0;
2295 memdev->address = 0;
2296 memdev->interleave_index = 0;
2297 memdev->interleave_ways = 1;
2298 offset += memdev->header.length;
2300 /* mem-region12 (spa/bdw2, dimm2) */
2301 memdev = nfit_buf + offset;
2302 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2303 memdev->header.length = sizeof(*memdev);
2304 memdev->device_handle = handle[2];
2305 memdev->physical_id = 2;
2306 memdev->region_id = 0;
2307 memdev->range_index = 8+1;
2308 memdev->region_index = 2+1;
2309 memdev->region_size = 0;
2310 memdev->region_offset = 0;
2311 memdev->address = 0;
2312 memdev->interleave_index = 0;
2313 memdev->interleave_ways = 1;
2314 offset += memdev->header.length;
2316 /* mem-region13 (spa/dcr3, dimm3) */
2317 memdev = nfit_buf + offset;
2318 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2319 memdev->header.length = sizeof(*memdev);
2320 memdev->device_handle = handle[3];
2321 memdev->physical_id = 3;
2322 memdev->region_id = 0;
2323 memdev->range_index = 9+1;
2324 memdev->region_index = 3+1;
2325 memdev->region_size = 0;
2326 memdev->region_offset = 0;
2327 memdev->address = 0;
2328 memdev->interleave_index = 0;
2329 memdev->interleave_ways = 1;
2330 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
2331 offset += memdev->header.length;
2333 /* dcr-descriptor0: blk */
2334 dcr = nfit_buf + offset;
2335 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2336 dcr->header.length = sizeof(*dcr);
2337 dcr->region_index = 0+1;
2338 dcr_common_init(dcr);
2339 dcr->serial_number = ~handle[0];
2340 dcr->code = NFIT_FIC_BLK;
2342 dcr->window_size = DCR_SIZE;
2343 dcr->command_offset = 0;
2344 dcr->command_size = 8;
2345 dcr->status_offset = 8;
2346 dcr->status_size = 4;
2347 offset += dcr->header.length;
2349 /* dcr-descriptor1: blk */
2350 dcr = nfit_buf + offset;
2351 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2352 dcr->header.length = sizeof(*dcr);
2353 dcr->region_index = 1+1;
2354 dcr_common_init(dcr);
2355 dcr->serial_number = ~handle[1];
2356 dcr->code = NFIT_FIC_BLK;
2358 dcr->window_size = DCR_SIZE;
2359 dcr->command_offset = 0;
2360 dcr->command_size = 8;
2361 dcr->status_offset = 8;
2362 dcr->status_size = 4;
2363 offset += dcr->header.length;
2365 /* dcr-descriptor2: blk */
2366 dcr = nfit_buf + offset;
2367 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2368 dcr->header.length = sizeof(*dcr);
2369 dcr->region_index = 2+1;
2370 dcr_common_init(dcr);
2371 dcr->serial_number = ~handle[2];
2372 dcr->code = NFIT_FIC_BLK;
2374 dcr->window_size = DCR_SIZE;
2375 dcr->command_offset = 0;
2376 dcr->command_size = 8;
2377 dcr->status_offset = 8;
2378 dcr->status_size = 4;
2379 offset += dcr->header.length;
2381 /* dcr-descriptor3: blk */
2382 dcr = nfit_buf + offset;
2383 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2384 dcr->header.length = sizeof(*dcr);
2385 dcr->region_index = 3+1;
2386 dcr_common_init(dcr);
2387 dcr->serial_number = ~handle[3];
2388 dcr->code = NFIT_FIC_BLK;
2390 dcr->window_size = DCR_SIZE;
2391 dcr->command_offset = 0;
2392 dcr->command_size = 8;
2393 dcr->status_offset = 8;
2394 dcr->status_size = 4;
2395 offset += dcr->header.length;
2397 /* dcr-descriptor0: pmem */
2398 dcr = nfit_buf + offset;
2399 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2400 dcr->header.length = offsetof(struct acpi_nfit_control_region,
2402 dcr->region_index = 4+1;
2403 dcr_common_init(dcr);
2404 dcr->serial_number = ~handle[0];
2405 dcr->code = NFIT_FIC_BYTEN;
2407 offset += dcr->header.length;
2409 /* dcr-descriptor1: pmem */
2410 dcr = nfit_buf + offset;
2411 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2412 dcr->header.length = offsetof(struct acpi_nfit_control_region,
2414 dcr->region_index = 5+1;
2415 dcr_common_init(dcr);
2416 dcr->serial_number = ~handle[1];
2417 dcr->code = NFIT_FIC_BYTEN;
2419 offset += dcr->header.length;
2421 /* dcr-descriptor2: pmem */
2422 dcr = nfit_buf + offset;
2423 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2424 dcr->header.length = offsetof(struct acpi_nfit_control_region,
2426 dcr->region_index = 6+1;
2427 dcr_common_init(dcr);
2428 dcr->serial_number = ~handle[2];
2429 dcr->code = NFIT_FIC_BYTEN;
2431 offset += dcr->header.length;
2433 /* dcr-descriptor3: pmem */
2434 dcr = nfit_buf + offset;
2435 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2436 dcr->header.length = offsetof(struct acpi_nfit_control_region,
2438 dcr->region_index = 7+1;
2439 dcr_common_init(dcr);
2440 dcr->serial_number = ~handle[3];
2441 dcr->code = NFIT_FIC_BYTEN;
2443 offset += dcr->header.length;
2445 /* bdw0 (spa/dcr0, dimm0) */
2446 bdw = nfit_buf + offset;
2447 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
2448 bdw->header.length = sizeof(*bdw);
2449 bdw->region_index = 0+1;
2452 bdw->size = BDW_SIZE;
2453 bdw->capacity = DIMM_SIZE;
2454 bdw->start_address = 0;
2455 offset += bdw->header.length;
2457 /* bdw1 (spa/dcr1, dimm1) */
2458 bdw = nfit_buf + offset;
2459 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
2460 bdw->header.length = sizeof(*bdw);
2461 bdw->region_index = 1+1;
2464 bdw->size = BDW_SIZE;
2465 bdw->capacity = DIMM_SIZE;
2466 bdw->start_address = 0;
2467 offset += bdw->header.length;
2469 /* bdw2 (spa/dcr2, dimm2) */
2470 bdw = nfit_buf + offset;
2471 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
2472 bdw->header.length = sizeof(*bdw);
2473 bdw->region_index = 2+1;
2476 bdw->size = BDW_SIZE;
2477 bdw->capacity = DIMM_SIZE;
2478 bdw->start_address = 0;
2479 offset += bdw->header.length;
2481 /* bdw3 (spa/dcr3, dimm3) */
2482 bdw = nfit_buf + offset;
2483 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
2484 bdw->header.length = sizeof(*bdw);
2485 bdw->region_index = 3+1;
2488 bdw->size = BDW_SIZE;
2489 bdw->capacity = DIMM_SIZE;
2490 bdw->start_address = 0;
2491 offset += bdw->header.length;
2493 /* flush0 (dimm0) */
2494 flush = nfit_buf + offset;
2495 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
2496 flush->header.length = flush_hint_size;
2497 flush->device_handle = handle[0];
2498 flush->hint_count = NUM_HINTS;
2499 for (i = 0; i < NUM_HINTS; i++)
2500 flush->hint_address[i] = t->flush_dma[0] + i * sizeof(u64);
2501 offset += flush->header.length;
2503 /* flush1 (dimm1) */
2504 flush = nfit_buf + offset;
2505 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
2506 flush->header.length = flush_hint_size;
2507 flush->device_handle = handle[1];
2508 flush->hint_count = NUM_HINTS;
2509 for (i = 0; i < NUM_HINTS; i++)
2510 flush->hint_address[i] = t->flush_dma[1] + i * sizeof(u64);
2511 offset += flush->header.length;
2513 /* flush2 (dimm2) */
2514 flush = nfit_buf + offset;
2515 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
2516 flush->header.length = flush_hint_size;
2517 flush->device_handle = handle[2];
2518 flush->hint_count = NUM_HINTS;
2519 for (i = 0; i < NUM_HINTS; i++)
2520 flush->hint_address[i] = t->flush_dma[2] + i * sizeof(u64);
2521 offset += flush->header.length;
2523 /* flush3 (dimm3) */
2524 flush = nfit_buf + offset;
2525 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
2526 flush->header.length = flush_hint_size;
2527 flush->device_handle = handle[3];
2528 flush->hint_count = NUM_HINTS;
2529 for (i = 0; i < NUM_HINTS; i++)
2530 flush->hint_address[i] = t->flush_dma[3] + i * sizeof(u64);
2531 offset += flush->header.length;
2533 /* platform capabilities */
2534 pcap = nfit_buf + offset;
2535 pcap->header.type = ACPI_NFIT_TYPE_CAPABILITIES;
2536 pcap->header.length = sizeof(*pcap);
2537 pcap->highest_capability = 1;
2538 pcap->capabilities = ACPI_NFIT_CAPABILITY_MEM_FLUSH;
2539 offset += pcap->header.length;
2541 if (t->setup_hotplug) {
2542 /* dcr-descriptor4: blk */
2543 dcr = nfit_buf + offset;
2544 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2545 dcr->header.length = sizeof(*dcr);
2546 dcr->region_index = 8+1;
2547 dcr_common_init(dcr);
2548 dcr->serial_number = ~handle[4];
2549 dcr->code = NFIT_FIC_BLK;
2551 dcr->window_size = DCR_SIZE;
2552 dcr->command_offset = 0;
2553 dcr->command_size = 8;
2554 dcr->status_offset = 8;
2555 dcr->status_size = 4;
2556 offset += dcr->header.length;
2558 /* dcr-descriptor4: pmem */
2559 dcr = nfit_buf + offset;
2560 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2561 dcr->header.length = offsetof(struct acpi_nfit_control_region,
2563 dcr->region_index = 9+1;
2564 dcr_common_init(dcr);
2565 dcr->serial_number = ~handle[4];
2566 dcr->code = NFIT_FIC_BYTEN;
2568 offset += dcr->header.length;
2570 /* bdw4 (spa/dcr4, dimm4) */
2571 bdw = nfit_buf + offset;
2572 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
2573 bdw->header.length = sizeof(*bdw);
2574 bdw->region_index = 8+1;
2577 bdw->size = BDW_SIZE;
2578 bdw->capacity = DIMM_SIZE;
2579 bdw->start_address = 0;
2580 offset += bdw->header.length;
2582 /* spa10 (dcr4) dimm4 */
2583 spa = nfit_buf + offset;
2584 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2585 spa->header.length = sizeof(*spa);
2586 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
2587 spa->range_index = 10+1;
2588 spa->address = t->dcr_dma[4];
2589 spa->length = DCR_SIZE;
2590 offset += spa->header.length;
2593 * spa11 (single-dimm interleave for hotplug, note storage
2594 * does not actually alias the related block-data-window
2597 spa = nfit_buf + offset;
2598 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2599 spa->header.length = sizeof(*spa);
2600 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
2601 spa->range_index = 11+1;
2602 spa->address = t->spa_set_dma[2];
2603 spa->length = SPA0_SIZE;
2604 offset += spa->header.length;
2606 /* spa12 (bdw for dcr4) dimm4 */
2607 spa = nfit_buf + offset;
2608 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2609 spa->header.length = sizeof(*spa);
2610 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
2611 spa->range_index = 12+1;
2612 spa->address = t->dimm_dma[4];
2613 spa->length = DIMM_SIZE;
2614 offset += spa->header.length;
2616 /* mem-region14 (spa/dcr4, dimm4) */
2617 memdev = nfit_buf + offset;
2618 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2619 memdev->header.length = sizeof(*memdev);
2620 memdev->device_handle = handle[4];
2621 memdev->physical_id = 4;
2622 memdev->region_id = 0;
2623 memdev->range_index = 10+1;
2624 memdev->region_index = 8+1;
2625 memdev->region_size = 0;
2626 memdev->region_offset = 0;
2627 memdev->address = 0;
2628 memdev->interleave_index = 0;
2629 memdev->interleave_ways = 1;
2630 offset += memdev->header.length;
2632 /* mem-region15 (spa11, dimm4) */
2633 memdev = nfit_buf + offset;
2634 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2635 memdev->header.length = sizeof(*memdev);
2636 memdev->device_handle = handle[4];
2637 memdev->physical_id = 4;
2638 memdev->region_id = 0;
2639 memdev->range_index = 11+1;
2640 memdev->region_index = 9+1;
2641 memdev->region_size = SPA0_SIZE;
2642 memdev->region_offset = (1ULL << 48);
2643 memdev->address = 0;
2644 memdev->interleave_index = 0;
2645 memdev->interleave_ways = 1;
2646 memdev->flags = ACPI_NFIT_MEM_HEALTH_ENABLED;
2647 offset += memdev->header.length;
2649 /* mem-region16 (spa/bdw4, dimm4) */
2650 memdev = nfit_buf + offset;
2651 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2652 memdev->header.length = sizeof(*memdev);
2653 memdev->device_handle = handle[4];
2654 memdev->physical_id = 4;
2655 memdev->region_id = 0;
2656 memdev->range_index = 12+1;
2657 memdev->region_index = 8+1;
2658 memdev->region_size = 0;
2659 memdev->region_offset = 0;
2660 memdev->address = 0;
2661 memdev->interleave_index = 0;
2662 memdev->interleave_ways = 1;
2663 offset += memdev->header.length;
2665 /* flush3 (dimm4) */
2666 flush = nfit_buf + offset;
2667 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
2668 flush->header.length = flush_hint_size;
2669 flush->device_handle = handle[4];
2670 flush->hint_count = NUM_HINTS;
2671 for (i = 0; i < NUM_HINTS; i++)
2672 flush->hint_address[i] = t->flush_dma[4]
2674 offset += flush->header.length;
2676 /* sanity check to make sure we've filled the buffer */
2677 WARN_ON(offset != t->nfit_size);
2680 t->nfit_filled = offset;
2682 post_ars_status(&t->ars_state, &t->badrange, t->spa_set_dma[0],
2685 acpi_desc = &t->acpi_desc;
2686 set_bit(ND_CMD_GET_CONFIG_SIZE, &acpi_desc->dimm_cmd_force_en);
2687 set_bit(ND_CMD_GET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
2688 set_bit(ND_CMD_SET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
2689 set_bit(ND_INTEL_SMART, &acpi_desc->dimm_cmd_force_en);
2690 set_bit(ND_INTEL_SMART_THRESHOLD, &acpi_desc->dimm_cmd_force_en);
2691 set_bit(ND_INTEL_SMART_SET_THRESHOLD, &acpi_desc->dimm_cmd_force_en);
2692 set_bit(ND_INTEL_SMART_INJECT, &acpi_desc->dimm_cmd_force_en);
2693 set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en);
2694 set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en);
2695 set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en);
2696 set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en);
2697 set_bit(ND_CMD_CALL, &acpi_desc->bus_cmd_force_en);
2698 set_bit(NFIT_CMD_TRANSLATE_SPA, &acpi_desc->bus_dsm_mask);
2699 set_bit(NFIT_CMD_ARS_INJECT_SET, &acpi_desc->bus_dsm_mask);
2700 set_bit(NFIT_CMD_ARS_INJECT_CLEAR, &acpi_desc->bus_dsm_mask);
2701 set_bit(NFIT_CMD_ARS_INJECT_GET, &acpi_desc->bus_dsm_mask);
2702 set_bit(ND_INTEL_FW_GET_INFO, &acpi_desc->dimm_cmd_force_en);
2703 set_bit(ND_INTEL_FW_START_UPDATE, &acpi_desc->dimm_cmd_force_en);
2704 set_bit(ND_INTEL_FW_SEND_DATA, &acpi_desc->dimm_cmd_force_en);
2705 set_bit(ND_INTEL_FW_FINISH_UPDATE, &acpi_desc->dimm_cmd_force_en);
2706 set_bit(ND_INTEL_FW_FINISH_QUERY, &acpi_desc->dimm_cmd_force_en);
2707 set_bit(ND_INTEL_ENABLE_LSS_STATUS, &acpi_desc->dimm_cmd_force_en);
2708 set_bit(NVDIMM_INTEL_GET_SECURITY_STATE,
2709 &acpi_desc->dimm_cmd_force_en);
2710 set_bit(NVDIMM_INTEL_SET_PASSPHRASE, &acpi_desc->dimm_cmd_force_en);
2711 set_bit(NVDIMM_INTEL_DISABLE_PASSPHRASE,
2712 &acpi_desc->dimm_cmd_force_en);
2713 set_bit(NVDIMM_INTEL_UNLOCK_UNIT, &acpi_desc->dimm_cmd_force_en);
2714 set_bit(NVDIMM_INTEL_FREEZE_LOCK, &acpi_desc->dimm_cmd_force_en);
2715 set_bit(NVDIMM_INTEL_SECURE_ERASE, &acpi_desc->dimm_cmd_force_en);
2716 set_bit(NVDIMM_INTEL_OVERWRITE, &acpi_desc->dimm_cmd_force_en);
2717 set_bit(NVDIMM_INTEL_QUERY_OVERWRITE, &acpi_desc->dimm_cmd_force_en);
2718 set_bit(NVDIMM_INTEL_SET_MASTER_PASSPHRASE,
2719 &acpi_desc->dimm_cmd_force_en);
2720 set_bit(NVDIMM_INTEL_MASTER_SECURE_ERASE,
2721 &acpi_desc->dimm_cmd_force_en);
2722 set_bit(NVDIMM_INTEL_FW_ACTIVATE_DIMMINFO, &acpi_desc->dimm_cmd_force_en);
2723 set_bit(NVDIMM_INTEL_FW_ACTIVATE_ARM, &acpi_desc->dimm_cmd_force_en);
2725 acpi_mask = &acpi_desc->family_dsm_mask[NVDIMM_BUS_FAMILY_INTEL];
2726 set_bit(NVDIMM_BUS_INTEL_FW_ACTIVATE_BUSINFO, acpi_mask);
2727 set_bit(NVDIMM_BUS_INTEL_FW_ACTIVATE, acpi_mask);
2730 static void nfit_test1_setup(struct nfit_test *t)
2733 void *nfit_buf = t->nfit_buf;
2734 struct acpi_nfit_memory_map *memdev;
2735 struct acpi_nfit_control_region *dcr;
2736 struct acpi_nfit_system_address *spa;
2737 struct acpi_nfit_desc *acpi_desc;
2740 /* spa0 (flat range with no bdw aliasing) */
2741 spa = nfit_buf + offset;
2742 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2743 spa->header.length = sizeof(*spa);
2744 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
2745 spa->range_index = 0+1;
2746 spa->address = t->spa_set_dma[0];
2747 spa->length = SPA2_SIZE;
2748 offset += spa->header.length;
2750 /* virtual cd region */
2751 spa = nfit_buf + offset;
2752 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
2753 spa->header.length = sizeof(*spa);
2754 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_VCD), 16);
2755 spa->range_index = 0;
2756 spa->address = t->spa_set_dma[1];
2757 spa->length = SPA_VCD_SIZE;
2758 offset += spa->header.length;
2760 /* mem-region0 (spa0, dimm0) */
2761 memdev = nfit_buf + offset;
2762 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2763 memdev->header.length = sizeof(*memdev);
2764 memdev->device_handle = handle[5];
2765 memdev->physical_id = 0;
2766 memdev->region_id = 0;
2767 memdev->range_index = 0+1;
2768 memdev->region_index = 0+1;
2769 memdev->region_size = SPA2_SIZE;
2770 memdev->region_offset = 0;
2771 memdev->address = 0;
2772 memdev->interleave_index = 0;
2773 memdev->interleave_ways = 1;
2774 memdev->flags = ACPI_NFIT_MEM_SAVE_FAILED | ACPI_NFIT_MEM_RESTORE_FAILED
2775 | ACPI_NFIT_MEM_FLUSH_FAILED | ACPI_NFIT_MEM_HEALTH_OBSERVED
2776 | ACPI_NFIT_MEM_NOT_ARMED;
2777 offset += memdev->header.length;
2779 /* dcr-descriptor0 */
2780 dcr = nfit_buf + offset;
2781 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2782 dcr->header.length = offsetof(struct acpi_nfit_control_region,
2784 dcr->region_index = 0+1;
2785 dcr_common_init(dcr);
2786 dcr->serial_number = ~handle[5];
2787 dcr->code = NFIT_FIC_BYTE;
2789 offset += dcr->header.length;
2791 memdev = nfit_buf + offset;
2792 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
2793 memdev->header.length = sizeof(*memdev);
2794 memdev->device_handle = handle[6];
2795 memdev->physical_id = 0;
2796 memdev->region_id = 0;
2797 memdev->range_index = 0;
2798 memdev->region_index = 0+2;
2799 memdev->region_size = SPA2_SIZE;
2800 memdev->region_offset = 0;
2801 memdev->address = 0;
2802 memdev->interleave_index = 0;
2803 memdev->interleave_ways = 1;
2804 memdev->flags = ACPI_NFIT_MEM_MAP_FAILED;
2805 offset += memdev->header.length;
2807 /* dcr-descriptor1 */
2808 dcr = nfit_buf + offset;
2809 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
2810 dcr->header.length = offsetof(struct acpi_nfit_control_region,
2812 dcr->region_index = 0+2;
2813 dcr_common_init(dcr);
2814 dcr->serial_number = ~handle[6];
2815 dcr->code = NFIT_FIC_BYTE;
2817 offset += dcr->header.length;
2819 /* sanity check to make sure we've filled the buffer */
2820 WARN_ON(offset != t->nfit_size);
2822 t->nfit_filled = offset;
2824 post_ars_status(&t->ars_state, &t->badrange, t->spa_set_dma[0],
2827 acpi_desc = &t->acpi_desc;
2828 set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en);
2829 set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en);
2830 set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en);
2831 set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en);
2832 set_bit(ND_INTEL_ENABLE_LSS_STATUS, &acpi_desc->dimm_cmd_force_en);
2833 set_bit(ND_CMD_GET_CONFIG_SIZE, &acpi_desc->dimm_cmd_force_en);
2834 set_bit(ND_CMD_GET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
2835 set_bit(ND_CMD_SET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
2838 static int nfit_test_blk_do_io(struct nd_blk_region *ndbr, resource_size_t dpa,
2839 void *iobuf, u64 len, int rw)
2841 struct nfit_blk *nfit_blk = ndbr->blk_provider_data;
2842 struct nfit_blk_mmio *mmio = &nfit_blk->mmio[BDW];
2843 struct nd_region *nd_region = &ndbr->nd_region;
2846 lane = nd_region_acquire_lane(nd_region);
2848 memcpy(mmio->addr.base + dpa, iobuf, len);
2850 memcpy(iobuf, mmio->addr.base + dpa, len);
2852 /* give us some some coverage of the arch_invalidate_pmem() API */
2853 arch_invalidate_pmem(mmio->addr.base + dpa, len);
2855 nd_region_release_lane(nd_region, lane);
2860 static unsigned long nfit_ctl_handle;
2862 union acpi_object *result;
2864 static union acpi_object *nfit_test_evaluate_dsm(acpi_handle handle,
2865 const guid_t *guid, u64 rev, u64 func, union acpi_object *argv4)
2867 if (handle != &nfit_ctl_handle)
2868 return ERR_PTR(-ENXIO);
2873 static int setup_result(void *buf, size_t size)
2875 result = kmalloc(sizeof(union acpi_object) + size, GFP_KERNEL);
2878 result->package.type = ACPI_TYPE_BUFFER,
2879 result->buffer.pointer = (void *) (result + 1);
2880 result->buffer.length = size;
2881 memcpy(result->buffer.pointer, buf, size);
2882 memset(buf, 0, size);
2886 static int nfit_ctl_test(struct device *dev)
2889 struct nvdimm *nvdimm;
2890 struct acpi_device *adev;
2891 struct nfit_mem *nfit_mem;
2892 struct nd_ars_record *record;
2893 struct acpi_nfit_desc *acpi_desc;
2894 const u64 test_val = 0x0123456789abcdefULL;
2895 unsigned long mask, cmd_size, offset;
2896 struct nfit_ctl_test_cmd {
2897 struct nd_cmd_pkg pkg;
2899 struct nd_cmd_get_config_size cfg_size;
2900 struct nd_cmd_clear_error clear_err;
2901 struct nd_cmd_ars_status ars_stat;
2902 struct nd_cmd_ars_cap ars_cap;
2903 struct nd_intel_bus_fw_activate_businfo fwa_info;
2904 char buf[sizeof(struct nd_cmd_ars_status)
2905 + sizeof(struct nd_ars_record)];
2909 adev = devm_kzalloc(dev, sizeof(*adev), GFP_KERNEL);
2912 *adev = (struct acpi_device) {
2913 .handle = &nfit_ctl_handle,
2915 .init_name = "test-adev",
2919 acpi_desc = devm_kzalloc(dev, sizeof(*acpi_desc), GFP_KERNEL);
2922 *acpi_desc = (struct acpi_nfit_desc) {
2924 .cmd_mask = 1UL << ND_CMD_ARS_CAP
2925 | 1UL << ND_CMD_ARS_START
2926 | 1UL << ND_CMD_ARS_STATUS
2927 | 1UL << ND_CMD_CLEAR_ERROR
2928 | 1UL << ND_CMD_CALL,
2929 .module = THIS_MODULE,
2930 .provider_name = "ACPI.NFIT",
2931 .ndctl = acpi_nfit_ctl,
2932 .bus_family_mask = 1UL << NVDIMM_BUS_FAMILY_NFIT
2933 | 1UL << NVDIMM_BUS_FAMILY_INTEL,
2935 .bus_dsm_mask = 1UL << NFIT_CMD_TRANSLATE_SPA
2936 | 1UL << NFIT_CMD_ARS_INJECT_SET
2937 | 1UL << NFIT_CMD_ARS_INJECT_CLEAR
2938 | 1UL << NFIT_CMD_ARS_INJECT_GET,
2939 .family_dsm_mask[NVDIMM_BUS_FAMILY_INTEL] =
2940 NVDIMM_BUS_INTEL_FW_ACTIVATE_CMDMASK,
2944 nfit_mem = devm_kzalloc(dev, sizeof(*nfit_mem), GFP_KERNEL);
2948 mask = 1UL << ND_CMD_SMART | 1UL << ND_CMD_SMART_THRESHOLD
2949 | 1UL << ND_CMD_DIMM_FLAGS | 1UL << ND_CMD_GET_CONFIG_SIZE
2950 | 1UL << ND_CMD_GET_CONFIG_DATA | 1UL << ND_CMD_SET_CONFIG_DATA
2951 | 1UL << ND_CMD_VENDOR;
2952 *nfit_mem = (struct nfit_mem) {
2954 .family = NVDIMM_FAMILY_INTEL,
2958 nvdimm = devm_kzalloc(dev, sizeof(*nvdimm), GFP_KERNEL);
2961 *nvdimm = (struct nvdimm) {
2962 .provider_data = nfit_mem,
2965 .init_name = "test-dimm",
2970 /* basic checkout of a typical 'get config size' command */
2971 cmd_size = sizeof(cmd.cfg_size);
2972 cmd.cfg_size = (struct nd_cmd_get_config_size) {
2974 .config_size = SZ_128K,
2977 rc = setup_result(cmd.buf, cmd_size);
2980 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, nvdimm, ND_CMD_GET_CONFIG_SIZE,
2981 cmd.buf, cmd_size, &cmd_rc);
2983 if (rc < 0 || cmd_rc || cmd.cfg_size.status != 0
2984 || cmd.cfg_size.config_size != SZ_128K
2985 || cmd.cfg_size.max_xfer != SZ_4K) {
2986 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
2987 __func__, __LINE__, rc, cmd_rc);
2992 /* test ars_status with zero output */
2993 cmd_size = offsetof(struct nd_cmd_ars_status, address);
2994 cmd.ars_stat = (struct nd_cmd_ars_status) {
2997 rc = setup_result(cmd.buf, cmd_size);
3000 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS,
3001 cmd.buf, cmd_size, &cmd_rc);
3003 if (rc < 0 || cmd_rc) {
3004 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
3005 __func__, __LINE__, rc, cmd_rc);
3010 /* test ars_cap with benign extended status */
3011 cmd_size = sizeof(cmd.ars_cap);
3012 cmd.ars_cap = (struct nd_cmd_ars_cap) {
3013 .status = ND_ARS_PERSISTENT << 16,
3015 offset = offsetof(struct nd_cmd_ars_cap, status);
3016 rc = setup_result(cmd.buf + offset, cmd_size - offset);
3019 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_CAP,
3020 cmd.buf, cmd_size, &cmd_rc);
3022 if (rc < 0 || cmd_rc) {
3023 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
3024 __func__, __LINE__, rc, cmd_rc);
3029 /* test ars_status with 'status' trimmed from 'out_length' */
3030 cmd_size = sizeof(cmd.ars_stat) + sizeof(struct nd_ars_record);
3031 cmd.ars_stat = (struct nd_cmd_ars_status) {
3032 .out_length = cmd_size - 4,
3034 record = &cmd.ars_stat.records[0];
3035 *record = (struct nd_ars_record) {
3038 rc = setup_result(cmd.buf, cmd_size);
3041 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS,
3042 cmd.buf, cmd_size, &cmd_rc);
3044 if (rc < 0 || cmd_rc || record->length != test_val) {
3045 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
3046 __func__, __LINE__, rc, cmd_rc);
3051 /* test ars_status with 'Output (Size)' including 'status' */
3052 cmd_size = sizeof(cmd.ars_stat) + sizeof(struct nd_ars_record);
3053 cmd.ars_stat = (struct nd_cmd_ars_status) {
3054 .out_length = cmd_size,
3056 record = &cmd.ars_stat.records[0];
3057 *record = (struct nd_ars_record) {
3060 rc = setup_result(cmd.buf, cmd_size);
3063 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_ARS_STATUS,
3064 cmd.buf, cmd_size, &cmd_rc);
3066 if (rc < 0 || cmd_rc || record->length != test_val) {
3067 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
3068 __func__, __LINE__, rc, cmd_rc);
3073 /* test extended status for get_config_size results in failure */
3074 cmd_size = sizeof(cmd.cfg_size);
3075 cmd.cfg_size = (struct nd_cmd_get_config_size) {
3078 rc = setup_result(cmd.buf, cmd_size);
3081 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, nvdimm, ND_CMD_GET_CONFIG_SIZE,
3082 cmd.buf, cmd_size, &cmd_rc);
3084 if (rc < 0 || cmd_rc >= 0) {
3085 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
3086 __func__, __LINE__, rc, cmd_rc);
3090 /* test clear error */
3091 cmd_size = sizeof(cmd.clear_err);
3092 cmd.clear_err = (struct nd_cmd_clear_error) {
3096 rc = setup_result(cmd.buf, cmd_size);
3099 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_CLEAR_ERROR,
3100 cmd.buf, cmd_size, &cmd_rc);
3101 if (rc < 0 || cmd_rc) {
3102 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
3103 __func__, __LINE__, rc, cmd_rc);
3107 /* test firmware activate bus info */
3108 cmd_size = sizeof(cmd.fwa_info);
3109 cmd = (struct nfit_ctl_test_cmd) {
3111 .nd_command = NVDIMM_BUS_INTEL_FW_ACTIVATE_BUSINFO,
3112 .nd_family = NVDIMM_BUS_FAMILY_INTEL,
3113 .nd_size_out = cmd_size,
3114 .nd_fw_size = cmd_size,
3117 .state = ND_INTEL_FWA_IDLE,
3118 .capability = ND_INTEL_BUS_FWA_CAP_FWQUIESCE
3119 | ND_INTEL_BUS_FWA_CAP_OSQUIESCE,
3121 .cpu_quiesce_tmo = 1,
3122 .io_quiesce_tmo = 1,
3123 .max_quiesce_tmo = 1,
3126 rc = setup_result(cmd.buf, cmd_size);
3129 rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_CALL,
3130 &cmd, sizeof(cmd.pkg) + cmd_size, &cmd_rc);
3131 if (rc < 0 || cmd_rc) {
3132 dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
3133 __func__, __LINE__, rc, cmd_rc);
3140 static int nfit_test_probe(struct platform_device *pdev)
3142 struct nvdimm_bus_descriptor *nd_desc;
3143 struct acpi_nfit_desc *acpi_desc;
3144 struct device *dev = &pdev->dev;
3145 struct nfit_test *nfit_test;
3146 struct nfit_mem *nfit_mem;
3147 union acpi_object *obj;
3150 if (strcmp(dev_name(&pdev->dev), "nfit_test.0") == 0) {
3151 rc = nfit_ctl_test(&pdev->dev);
3156 nfit_test = to_nfit_test(&pdev->dev);
3159 if (nfit_test->num_dcr) {
3160 int num = nfit_test->num_dcr;
3162 nfit_test->dimm = devm_kcalloc(dev, num, sizeof(void *),
3164 nfit_test->dimm_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t),
3166 nfit_test->flush = devm_kcalloc(dev, num, sizeof(void *),
3168 nfit_test->flush_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t),
3170 nfit_test->label = devm_kcalloc(dev, num, sizeof(void *),
3172 nfit_test->label_dma = devm_kcalloc(dev, num,
3173 sizeof(dma_addr_t), GFP_KERNEL);
3174 nfit_test->dcr = devm_kcalloc(dev, num,
3175 sizeof(struct nfit_test_dcr *), GFP_KERNEL);
3176 nfit_test->dcr_dma = devm_kcalloc(dev, num,
3177 sizeof(dma_addr_t), GFP_KERNEL);
3178 nfit_test->smart = devm_kcalloc(dev, num,
3179 sizeof(struct nd_intel_smart), GFP_KERNEL);
3180 nfit_test->smart_threshold = devm_kcalloc(dev, num,
3181 sizeof(struct nd_intel_smart_threshold),
3183 nfit_test->fw = devm_kcalloc(dev, num,
3184 sizeof(struct nfit_test_fw), GFP_KERNEL);
3185 if (nfit_test->dimm && nfit_test->dimm_dma && nfit_test->label
3186 && nfit_test->label_dma && nfit_test->dcr
3187 && nfit_test->dcr_dma && nfit_test->flush
3188 && nfit_test->flush_dma
3195 if (nfit_test->num_pm) {
3196 int num = nfit_test->num_pm;
3198 nfit_test->spa_set = devm_kcalloc(dev, num, sizeof(void *),
3200 nfit_test->spa_set_dma = devm_kcalloc(dev, num,
3201 sizeof(dma_addr_t), GFP_KERNEL);
3202 if (nfit_test->spa_set && nfit_test->spa_set_dma)
3208 /* per-nfit specific alloc */
3209 if (nfit_test->alloc(nfit_test))
3212 nfit_test->setup(nfit_test);
3213 acpi_desc = &nfit_test->acpi_desc;
3214 acpi_nfit_desc_init(acpi_desc, &pdev->dev);
3215 acpi_desc->blk_do_io = nfit_test_blk_do_io;
3216 nd_desc = &acpi_desc->nd_desc;
3217 nd_desc->provider_name = NULL;
3218 nd_desc->module = THIS_MODULE;
3219 nd_desc->ndctl = nfit_test_ctl;
3221 rc = acpi_nfit_init(acpi_desc, nfit_test->nfit_buf,
3222 nfit_test->nfit_filled);
3226 rc = devm_add_action_or_reset(&pdev->dev, acpi_nfit_shutdown, acpi_desc);
3230 if (nfit_test->setup != nfit_test0_setup)
3233 nfit_test->setup_hotplug = 1;
3234 nfit_test->setup(nfit_test);
3236 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3239 obj->type = ACPI_TYPE_BUFFER;
3240 obj->buffer.length = nfit_test->nfit_size;
3241 obj->buffer.pointer = nfit_test->nfit_buf;
3242 *(nfit_test->_fit) = obj;
3243 __acpi_nfit_notify(&pdev->dev, nfit_test, 0x80);
3245 /* associate dimm devices with nfit_mem data for notification testing */
3246 mutex_lock(&acpi_desc->init_mutex);
3247 list_for_each_entry(nfit_mem, &acpi_desc->dimms, list) {
3248 u32 nfit_handle = __to_nfit_memdev(nfit_mem)->device_handle;
3251 for (i = 0; i < ARRAY_SIZE(handle); i++)
3252 if (nfit_handle == handle[i])
3253 dev_set_drvdata(nfit_test->dimm_dev[i],
3256 mutex_unlock(&acpi_desc->init_mutex);
3261 static int nfit_test_remove(struct platform_device *pdev)
3266 static void nfit_test_release(struct device *dev)
3268 struct nfit_test *nfit_test = to_nfit_test(dev);
3273 static const struct platform_device_id nfit_test_id[] = {
3278 static struct platform_driver nfit_test_driver = {
3279 .probe = nfit_test_probe,
3280 .remove = nfit_test_remove,
3282 .name = KBUILD_MODNAME,
3284 .id_table = nfit_test_id,
3287 static char copy_mc_buf[PAGE_SIZE] __attribute__((__aligned__(PAGE_SIZE)));
3295 static void copy_mc_test_init(char *dst, char *src, size_t size)
3299 memset(dst, 0xff, size);
3300 for (i = 0; i < size; i++)
3304 static bool copy_mc_test_validate(unsigned char *dst, unsigned char *src,
3305 size_t size, unsigned long rem)
3309 for (i = 0; i < size - rem; i++)
3310 if (dst[i] != (unsigned char) i) {
3311 pr_info_once("%s:%d: offset: %zd got: %#x expect: %#x\n",
3312 __func__, __LINE__, i, dst[i],
3316 for (i = size - rem; i < size; i++)
3317 if (dst[i] != 0xffU) {
3318 pr_info_once("%s:%d: offset: %zd got: %#x expect: 0xff\n",
3319 __func__, __LINE__, i, dst[i]);
3325 void copy_mc_test(void)
3327 char *inject_desc[] = { "none", "source", "destination" };
3330 if (IS_ENABLED(CONFIG_COPY_MC_TEST)) {
3331 pr_info("%s: run...\n", __func__);
3333 pr_info("%s: disabled, skip.\n", __func__);
3337 for (inj = INJECT_NONE; inj <= INJECT_DST; inj++) {
3340 pr_info("%s: inject: %s\n", __func__, inject_desc[inj]);
3341 for (i = 0; i < 512; i++) {
3342 unsigned long expect, rem;
3348 copy_mc_inject_src(NULL);
3349 copy_mc_inject_dst(NULL);
3350 dst = ©_mc_buf[2048];
3351 src = ©_mc_buf[1024 - i];
3355 copy_mc_inject_src(©_mc_buf[1024]);
3356 copy_mc_inject_dst(NULL);
3357 dst = ©_mc_buf[2048];
3358 src = ©_mc_buf[1024 - i];
3362 copy_mc_inject_src(NULL);
3363 copy_mc_inject_dst(©_mc_buf[2048]);
3364 dst = ©_mc_buf[2048 - i];
3365 src = ©_mc_buf[1024];
3370 copy_mc_test_init(dst, src, 512);
3371 rem = copy_mc_fragile(dst, src, 512);
3372 valid = copy_mc_test_validate(dst, src, 512, expect);
3373 if (rem == expect && valid)
3375 pr_info("%s: copy(%#lx, %#lx, %d) off: %d rem: %ld %s expect: %ld\n",
3377 ((unsigned long) dst) & ~PAGE_MASK,
3378 ((unsigned long ) src) & ~PAGE_MASK,
3379 512, i, rem, valid ? "valid" : "bad",
3384 copy_mc_inject_src(NULL);
3385 copy_mc_inject_dst(NULL);
3388 static __init int nfit_test_init(void)
3398 dax_pmem_core_test();
3399 #ifdef CONFIG_DEV_DAX_PMEM_COMPAT
3400 dax_pmem_compat_test();
3403 nfit_test_setup(nfit_test_lookup, nfit_test_evaluate_dsm);
3405 nfit_wq = create_singlethread_workqueue("nfit");
3409 nfit_test_dimm = class_create(THIS_MODULE, "nfit_test_dimm");
3410 if (IS_ERR(nfit_test_dimm)) {
3411 rc = PTR_ERR(nfit_test_dimm);
3415 nfit_pool = gen_pool_create(ilog2(SZ_4M), NUMA_NO_NODE);
3421 if (gen_pool_add(nfit_pool, SZ_4G, SZ_4G, NUMA_NO_NODE)) {
3426 for (i = 0; i < NUM_NFITS; i++) {
3427 struct nfit_test *nfit_test;
3428 struct platform_device *pdev;
3430 nfit_test = kzalloc(sizeof(*nfit_test), GFP_KERNEL);
3435 INIT_LIST_HEAD(&nfit_test->resources);
3436 badrange_init(&nfit_test->badrange);
3439 nfit_test->num_pm = NUM_PM;
3440 nfit_test->dcr_idx = 0;
3441 nfit_test->num_dcr = NUM_DCR;
3442 nfit_test->alloc = nfit_test0_alloc;
3443 nfit_test->setup = nfit_test0_setup;
3446 nfit_test->num_pm = 2;
3447 nfit_test->dcr_idx = NUM_DCR;
3448 nfit_test->num_dcr = 2;
3449 nfit_test->alloc = nfit_test1_alloc;
3450 nfit_test->setup = nfit_test1_setup;
3456 pdev = &nfit_test->pdev;
3457 pdev->name = KBUILD_MODNAME;
3459 pdev->dev.release = nfit_test_release;
3460 rc = platform_device_register(pdev);
3462 put_device(&pdev->dev);
3465 get_device(&pdev->dev);
3467 rc = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3471 instances[i] = nfit_test;
3472 INIT_WORK(&nfit_test->work, uc_error_notify);
3475 rc = platform_driver_register(&nfit_test_driver);
3482 gen_pool_destroy(nfit_pool);
3484 destroy_workqueue(nfit_wq);
3485 for (i = 0; i < NUM_NFITS; i++)
3487 platform_device_unregister(&instances[i]->pdev);
3488 nfit_test_teardown();
3489 for (i = 0; i < NUM_NFITS; i++)
3491 put_device(&instances[i]->pdev.dev);
3496 static __exit void nfit_test_exit(void)
3500 flush_workqueue(nfit_wq);
3501 destroy_workqueue(nfit_wq);
3502 for (i = 0; i < NUM_NFITS; i++)
3503 platform_device_unregister(&instances[i]->pdev);
3504 platform_driver_unregister(&nfit_test_driver);
3505 nfit_test_teardown();
3507 gen_pool_destroy(nfit_pool);
3509 for (i = 0; i < NUM_NFITS; i++)
3510 put_device(&instances[i]->pdev.dev);
3511 class_destroy(nfit_test_dimm);
3514 module_init(nfit_test_init);
3515 module_exit(nfit_test_exit);
3516 MODULE_LICENSE("GPL v2");
3517 MODULE_AUTHOR("Intel Corporation");