2 * turbostat -- show CPU frequency and C-state residency
3 * on modern Intel turbo-capable processors.
5 * Copyright (c) 2013 Intel Corporation.
6 * Len Brown <len.brown@intel.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
24 #include INTEL_FAMILY_HEADER
29 #include <sys/types.h>
32 #include <sys/resource.h>
44 #include <linux/capability.h>
47 char *proc_stat = "/proc/stat";
50 struct timespec interval_ts = {5, 0};
53 unsigned int sums_need_wide_columns;
54 unsigned int rapl_joules;
55 unsigned int summary_only;
56 unsigned int list_header_only;
57 unsigned int dump_only;
58 unsigned int do_snb_cstates;
59 unsigned int do_knl_cstates;
60 unsigned int do_slm_cstates;
61 unsigned int use_c1_residency_msr;
62 unsigned int has_aperf;
64 unsigned int do_irtl_snb;
65 unsigned int do_irtl_hsw;
66 unsigned int units = 1000000; /* MHz etc */
67 unsigned int genuine_intel;
68 unsigned int has_invariant_tsc;
69 unsigned int do_nhm_platform_info;
70 unsigned int no_MSR_MISC_PWR_MGMT;
71 unsigned int aperf_mperf_multiplier = 1;
74 unsigned int has_base_hz;
75 double tsc_tweak = 1.0;
76 unsigned int show_pkg_only;
77 unsigned int show_core_only;
78 char *output_buffer, *outp;
82 unsigned long long gfx_cur_rc6_ms;
83 unsigned int gfx_cur_mhz;
84 unsigned int tcc_activation_temp;
85 unsigned int tcc_activation_temp_override;
86 double rapl_power_units, rapl_time_units;
87 double rapl_dram_energy_units, rapl_energy_units;
88 double rapl_joule_counter_range;
89 unsigned int do_core_perf_limit_reasons;
90 unsigned int do_gfx_perf_limit_reasons;
91 unsigned int do_ring_perf_limit_reasons;
92 unsigned int crystal_hz;
93 unsigned long long tsc_hz;
95 double discover_bclk(unsigned int family, unsigned int model);
96 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */
97 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */
98 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */
99 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */
100 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */
101 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */
102 unsigned int has_misc_feature_control;
104 #define RAPL_PKG (1 << 0)
105 /* 0x610 MSR_PKG_POWER_LIMIT */
106 /* 0x611 MSR_PKG_ENERGY_STATUS */
107 #define RAPL_PKG_PERF_STATUS (1 << 1)
108 /* 0x613 MSR_PKG_PERF_STATUS */
109 #define RAPL_PKG_POWER_INFO (1 << 2)
110 /* 0x614 MSR_PKG_POWER_INFO */
112 #define RAPL_DRAM (1 << 3)
113 /* 0x618 MSR_DRAM_POWER_LIMIT */
114 /* 0x619 MSR_DRAM_ENERGY_STATUS */
115 #define RAPL_DRAM_PERF_STATUS (1 << 4)
116 /* 0x61b MSR_DRAM_PERF_STATUS */
117 #define RAPL_DRAM_POWER_INFO (1 << 5)
118 /* 0x61c MSR_DRAM_POWER_INFO */
120 #define RAPL_CORES_POWER_LIMIT (1 << 6)
121 /* 0x638 MSR_PP0_POWER_LIMIT */
122 #define RAPL_CORE_POLICY (1 << 7)
123 /* 0x63a MSR_PP0_POLICY */
125 #define RAPL_GFX (1 << 8)
126 /* 0x640 MSR_PP1_POWER_LIMIT */
127 /* 0x641 MSR_PP1_ENERGY_STATUS */
128 /* 0x642 MSR_PP1_POLICY */
130 #define RAPL_CORES_ENERGY_STATUS (1 << 9)
131 /* 0x639 MSR_PP0_ENERGY_STATUS */
132 #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT)
133 #define TJMAX_DEFAULT 100
135 #define MAX(a, b) ((a) > (b) ? (a) : (b))
138 * buffer size used by sscanf() for added column names
139 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters
141 #define NAME_BYTES 20
142 #define PATH_BYTES 128
147 #define CPU_SUBSET_MAXCPUS 1024 /* need to use before probe... */
148 cpu_set_t *cpu_present_set, *cpu_affinity_set, *cpu_subset;
149 size_t cpu_present_setsize, cpu_affinity_setsize, cpu_subset_size;
150 #define MAX_ADDED_COUNTERS 16
153 struct timeval tv_begin;
154 struct timeval tv_end;
155 unsigned long long tsc;
156 unsigned long long aperf;
157 unsigned long long mperf;
158 unsigned long long c1;
159 unsigned long long irq_count;
160 unsigned int smi_count;
163 #define CPU_IS_FIRST_THREAD_IN_CORE 0x2
164 #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4
165 unsigned long long counter[MAX_ADDED_COUNTERS];
166 } *thread_even, *thread_odd;
169 unsigned long long c3;
170 unsigned long long c6;
171 unsigned long long c7;
172 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */
173 unsigned int core_temp_c;
174 unsigned int core_id;
175 unsigned long long counter[MAX_ADDED_COUNTERS];
176 } *core_even, *core_odd;
179 unsigned long long pc2;
180 unsigned long long pc3;
181 unsigned long long pc6;
182 unsigned long long pc7;
183 unsigned long long pc8;
184 unsigned long long pc9;
185 unsigned long long pc10;
186 unsigned long long pkg_wtd_core_c0;
187 unsigned long long pkg_any_core_c0;
188 unsigned long long pkg_any_gfxe_c0;
189 unsigned long long pkg_both_core_gfxe_c0;
190 long long gfx_rc6_ms;
191 unsigned int gfx_mhz;
192 unsigned int package_id;
193 unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */
194 unsigned int energy_dram; /* MSR_DRAM_ENERGY_STATUS */
195 unsigned int energy_cores; /* MSR_PP0_ENERGY_STATUS */
196 unsigned int energy_gfx; /* MSR_PP1_ENERGY_STATUS */
197 unsigned int rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */
198 unsigned int rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */
199 unsigned int pkg_temp_c;
200 unsigned long long counter[MAX_ADDED_COUNTERS];
201 } *package_even, *package_odd;
203 #define ODD_COUNTERS thread_odd, core_odd, package_odd
204 #define EVEN_COUNTERS thread_even, core_even, package_even
206 #define GET_THREAD(thread_base, thread_no, core_no, pkg_no) \
207 (thread_base + (pkg_no) * topo.num_cores_per_pkg * \
208 topo.num_threads_per_core + \
209 (core_no) * topo.num_threads_per_core + (thread_no))
210 #define GET_CORE(core_base, core_no, pkg_no) \
211 (core_base + (pkg_no) * topo.num_cores_per_pkg + (core_no))
212 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no)
214 enum counter_scope {SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE};
215 enum counter_type {COUNTER_ITEMS, COUNTER_CYCLES, COUNTER_SECONDS, COUNTER_USEC};
216 enum counter_format {FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT};
219 unsigned int msr_num;
220 char name[NAME_BYTES];
221 char path[PATH_BYTES];
223 enum counter_type type;
224 enum counter_format format;
225 struct msr_counter *next;
227 #define FLAGS_HIDE (1 << 0)
228 #define FLAGS_SHOW (1 << 1)
229 #define SYSFS_PERCPU (1 << 1)
232 struct sys_counters {
233 unsigned int added_thread_counters;
234 unsigned int added_core_counters;
235 unsigned int added_package_counters;
236 struct msr_counter *tp;
237 struct msr_counter *cp;
238 struct msr_counter *pp;
241 struct system_summary {
242 struct thread_data threads;
243 struct core_data cores;
244 struct pkg_data packages;
253 int num_cores_per_pkg;
254 int num_threads_per_core;
257 struct timeval tv_even, tv_odd, tv_delta;
259 int *irq_column_2_cpu; /* /proc/interrupts column numbers */
260 int *irqs_per_cpu; /* indexed by cpu_num */
262 void setup_all_buffers(void);
264 int cpu_is_not_present(int cpu)
266 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set);
269 * run func(thread, core, package) in topology order
270 * skip non-present cpus
273 int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *),
274 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base)
276 int retval, pkg_no, core_no, thread_no;
278 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
279 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) {
280 for (thread_no = 0; thread_no <
281 topo.num_threads_per_core; ++thread_no) {
282 struct thread_data *t;
286 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no);
288 if (cpu_is_not_present(t->cpu_id))
291 c = GET_CORE(core_base, core_no, pkg_no);
292 p = GET_PKG(pkg_base, pkg_no);
294 retval = func(t, c, p);
303 int cpu_migrate(int cpu)
305 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
306 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set);
307 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1)
312 int get_msr_fd(int cpu)
322 sprintf(pathname, "/dev/cpu/%d/msr", cpu);
323 fd = open(pathname, O_RDONLY);
325 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname);
332 int get_msr(int cpu, off_t offset, unsigned long long *msr)
336 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset);
338 if (retval != sizeof *msr)
339 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset);
345 * Each string in this array is compared in --show and --hide cmdline.
346 * Thus, strings that are proper sub-sets must follow their more specific peers.
348 struct msr_counter bic[] = {
354 { 0x0, "SMI", "", 32, 0, FORMAT_DELTA, NULL},
396 #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter))
397 #define BIC_Package (1ULL << 0)
398 #define BIC_Avg_MHz (1ULL << 1)
399 #define BIC_Bzy_MHz (1ULL << 2)
400 #define BIC_TSC_MHz (1ULL << 3)
401 #define BIC_IRQ (1ULL << 4)
402 #define BIC_SMI (1ULL << 5)
403 #define BIC_Busy (1ULL << 6)
404 #define BIC_CPU_c1 (1ULL << 7)
405 #define BIC_CPU_c3 (1ULL << 8)
406 #define BIC_CPU_c6 (1ULL << 9)
407 #define BIC_CPU_c7 (1ULL << 10)
408 #define BIC_ThreadC (1ULL << 11)
409 #define BIC_CoreTmp (1ULL << 12)
410 #define BIC_CoreCnt (1ULL << 13)
411 #define BIC_PkgTmp (1ULL << 14)
412 #define BIC_GFX_rc6 (1ULL << 15)
413 #define BIC_GFXMHz (1ULL << 16)
414 #define BIC_Pkgpc2 (1ULL << 17)
415 #define BIC_Pkgpc3 (1ULL << 18)
416 #define BIC_Pkgpc6 (1ULL << 19)
417 #define BIC_Pkgpc7 (1ULL << 20)
418 #define BIC_Pkgpc8 (1ULL << 21)
419 #define BIC_Pkgpc9 (1ULL << 22)
420 #define BIC_Pkgpc10 (1ULL << 23)
421 #define BIC_PkgWatt (1ULL << 24)
422 #define BIC_CorWatt (1ULL << 25)
423 #define BIC_GFXWatt (1ULL << 26)
424 #define BIC_PkgCnt (1ULL << 27)
425 #define BIC_RAMWatt (1ULL << 28)
426 #define BIC_PKG__ (1ULL << 29)
427 #define BIC_RAM__ (1ULL << 30)
428 #define BIC_Pkg_J (1ULL << 31)
429 #define BIC_Cor_J (1ULL << 32)
430 #define BIC_GFX_J (1ULL << 33)
431 #define BIC_RAM_J (1ULL << 34)
432 #define BIC_Core (1ULL << 35)
433 #define BIC_CPU (1ULL << 36)
434 #define BIC_Mod_c6 (1ULL << 37)
435 #define BIC_sysfs (1ULL << 38)
436 #define BIC_Totl_c0 (1ULL << 39)
437 #define BIC_Any_c0 (1ULL << 40)
438 #define BIC_GFX_c0 (1ULL << 41)
439 #define BIC_CPUGFX (1ULL << 42)
441 unsigned long long bic_enabled = 0xFFFFFFFFFFFFFFFFULL;
442 unsigned long long bic_present = BIC_sysfs;
444 #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME)
445 #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT)
446 #define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT)
448 #define MAX_DEFERRED 16
449 char *deferred_skip_names[MAX_DEFERRED];
450 int deferred_skip_index;
453 * HIDE_LIST - hide this list of counters, show the rest [default]
454 * SHOW_LIST - show this list of counters, hide the rest
456 enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST;
461 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n"
463 "Turbostat forks the specified COMMAND and prints statistics\n"
464 "when COMMAND completes.\n"
465 "If no COMMAND is specified, turbostat wakes every 5-seconds\n"
466 "to print statistics, until interrupted.\n"
467 "--add add a counter\n"
468 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n"
469 "--cpu cpu-set limit output to summary plus cpu-set:\n"
470 " {core | package | j,k,l..m,n-p }\n"
471 "--quiet skip decoding system configuration header\n"
472 "--interval sec Override default 5-second measurement interval\n"
473 "--help print this help message\n"
474 "--list list column headers only\n"
475 "--out file create or truncate \"file\" for all output\n"
476 "--version print version information\n"
478 "For more help, run \"man turbostat\"\n");
483 * for all the strings in comma separate name_list,
484 * set the approprate bit in return value.
486 unsigned long long bic_lookup(char *name_list, enum show_hide_mode mode)
489 unsigned long long retval = 0;
494 comma = strchr(name_list, ',');
499 for (i = 0; i < MAX_BIC; ++i) {
500 if (!strcmp(name_list, bic[i].name)) {
501 retval |= (1ULL << i);
506 if (mode == SHOW_LIST) {
507 fprintf(stderr, "Invalid counter name: %s\n", name_list);
510 deferred_skip_names[deferred_skip_index++] = name_list;
512 fprintf(stderr, "deferred \"%s\"\n", name_list);
513 if (deferred_skip_index >= MAX_DEFERRED) {
514 fprintf(stderr, "More than max %d un-recognized --skip options '%s'\n",
515 MAX_DEFERRED, name_list);
530 void print_header(char *delim)
532 struct msr_counter *mp;
536 outp += sprintf(outp, "usec %s", delim);
537 if (DO_BIC(BIC_Package))
538 outp += sprintf(outp, "%sPackage", (printed++ ? delim : ""));
539 if (DO_BIC(BIC_Core))
540 outp += sprintf(outp, "%sCore", (printed++ ? delim : ""));
542 outp += sprintf(outp, "%sCPU", (printed++ ? delim : ""));
543 if (DO_BIC(BIC_Avg_MHz))
544 outp += sprintf(outp, "%sAvg_MHz", (printed++ ? delim : ""));
545 if (DO_BIC(BIC_Busy))
546 outp += sprintf(outp, "%sBusy%%", (printed++ ? delim : ""));
547 if (DO_BIC(BIC_Bzy_MHz))
548 outp += sprintf(outp, "%sBzy_MHz", (printed++ ? delim : ""));
549 if (DO_BIC(BIC_TSC_MHz))
550 outp += sprintf(outp, "%sTSC_MHz", (printed++ ? delim : ""));
552 if (DO_BIC(BIC_IRQ)) {
553 if (sums_need_wide_columns)
554 outp += sprintf(outp, "%s IRQ", (printed++ ? delim : ""));
556 outp += sprintf(outp, "%sIRQ", (printed++ ? delim : ""));
560 outp += sprintf(outp, "%sSMI", (printed++ ? delim : ""));
562 for (mp = sys.tp; mp; mp = mp->next) {
564 if (mp->format == FORMAT_RAW) {
566 outp += sprintf(outp, "%s%18.18s", (printed++ ? delim : ""), mp->name);
568 outp += sprintf(outp, "%s%10.10s", (printed++ ? delim : ""), mp->name);
570 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
571 outp += sprintf(outp, "%s%8s", (printed++ ? delim : ""), mp->name);
573 outp += sprintf(outp, "%s%s", (printed++ ? delim : ""), mp->name);
577 if (DO_BIC(BIC_CPU_c1))
578 outp += sprintf(outp, "%sCPU%%c1", (printed++ ? delim : ""));
579 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates)
580 outp += sprintf(outp, "%sCPU%%c3", (printed++ ? delim : ""));
581 if (DO_BIC(BIC_CPU_c6))
582 outp += sprintf(outp, "%sCPU%%c6", (printed++ ? delim : ""));
583 if (DO_BIC(BIC_CPU_c7))
584 outp += sprintf(outp, "%sCPU%%c7", (printed++ ? delim : ""));
586 if (DO_BIC(BIC_Mod_c6))
587 outp += sprintf(outp, "%sMod%%c6", (printed++ ? delim : ""));
589 if (DO_BIC(BIC_CoreTmp))
590 outp += sprintf(outp, "%sCoreTmp", (printed++ ? delim : ""));
592 for (mp = sys.cp; mp; mp = mp->next) {
593 if (mp->format == FORMAT_RAW) {
595 outp += sprintf(outp, "%s%18.18s", delim, mp->name);
597 outp += sprintf(outp, "%s%10.10s", delim, mp->name);
599 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
600 outp += sprintf(outp, "%s%8s", delim, mp->name);
602 outp += sprintf(outp, "%s%s", delim, mp->name);
606 if (DO_BIC(BIC_PkgTmp))
607 outp += sprintf(outp, "%sPkgTmp", (printed++ ? delim : ""));
609 if (DO_BIC(BIC_GFX_rc6))
610 outp += sprintf(outp, "%sGFX%%rc6", (printed++ ? delim : ""));
612 if (DO_BIC(BIC_GFXMHz))
613 outp += sprintf(outp, "%sGFXMHz", (printed++ ? delim : ""));
615 if (DO_BIC(BIC_Totl_c0))
616 outp += sprintf(outp, "%sTotl%%C0", (printed++ ? delim : ""));
617 if (DO_BIC(BIC_Any_c0))
618 outp += sprintf(outp, "%sAny%%C0", (printed++ ? delim : ""));
619 if (DO_BIC(BIC_GFX_c0))
620 outp += sprintf(outp, "%sGFX%%C0", (printed++ ? delim : ""));
621 if (DO_BIC(BIC_CPUGFX))
622 outp += sprintf(outp, "%sCPUGFX%%", (printed++ ? delim : ""));
624 if (DO_BIC(BIC_Pkgpc2))
625 outp += sprintf(outp, "%sPkg%%pc2", (printed++ ? delim : ""));
626 if (DO_BIC(BIC_Pkgpc3))
627 outp += sprintf(outp, "%sPkg%%pc3", (printed++ ? delim : ""));
628 if (DO_BIC(BIC_Pkgpc6))
629 outp += sprintf(outp, "%sPkg%%pc6", (printed++ ? delim : ""));
630 if (DO_BIC(BIC_Pkgpc7))
631 outp += sprintf(outp, "%sPkg%%pc7", (printed++ ? delim : ""));
632 if (DO_BIC(BIC_Pkgpc8))
633 outp += sprintf(outp, "%sPkg%%pc8", (printed++ ? delim : ""));
634 if (DO_BIC(BIC_Pkgpc9))
635 outp += sprintf(outp, "%sPkg%%pc9", (printed++ ? delim : ""));
636 if (DO_BIC(BIC_Pkgpc10))
637 outp += sprintf(outp, "%sPk%%pc10", (printed++ ? delim : ""));
639 if (do_rapl && !rapl_joules) {
640 if (DO_BIC(BIC_PkgWatt))
641 outp += sprintf(outp, "%sPkgWatt", (printed++ ? delim : ""));
642 if (DO_BIC(BIC_CorWatt))
643 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : ""));
644 if (DO_BIC(BIC_GFXWatt))
645 outp += sprintf(outp, "%sGFXWatt", (printed++ ? delim : ""));
646 if (DO_BIC(BIC_RAMWatt))
647 outp += sprintf(outp, "%sRAMWatt", (printed++ ? delim : ""));
648 if (DO_BIC(BIC_PKG__))
649 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : ""));
650 if (DO_BIC(BIC_RAM__))
651 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : ""));
652 } else if (do_rapl && rapl_joules) {
653 if (DO_BIC(BIC_Pkg_J))
654 outp += sprintf(outp, "%sPkg_J", (printed++ ? delim : ""));
655 if (DO_BIC(BIC_Cor_J))
656 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : ""));
657 if (DO_BIC(BIC_GFX_J))
658 outp += sprintf(outp, "%sGFX_J", (printed++ ? delim : ""));
659 if (DO_BIC(BIC_RAM_J))
660 outp += sprintf(outp, "%sRAM_J", (printed++ ? delim : ""));
661 if (DO_BIC(BIC_PKG__))
662 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : ""));
663 if (DO_BIC(BIC_RAM__))
664 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : ""));
666 for (mp = sys.pp; mp; mp = mp->next) {
667 if (mp->format == FORMAT_RAW) {
669 outp += sprintf(outp, "%s%18.18s", delim, mp->name);
671 outp += sprintf(outp, "%s%10.10s", delim, mp->name);
673 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
674 outp += sprintf(outp, "%s%8s", delim, mp->name);
676 outp += sprintf(outp, "%s%s", delim, mp->name);
680 outp += sprintf(outp, "\n");
683 int dump_counters(struct thread_data *t, struct core_data *c,
687 struct msr_counter *mp;
689 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p);
692 outp += sprintf(outp, "CPU: %d flags 0x%x\n",
693 t->cpu_id, t->flags);
694 outp += sprintf(outp, "TSC: %016llX\n", t->tsc);
695 outp += sprintf(outp, "aperf: %016llX\n", t->aperf);
696 outp += sprintf(outp, "mperf: %016llX\n", t->mperf);
697 outp += sprintf(outp, "c1: %016llX\n", t->c1);
700 outp += sprintf(outp, "IRQ: %lld\n", t->irq_count);
702 outp += sprintf(outp, "SMI: %d\n", t->smi_count);
704 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
705 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n",
706 i, mp->msr_num, t->counter[i]);
711 outp += sprintf(outp, "core: %d\n", c->core_id);
712 outp += sprintf(outp, "c3: %016llX\n", c->c3);
713 outp += sprintf(outp, "c6: %016llX\n", c->c6);
714 outp += sprintf(outp, "c7: %016llX\n", c->c7);
715 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c);
717 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
718 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n",
719 i, mp->msr_num, c->counter[i]);
721 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us);
725 outp += sprintf(outp, "package: %d\n", p->package_id);
727 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0);
728 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0);
729 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0);
730 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0);
732 outp += sprintf(outp, "pc2: %016llX\n", p->pc2);
733 if (DO_BIC(BIC_Pkgpc3))
734 outp += sprintf(outp, "pc3: %016llX\n", p->pc3);
735 if (DO_BIC(BIC_Pkgpc6))
736 outp += sprintf(outp, "pc6: %016llX\n", p->pc6);
737 if (DO_BIC(BIC_Pkgpc7))
738 outp += sprintf(outp, "pc7: %016llX\n", p->pc7);
739 outp += sprintf(outp, "pc8: %016llX\n", p->pc8);
740 outp += sprintf(outp, "pc9: %016llX\n", p->pc9);
741 outp += sprintf(outp, "pc10: %016llX\n", p->pc10);
742 outp += sprintf(outp, "Joules PKG: %0X\n", p->energy_pkg);
743 outp += sprintf(outp, "Joules COR: %0X\n", p->energy_cores);
744 outp += sprintf(outp, "Joules GFX: %0X\n", p->energy_gfx);
745 outp += sprintf(outp, "Joules RAM: %0X\n", p->energy_dram);
746 outp += sprintf(outp, "Throttle PKG: %0X\n",
747 p->rapl_pkg_perf_status);
748 outp += sprintf(outp, "Throttle RAM: %0X\n",
749 p->rapl_dram_perf_status);
750 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c);
752 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
753 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n",
754 i, mp->msr_num, p->counter[i]);
758 outp += sprintf(outp, "\n");
764 * column formatting convention & formats
766 int format_counters(struct thread_data *t, struct core_data *c,
769 double interval_float, tsc;
772 struct msr_counter *mp;
776 /* if showing only 1st thread in core and this isn't one, bail out */
777 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
780 /* if showing only 1st thread in pkg and this isn't one, bail out */
781 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
784 /*if not summary line and --cpu is used */
785 if ((t != &average.threads) &&
786 (cpu_subset && !CPU_ISSET_S(t->cpu_id, cpu_subset_size, cpu_subset)))
790 /* on each row, print how many usec each timestamp took to gather */
793 timersub(&t->tv_end, &t->tv_begin, &tv);
794 outp += sprintf(outp, "%5ld\t", tv.tv_sec * 1000000 + tv.tv_usec);
797 interval_float = tv_delta.tv_sec + tv_delta.tv_usec/1000000.0;
799 tsc = t->tsc * tsc_tweak;
801 /* topo columns, print blanks on 1st (average) line */
802 if (t == &average.threads) {
803 if (DO_BIC(BIC_Package))
804 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
805 if (DO_BIC(BIC_Core))
806 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
808 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
810 if (DO_BIC(BIC_Package)) {
812 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->package_id);
814 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
816 if (DO_BIC(BIC_Core)) {
818 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_id);
820 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
823 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->cpu_id);
826 if (DO_BIC(BIC_Avg_MHz))
827 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""),
828 1.0 / units * t->aperf / interval_float);
830 if (DO_BIC(BIC_Busy))
831 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->mperf/tsc);
833 if (DO_BIC(BIC_Bzy_MHz)) {
835 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), base_hz / units * t->aperf / t->mperf);
837 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""),
838 tsc / units * t->aperf / t->mperf / interval_float);
841 if (DO_BIC(BIC_TSC_MHz))
842 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 * t->tsc/units/interval_float);
845 if (DO_BIC(BIC_IRQ)) {
846 if (sums_need_wide_columns)
847 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->irq_count);
849 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->irq_count);
854 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->smi_count);
857 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
858 if (mp->format == FORMAT_RAW) {
860 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) t->counter[i]);
862 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), t->counter[i]);
863 } else if (mp->format == FORMAT_DELTA) {
864 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
865 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->counter[i]);
867 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->counter[i]);
868 } else if (mp->format == FORMAT_PERCENT) {
869 if (mp->type == COUNTER_USEC)
870 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), t->counter[i]/interval_float/10000);
872 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->counter[i]/tsc);
877 if (DO_BIC(BIC_CPU_c1))
878 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->c1/tsc);
881 /* print per-core data only for 1st thread in core */
882 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
885 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates)
886 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c3/tsc);
887 if (DO_BIC(BIC_CPU_c6))
888 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c6/tsc);
889 if (DO_BIC(BIC_CPU_c7))
890 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c7/tsc);
893 if (DO_BIC(BIC_Mod_c6))
894 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->mc6_us / tsc);
896 if (DO_BIC(BIC_CoreTmp))
897 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_temp_c);
899 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
900 if (mp->format == FORMAT_RAW) {
902 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) c->counter[i]);
904 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), c->counter[i]);
905 } else if (mp->format == FORMAT_DELTA) {
906 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
907 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), c->counter[i]);
909 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->counter[i]);
910 } else if (mp->format == FORMAT_PERCENT) {
911 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->counter[i]/tsc);
915 /* print per-package data only for 1st core in package */
916 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
920 if (DO_BIC(BIC_PkgTmp))
921 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->pkg_temp_c);
924 if (DO_BIC(BIC_GFX_rc6)) {
925 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */
926 outp += sprintf(outp, "%s**.**", (printed++ ? delim : ""));
928 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""),
929 p->gfx_rc6_ms / 10.0 / interval_float);
934 if (DO_BIC(BIC_GFXMHz))
935 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_mhz);
937 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */
938 if (DO_BIC(BIC_Totl_c0))
939 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_wtd_core_c0/tsc);
940 if (DO_BIC(BIC_Any_c0))
941 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_core_c0/tsc);
942 if (DO_BIC(BIC_GFX_c0))
943 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_gfxe_c0/tsc);
944 if (DO_BIC(BIC_CPUGFX))
945 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_both_core_gfxe_c0/tsc);
947 if (DO_BIC(BIC_Pkgpc2))
948 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc2/tsc);
949 if (DO_BIC(BIC_Pkgpc3))
950 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc3/tsc);
951 if (DO_BIC(BIC_Pkgpc6))
952 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc6/tsc);
953 if (DO_BIC(BIC_Pkgpc7))
954 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc7/tsc);
955 if (DO_BIC(BIC_Pkgpc8))
956 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc8/tsc);
957 if (DO_BIC(BIC_Pkgpc9))
958 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc9/tsc);
959 if (DO_BIC(BIC_Pkgpc10))
960 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc10/tsc);
963 * If measurement interval exceeds minimum RAPL Joule Counter range,
964 * indicate that results are suspect by printing "**" in fraction place.
966 if (interval_float < rapl_joule_counter_range)
971 if (DO_BIC(BIC_PkgWatt))
972 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units / interval_float);
973 if (DO_BIC(BIC_CorWatt))
974 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units / interval_float);
975 if (DO_BIC(BIC_GFXWatt))
976 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units / interval_float);
977 if (DO_BIC(BIC_RAMWatt))
978 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units / interval_float);
979 if (DO_BIC(BIC_Pkg_J))
980 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units);
981 if (DO_BIC(BIC_Cor_J))
982 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units);
983 if (DO_BIC(BIC_GFX_J))
984 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units);
985 if (DO_BIC(BIC_RAM_J))
986 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units);
987 if (DO_BIC(BIC_PKG__))
988 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float);
989 if (DO_BIC(BIC_RAM__))
990 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float);
992 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
993 if (mp->format == FORMAT_RAW) {
995 outp += sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int) p->counter[i]);
997 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), p->counter[i]);
998 } else if (mp->format == FORMAT_DELTA) {
999 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
1000 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), p->counter[i]);
1002 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), p->counter[i]);
1003 } else if (mp->format == FORMAT_PERCENT) {
1004 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->counter[i]/tsc);
1009 outp += sprintf(outp, "\n");
1014 void flush_output_stdout(void)
1023 fputs(output_buffer, filep);
1026 outp = output_buffer;
1028 void flush_output_stderr(void)
1030 fputs(output_buffer, outf);
1032 outp = output_buffer;
1034 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1038 if (!printed || !summary_only)
1041 format_counters(&average.threads, &average.cores, &average.packages);
1048 for_all_cpus(format_counters, t, c, p);
1051 #define DELTA_WRAP32(new, old) \
1055 old = 0x100000000 + new - old; \
1059 delta_package(struct pkg_data *new, struct pkg_data *old)
1062 struct msr_counter *mp;
1065 if (DO_BIC(BIC_Totl_c0))
1066 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0;
1067 if (DO_BIC(BIC_Any_c0))
1068 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0;
1069 if (DO_BIC(BIC_GFX_c0))
1070 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0;
1071 if (DO_BIC(BIC_CPUGFX))
1072 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0;
1074 old->pc2 = new->pc2 - old->pc2;
1075 if (DO_BIC(BIC_Pkgpc3))
1076 old->pc3 = new->pc3 - old->pc3;
1077 if (DO_BIC(BIC_Pkgpc6))
1078 old->pc6 = new->pc6 - old->pc6;
1079 if (DO_BIC(BIC_Pkgpc7))
1080 old->pc7 = new->pc7 - old->pc7;
1081 old->pc8 = new->pc8 - old->pc8;
1082 old->pc9 = new->pc9 - old->pc9;
1083 old->pc10 = new->pc10 - old->pc10;
1084 old->pkg_temp_c = new->pkg_temp_c;
1086 /* flag an error when rc6 counter resets/wraps */
1087 if (old->gfx_rc6_ms > new->gfx_rc6_ms)
1088 old->gfx_rc6_ms = -1;
1090 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms;
1092 old->gfx_mhz = new->gfx_mhz;
1094 DELTA_WRAP32(new->energy_pkg, old->energy_pkg);
1095 DELTA_WRAP32(new->energy_cores, old->energy_cores);
1096 DELTA_WRAP32(new->energy_gfx, old->energy_gfx);
1097 DELTA_WRAP32(new->energy_dram, old->energy_dram);
1098 DELTA_WRAP32(new->rapl_pkg_perf_status, old->rapl_pkg_perf_status);
1099 DELTA_WRAP32(new->rapl_dram_perf_status, old->rapl_dram_perf_status);
1101 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1102 if (mp->format == FORMAT_RAW)
1103 old->counter[i] = new->counter[i];
1105 old->counter[i] = new->counter[i] - old->counter[i];
1112 delta_core(struct core_data *new, struct core_data *old)
1115 struct msr_counter *mp;
1117 old->c3 = new->c3 - old->c3;
1118 old->c6 = new->c6 - old->c6;
1119 old->c7 = new->c7 - old->c7;
1120 old->core_temp_c = new->core_temp_c;
1121 old->mc6_us = new->mc6_us - old->mc6_us;
1123 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1124 if (mp->format == FORMAT_RAW)
1125 old->counter[i] = new->counter[i];
1127 old->counter[i] = new->counter[i] - old->counter[i];
1135 delta_thread(struct thread_data *new, struct thread_data *old,
1136 struct core_data *core_delta)
1139 struct msr_counter *mp;
1141 old->tsc = new->tsc - old->tsc;
1143 /* check for TSC < 1 Mcycles over interval */
1144 if (old->tsc < (1000 * 1000))
1145 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n"
1146 "You can disable all c-states by booting with \"idle=poll\"\n"
1147 "or just the deep ones with \"processor.max_cstate=1\"");
1149 old->c1 = new->c1 - old->c1;
1151 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) {
1152 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) {
1153 old->aperf = new->aperf - old->aperf;
1154 old->mperf = new->mperf - old->mperf;
1161 if (use_c1_residency_msr) {
1163 * Some models have a dedicated C1 residency MSR,
1164 * which should be more accurate than the derivation below.
1168 * As counter collection is not atomic,
1169 * it is possible for mperf's non-halted cycles + idle states
1170 * to exceed TSC's all cycles: show c1 = 0% in that case.
1172 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > (old->tsc * tsc_tweak))
1175 /* normal case, derive c1 */
1176 old->c1 = (old->tsc * tsc_tweak) - old->mperf - core_delta->c3
1177 - core_delta->c6 - core_delta->c7;
1181 if (old->mperf == 0) {
1183 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id);
1184 old->mperf = 1; /* divide by 0 protection */
1187 if (DO_BIC(BIC_IRQ))
1188 old->irq_count = new->irq_count - old->irq_count;
1190 if (DO_BIC(BIC_SMI))
1191 old->smi_count = new->smi_count - old->smi_count;
1193 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1194 if (mp->format == FORMAT_RAW)
1195 old->counter[i] = new->counter[i];
1197 old->counter[i] = new->counter[i] - old->counter[i];
1202 int delta_cpu(struct thread_data *t, struct core_data *c,
1203 struct pkg_data *p, struct thread_data *t2,
1204 struct core_data *c2, struct pkg_data *p2)
1208 /* calculate core delta only for 1st thread in core */
1209 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE)
1212 /* always calculate thread delta */
1213 retval = delta_thread(t, t2, c2); /* c2 is core delta */
1217 /* calculate package delta only for 1st core in package */
1218 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)
1219 retval = delta_package(p, p2);
1224 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1227 struct msr_counter *mp;
1237 /* tells format_counters to dump all fields from this set */
1238 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE;
1246 p->pkg_wtd_core_c0 = 0;
1247 p->pkg_any_core_c0 = 0;
1248 p->pkg_any_gfxe_c0 = 0;
1249 p->pkg_both_core_gfxe_c0 = 0;
1252 if (DO_BIC(BIC_Pkgpc3))
1254 if (DO_BIC(BIC_Pkgpc6))
1256 if (DO_BIC(BIC_Pkgpc7))
1264 p->energy_cores = 0;
1266 p->rapl_pkg_perf_status = 0;
1267 p->rapl_dram_perf_status = 0;
1272 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next)
1275 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next)
1278 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next)
1281 int sum_counters(struct thread_data *t, struct core_data *c,
1285 struct msr_counter *mp;
1287 average.threads.tsc += t->tsc;
1288 average.threads.aperf += t->aperf;
1289 average.threads.mperf += t->mperf;
1290 average.threads.c1 += t->c1;
1292 average.threads.irq_count += t->irq_count;
1293 average.threads.smi_count += t->smi_count;
1295 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1296 if (mp->format == FORMAT_RAW)
1298 average.threads.counter[i] += t->counter[i];
1301 /* sum per-core values only for 1st thread in core */
1302 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1305 average.cores.c3 += c->c3;
1306 average.cores.c6 += c->c6;
1307 average.cores.c7 += c->c7;
1308 average.cores.mc6_us += c->mc6_us;
1310 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c);
1312 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1313 if (mp->format == FORMAT_RAW)
1315 average.cores.counter[i] += c->counter[i];
1318 /* sum per-pkg values only for 1st core in pkg */
1319 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1322 if (DO_BIC(BIC_Totl_c0))
1323 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0;
1324 if (DO_BIC(BIC_Any_c0))
1325 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0;
1326 if (DO_BIC(BIC_GFX_c0))
1327 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0;
1328 if (DO_BIC(BIC_CPUGFX))
1329 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0;
1331 average.packages.pc2 += p->pc2;
1332 if (DO_BIC(BIC_Pkgpc3))
1333 average.packages.pc3 += p->pc3;
1334 if (DO_BIC(BIC_Pkgpc6))
1335 average.packages.pc6 += p->pc6;
1336 if (DO_BIC(BIC_Pkgpc7))
1337 average.packages.pc7 += p->pc7;
1338 average.packages.pc8 += p->pc8;
1339 average.packages.pc9 += p->pc9;
1340 average.packages.pc10 += p->pc10;
1342 average.packages.energy_pkg += p->energy_pkg;
1343 average.packages.energy_dram += p->energy_dram;
1344 average.packages.energy_cores += p->energy_cores;
1345 average.packages.energy_gfx += p->energy_gfx;
1347 average.packages.gfx_rc6_ms = p->gfx_rc6_ms;
1348 average.packages.gfx_mhz = p->gfx_mhz;
1350 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c);
1352 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status;
1353 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status;
1355 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1356 if (mp->format == FORMAT_RAW)
1358 average.packages.counter[i] += p->counter[i];
1363 * sum the counters for all cpus in the system
1364 * compute the weighted average
1366 void compute_average(struct thread_data *t, struct core_data *c,
1370 struct msr_counter *mp;
1372 clear_counters(&average.threads, &average.cores, &average.packages);
1374 for_all_cpus(sum_counters, t, c, p);
1376 average.threads.tsc /= topo.num_cpus;
1377 average.threads.aperf /= topo.num_cpus;
1378 average.threads.mperf /= topo.num_cpus;
1379 average.threads.c1 /= topo.num_cpus;
1381 if (average.threads.irq_count > 9999999)
1382 sums_need_wide_columns = 1;
1384 average.cores.c3 /= topo.num_cores;
1385 average.cores.c6 /= topo.num_cores;
1386 average.cores.c7 /= topo.num_cores;
1387 average.cores.mc6_us /= topo.num_cores;
1389 if (DO_BIC(BIC_Totl_c0))
1390 average.packages.pkg_wtd_core_c0 /= topo.num_packages;
1391 if (DO_BIC(BIC_Any_c0))
1392 average.packages.pkg_any_core_c0 /= topo.num_packages;
1393 if (DO_BIC(BIC_GFX_c0))
1394 average.packages.pkg_any_gfxe_c0 /= topo.num_packages;
1395 if (DO_BIC(BIC_CPUGFX))
1396 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages;
1398 average.packages.pc2 /= topo.num_packages;
1399 if (DO_BIC(BIC_Pkgpc3))
1400 average.packages.pc3 /= topo.num_packages;
1401 if (DO_BIC(BIC_Pkgpc6))
1402 average.packages.pc6 /= topo.num_packages;
1403 if (DO_BIC(BIC_Pkgpc7))
1404 average.packages.pc7 /= topo.num_packages;
1406 average.packages.pc8 /= topo.num_packages;
1407 average.packages.pc9 /= topo.num_packages;
1408 average.packages.pc10 /= topo.num_packages;
1410 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1411 if (mp->format == FORMAT_RAW)
1413 if (mp->type == COUNTER_ITEMS) {
1414 if (average.threads.counter[i] > 9999999)
1415 sums_need_wide_columns = 1;
1418 average.threads.counter[i] /= topo.num_cpus;
1420 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1421 if (mp->format == FORMAT_RAW)
1423 if (mp->type == COUNTER_ITEMS) {
1424 if (average.cores.counter[i] > 9999999)
1425 sums_need_wide_columns = 1;
1427 average.cores.counter[i] /= topo.num_cores;
1429 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1430 if (mp->format == FORMAT_RAW)
1432 if (mp->type == COUNTER_ITEMS) {
1433 if (average.packages.counter[i] > 9999999)
1434 sums_need_wide_columns = 1;
1436 average.packages.counter[i] /= topo.num_packages;
1440 static unsigned long long rdtsc(void)
1442 unsigned int low, high;
1444 asm volatile("rdtsc" : "=a" (low), "=d" (high));
1446 return low | ((unsigned long long)high) << 32;
1450 * Open a file, and exit on failure
1452 FILE *fopen_or_die(const char *path, const char *mode)
1454 FILE *filep = fopen(path, mode);
1457 err(1, "%s: open failed", path);
1461 * snapshot_sysfs_counter()
1463 * return snapshot of given counter
1465 unsigned long long snapshot_sysfs_counter(char *path)
1469 unsigned long long counter;
1471 fp = fopen_or_die(path, "r");
1473 retval = fscanf(fp, "%lld", &counter);
1475 err(1, "snapshot_sysfs_counter(%s)", path);
1482 int get_mp(int cpu, struct msr_counter *mp, unsigned long long *counterp)
1484 if (mp->msr_num != 0) {
1485 if (get_msr(cpu, mp->msr_num, counterp))
1488 char path[128 + PATH_BYTES];
1490 if (mp->flags & SYSFS_PERCPU) {
1491 sprintf(path, "/sys/devices/system/cpu/cpu%d/%s",
1494 *counterp = snapshot_sysfs_counter(path);
1496 *counterp = snapshot_sysfs_counter(mp->path);
1506 * acquire and record local counters for that cpu
1508 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1510 int cpu = t->cpu_id;
1511 unsigned long long msr;
1512 int aperf_mperf_retry_count = 0;
1513 struct msr_counter *mp;
1517 gettimeofday(&t->tv_begin, (struct timezone *)NULL);
1519 if (cpu_migrate(cpu)) {
1520 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
1525 t->tsc = rdtsc(); /* we are running on local CPU of interest */
1527 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) {
1528 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time;
1531 * The TSC, APERF and MPERF must be read together for
1532 * APERF/MPERF and MPERF/TSC to give accurate results.
1534 * Unfortunately, APERF and MPERF are read by
1535 * individual system call, so delays may occur
1536 * between them. If the time to read them
1537 * varies by a large amount, we re-read them.
1541 * This initial dummy APERF read has been seen to
1542 * reduce jitter in the subsequent reads.
1545 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
1548 t->tsc = rdtsc(); /* re-read close to APERF */
1550 tsc_before = t->tsc;
1552 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
1555 tsc_between = rdtsc();
1557 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf))
1560 tsc_after = rdtsc();
1562 aperf_time = tsc_between - tsc_before;
1563 mperf_time = tsc_after - tsc_between;
1566 * If the system call latency to read APERF and MPERF
1567 * differ by more than 2x, then try again.
1569 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) {
1570 aperf_mperf_retry_count++;
1571 if (aperf_mperf_retry_count < 5)
1574 warnx("cpu%d jitter %lld %lld",
1575 cpu, aperf_time, mperf_time);
1577 aperf_mperf_retry_count = 0;
1579 t->aperf = t->aperf * aperf_mperf_multiplier;
1580 t->mperf = t->mperf * aperf_mperf_multiplier;
1583 if (DO_BIC(BIC_IRQ))
1584 t->irq_count = irqs_per_cpu[cpu];
1585 if (DO_BIC(BIC_SMI)) {
1586 if (get_msr(cpu, MSR_SMI_COUNT, &msr))
1588 t->smi_count = msr & 0xFFFFFFFF;
1590 if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) {
1591 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1))
1595 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1596 if (get_mp(cpu, mp, &t->counter[i]))
1600 /* collect core counters only for 1st thread in core */
1601 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1604 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates) {
1605 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3))
1609 if (DO_BIC(BIC_CPU_c6) && !do_knl_cstates) {
1610 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6))
1612 } else if (do_knl_cstates) {
1613 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6))
1617 if (DO_BIC(BIC_CPU_c7))
1618 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7))
1621 if (DO_BIC(BIC_Mod_c6))
1622 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us))
1625 if (DO_BIC(BIC_CoreTmp)) {
1626 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
1628 c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F);
1631 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1632 if (get_mp(cpu, mp, &c->counter[i]))
1636 /* collect package counters only for 1st core in package */
1637 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1640 if (DO_BIC(BIC_Totl_c0)) {
1641 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0))
1644 if (DO_BIC(BIC_Any_c0)) {
1645 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0))
1648 if (DO_BIC(BIC_GFX_c0)) {
1649 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0))
1652 if (DO_BIC(BIC_CPUGFX)) {
1653 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0))
1656 if (DO_BIC(BIC_Pkgpc3))
1657 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3))
1659 if (DO_BIC(BIC_Pkgpc6)) {
1660 if (do_slm_cstates) {
1661 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6))
1664 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6))
1669 if (DO_BIC(BIC_Pkgpc2))
1670 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2))
1672 if (DO_BIC(BIC_Pkgpc7))
1673 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7))
1675 if (DO_BIC(BIC_Pkgpc8))
1676 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8))
1678 if (DO_BIC(BIC_Pkgpc9))
1679 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9))
1681 if (DO_BIC(BIC_Pkgpc10))
1682 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10))
1685 if (do_rapl & RAPL_PKG) {
1686 if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr))
1688 p->energy_pkg = msr & 0xFFFFFFFF;
1690 if (do_rapl & RAPL_CORES_ENERGY_STATUS) {
1691 if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr))
1693 p->energy_cores = msr & 0xFFFFFFFF;
1695 if (do_rapl & RAPL_DRAM) {
1696 if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr))
1698 p->energy_dram = msr & 0xFFFFFFFF;
1700 if (do_rapl & RAPL_GFX) {
1701 if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr))
1703 p->energy_gfx = msr & 0xFFFFFFFF;
1705 if (do_rapl & RAPL_PKG_PERF_STATUS) {
1706 if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr))
1708 p->rapl_pkg_perf_status = msr & 0xFFFFFFFF;
1710 if (do_rapl & RAPL_DRAM_PERF_STATUS) {
1711 if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr))
1713 p->rapl_dram_perf_status = msr & 0xFFFFFFFF;
1715 if (DO_BIC(BIC_PkgTmp)) {
1716 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
1718 p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F);
1721 if (DO_BIC(BIC_GFX_rc6))
1722 p->gfx_rc6_ms = gfx_cur_rc6_ms;
1724 if (DO_BIC(BIC_GFXMHz))
1725 p->gfx_mhz = gfx_cur_mhz;
1727 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1728 if (get_mp(cpu, mp, &p->counter[i]))
1732 gettimeofday(&t->tv_end, (struct timezone *)NULL);
1738 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit:
1739 * If you change the values, note they are used both in comparisons
1740 * (>= PCL__7) and to index pkg_cstate_limit_strings[].
1743 #define PCLUKN 0 /* Unknown */
1744 #define PCLRSV 1 /* Reserved */
1745 #define PCL__0 2 /* PC0 */
1746 #define PCL__1 3 /* PC1 */
1747 #define PCL__2 4 /* PC2 */
1748 #define PCL__3 5 /* PC3 */
1749 #define PCL__4 6 /* PC4 */
1750 #define PCL__6 7 /* PC6 */
1751 #define PCL_6N 8 /* PC6 No Retention */
1752 #define PCL_6R 9 /* PC6 Retention */
1753 #define PCL__7 10 /* PC7 */
1754 #define PCL_7S 11 /* PC7 Shrink */
1755 #define PCL__8 12 /* PC8 */
1756 #define PCL__9 13 /* PC9 */
1757 #define PCLUNL 14 /* Unlimited */
1759 int pkg_cstate_limit = PCLUKN;
1760 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2",
1761 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "unlimited"};
1763 int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1764 int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1765 int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1766 int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7};
1767 int amt_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1768 int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1769 int bxt_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1770 int skx_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1774 calculate_tsc_tweak()
1776 tsc_tweak = base_hz / tsc_hz;
1780 dump_nhm_platform_info(void)
1782 unsigned long long msr;
1785 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
1787 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr);
1789 ratio = (msr >> 40) & 0xFF;
1790 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n",
1791 ratio, bclk, ratio * bclk);
1793 ratio = (msr >> 8) & 0xFF;
1794 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n",
1795 ratio, bclk, ratio * bclk);
1797 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr);
1798 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n",
1799 base_cpu, msr, msr & 0x2 ? "EN" : "DIS");
1805 dump_hsw_turbo_ratio_limits(void)
1807 unsigned long long msr;
1810 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr);
1812 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr);
1814 ratio = (msr >> 8) & 0xFF;
1816 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n",
1817 ratio, bclk, ratio * bclk);
1819 ratio = (msr >> 0) & 0xFF;
1821 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n",
1822 ratio, bclk, ratio * bclk);
1827 dump_ivt_turbo_ratio_limits(void)
1829 unsigned long long msr;
1832 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr);
1834 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr);
1836 ratio = (msr >> 56) & 0xFF;
1838 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n",
1839 ratio, bclk, ratio * bclk);
1841 ratio = (msr >> 48) & 0xFF;
1843 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n",
1844 ratio, bclk, ratio * bclk);
1846 ratio = (msr >> 40) & 0xFF;
1848 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n",
1849 ratio, bclk, ratio * bclk);
1851 ratio = (msr >> 32) & 0xFF;
1853 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n",
1854 ratio, bclk, ratio * bclk);
1856 ratio = (msr >> 24) & 0xFF;
1858 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n",
1859 ratio, bclk, ratio * bclk);
1861 ratio = (msr >> 16) & 0xFF;
1863 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n",
1864 ratio, bclk, ratio * bclk);
1866 ratio = (msr >> 8) & 0xFF;
1868 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n",
1869 ratio, bclk, ratio * bclk);
1871 ratio = (msr >> 0) & 0xFF;
1873 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n",
1874 ratio, bclk, ratio * bclk);
1877 int has_turbo_ratio_group_limits(int family, int model)
1884 case INTEL_FAM6_ATOM_GOLDMONT:
1885 case INTEL_FAM6_SKYLAKE_X:
1886 case INTEL_FAM6_ATOM_GOLDMONT_X:
1893 dump_turbo_ratio_limits(int family, int model)
1895 unsigned long long msr, core_counts;
1896 unsigned int ratio, group_size;
1898 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
1899 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr);
1901 if (has_turbo_ratio_group_limits(family, model)) {
1902 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts);
1903 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, core_counts);
1905 core_counts = 0x0807060504030201;
1908 ratio = (msr >> 56) & 0xFF;
1909 group_size = (core_counts >> 56) & 0xFF;
1911 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
1912 ratio, bclk, ratio * bclk, group_size);
1914 ratio = (msr >> 48) & 0xFF;
1915 group_size = (core_counts >> 48) & 0xFF;
1917 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
1918 ratio, bclk, ratio * bclk, group_size);
1920 ratio = (msr >> 40) & 0xFF;
1921 group_size = (core_counts >> 40) & 0xFF;
1923 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
1924 ratio, bclk, ratio * bclk, group_size);
1926 ratio = (msr >> 32) & 0xFF;
1927 group_size = (core_counts >> 32) & 0xFF;
1929 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
1930 ratio, bclk, ratio * bclk, group_size);
1932 ratio = (msr >> 24) & 0xFF;
1933 group_size = (core_counts >> 24) & 0xFF;
1935 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
1936 ratio, bclk, ratio * bclk, group_size);
1938 ratio = (msr >> 16) & 0xFF;
1939 group_size = (core_counts >> 16) & 0xFF;
1941 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
1942 ratio, bclk, ratio * bclk, group_size);
1944 ratio = (msr >> 8) & 0xFF;
1945 group_size = (core_counts >> 8) & 0xFF;
1947 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
1948 ratio, bclk, ratio * bclk, group_size);
1950 ratio = (msr >> 0) & 0xFF;
1951 group_size = (core_counts >> 0) & 0xFF;
1953 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
1954 ratio, bclk, ratio * bclk, group_size);
1959 dump_atom_turbo_ratio_limits(void)
1961 unsigned long long msr;
1964 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr);
1965 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
1967 ratio = (msr >> 0) & 0x3F;
1969 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n",
1970 ratio, bclk, ratio * bclk);
1972 ratio = (msr >> 8) & 0x3F;
1974 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n",
1975 ratio, bclk, ratio * bclk);
1977 ratio = (msr >> 16) & 0x3F;
1979 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n",
1980 ratio, bclk, ratio * bclk);
1982 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr);
1983 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
1985 ratio = (msr >> 24) & 0x3F;
1987 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n",
1988 ratio, bclk, ratio * bclk);
1990 ratio = (msr >> 16) & 0x3F;
1992 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n",
1993 ratio, bclk, ratio * bclk);
1995 ratio = (msr >> 8) & 0x3F;
1997 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n",
1998 ratio, bclk, ratio * bclk);
2000 ratio = (msr >> 0) & 0x3F;
2002 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n",
2003 ratio, bclk, ratio * bclk);
2007 dump_knl_turbo_ratio_limits(void)
2009 const unsigned int buckets_no = 7;
2011 unsigned long long msr;
2012 int delta_cores, delta_ratio;
2014 unsigned int cores[buckets_no];
2015 unsigned int ratio[buckets_no];
2017 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
2019 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n",
2023 * Turbo encoding in KNL is as follows:
2025 * [7:1] -- Base value of number of active cores of bucket 1.
2026 * [15:8] -- Base value of freq ratio of bucket 1.
2027 * [20:16] -- +ve delta of number of active cores of bucket 2.
2028 * i.e. active cores of bucket 2 =
2029 * active cores of bucket 1 + delta
2030 * [23:21] -- Negative delta of freq ratio of bucket 2.
2031 * i.e. freq ratio of bucket 2 =
2032 * freq ratio of bucket 1 - delta
2033 * [28:24]-- +ve delta of number of active cores of bucket 3.
2034 * [31:29]-- -ve delta of freq ratio of bucket 3.
2035 * [36:32]-- +ve delta of number of active cores of bucket 4.
2036 * [39:37]-- -ve delta of freq ratio of bucket 4.
2037 * [44:40]-- +ve delta of number of active cores of bucket 5.
2038 * [47:45]-- -ve delta of freq ratio of bucket 5.
2039 * [52:48]-- +ve delta of number of active cores of bucket 6.
2040 * [55:53]-- -ve delta of freq ratio of bucket 6.
2041 * [60:56]-- +ve delta of number of active cores of bucket 7.
2042 * [63:61]-- -ve delta of freq ratio of bucket 7.
2046 cores[b_nr] = (msr & 0xFF) >> 1;
2047 ratio[b_nr] = (msr >> 8) & 0xFF;
2049 for (i = 16; i < 64; i += 8) {
2050 delta_cores = (msr >> i) & 0x1F;
2051 delta_ratio = (msr >> (i + 5)) & 0x7;
2053 cores[b_nr + 1] = cores[b_nr] + delta_cores;
2054 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio;
2058 for (i = buckets_no - 1; i >= 0; i--)
2059 if (i > 0 ? ratio[i] != ratio[i - 1] : 1)
2061 "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2062 ratio[i], bclk, ratio[i] * bclk, cores[i]);
2066 dump_nhm_cst_cfg(void)
2068 unsigned long long msr;
2070 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
2072 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
2073 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
2075 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr);
2077 fprintf(outf, " (%s%s%s%s%slocked: pkg-cstate-limit=%d: %s)\n",
2078 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "",
2079 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "",
2080 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "",
2081 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "",
2082 (msr & (1 << 15)) ? "" : "UN",
2083 (unsigned int)msr & 0xF,
2084 pkg_cstate_limit_strings[pkg_cstate_limit]);
2089 dump_config_tdp(void)
2091 unsigned long long msr;
2093 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr);
2094 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr);
2095 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF);
2097 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr);
2098 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr);
2100 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
2101 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
2102 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
2103 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF);
2105 fprintf(outf, ")\n");
2107 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr);
2108 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr);
2110 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
2111 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
2112 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
2113 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF);
2115 fprintf(outf, ")\n");
2117 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr);
2118 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr);
2120 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3);
2121 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
2122 fprintf(outf, ")\n");
2124 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr);
2125 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr);
2126 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF);
2127 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
2128 fprintf(outf, ")\n");
2131 unsigned int irtl_time_units[] = {1, 32, 1024, 32768, 1048576, 33554432, 0, 0 };
2133 void print_irtl(void)
2135 unsigned long long msr;
2137 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr);
2138 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr);
2139 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2140 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2142 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr);
2143 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr);
2144 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2145 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2147 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr);
2148 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr);
2149 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2150 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2155 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr);
2156 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr);
2157 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2158 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2160 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr);
2161 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr);
2162 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2163 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2165 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr);
2166 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr);
2167 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2168 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2171 void free_fd_percpu(void)
2175 for (i = 0; i < topo.max_cpu_num + 1; ++i) {
2176 if (fd_percpu[i] != 0)
2177 close(fd_percpu[i]);
2183 void free_all_buffers(void)
2185 CPU_FREE(cpu_present_set);
2186 cpu_present_set = NULL;
2187 cpu_present_setsize = 0;
2189 CPU_FREE(cpu_affinity_set);
2190 cpu_affinity_set = NULL;
2191 cpu_affinity_setsize = 0;
2199 package_even = NULL;
2209 free(output_buffer);
2210 output_buffer = NULL;
2215 free(irq_column_2_cpu);
2221 * Parse a file containing a single int.
2223 int parse_int_file(const char *fmt, ...)
2226 char path[PATH_MAX];
2230 va_start(args, fmt);
2231 vsnprintf(path, sizeof(path), fmt, args);
2233 filep = fopen_or_die(path, "r");
2234 if (fscanf(filep, "%d", &value) != 1)
2235 err(1, "%s: failed to parse number from file", path);
2241 * get_cpu_position_in_core(cpu)
2242 * return the position of the CPU among its HT siblings in the core
2243 * return -1 if the sibling is not in list
2245 int get_cpu_position_in_core(int cpu)
2254 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list",
2256 filep = fopen(path, "r");
2257 if (filep == NULL) {
2262 for (i = 0; i < topo.num_threads_per_core; i++) {
2263 fscanf(filep, "%d", &this_cpu);
2264 if (this_cpu == cpu) {
2269 /* Account for no separator after last thread*/
2270 if (i != (topo.num_threads_per_core - 1))
2271 fscanf(filep, "%c", &character);
2279 * cpu_is_first_core_in_package(cpu)
2280 * return 1 if given CPU is 1st core in package
2282 int cpu_is_first_core_in_package(int cpu)
2284 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu);
2287 int get_physical_package_id(int cpu)
2289 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu);
2292 int get_core_id(int cpu)
2294 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu);
2297 int get_num_ht_siblings(int cpu)
2307 sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", cpu);
2308 filep = fopen_or_die(path, "r");
2312 * A ',' separated or '-' separated set of numbers
2313 * (eg 1-2 or 1,3,4,5)
2315 fscanf(filep, "%d%c\n", &sib1, &character);
2316 fseek(filep, 0, SEEK_SET);
2317 fgets(str, 100, filep);
2318 ch = strchr(str, character);
2319 while (ch != NULL) {
2321 ch = strchr(ch+1, character);
2329 * run func(thread, core, package) in topology order
2330 * skip non-present cpus
2333 int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *,
2334 struct pkg_data *, struct thread_data *, struct core_data *,
2335 struct pkg_data *), struct thread_data *thread_base,
2336 struct core_data *core_base, struct pkg_data *pkg_base,
2337 struct thread_data *thread_base2, struct core_data *core_base2,
2338 struct pkg_data *pkg_base2)
2340 int retval, pkg_no, core_no, thread_no;
2342 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
2343 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) {
2344 for (thread_no = 0; thread_no <
2345 topo.num_threads_per_core; ++thread_no) {
2346 struct thread_data *t, *t2;
2347 struct core_data *c, *c2;
2348 struct pkg_data *p, *p2;
2350 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no);
2352 if (cpu_is_not_present(t->cpu_id))
2355 t2 = GET_THREAD(thread_base2, thread_no, core_no, pkg_no);
2357 c = GET_CORE(core_base, core_no, pkg_no);
2358 c2 = GET_CORE(core_base2, core_no, pkg_no);
2360 p = GET_PKG(pkg_base, pkg_no);
2361 p2 = GET_PKG(pkg_base2, pkg_no);
2363 retval = func(t, c, p, t2, c2, p2);
2373 * run func(cpu) on every cpu in /proc/stat
2374 * return max_cpu number
2376 int for_all_proc_cpus(int (func)(int))
2382 fp = fopen_or_die(proc_stat, "r");
2384 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n");
2386 err(1, "%s: failed to parse format", proc_stat);
2389 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num);
2393 retval = func(cpu_num);
2403 void re_initialize(void)
2406 setup_all_buffers();
2407 printf("turbostat: re-initialized with num_cpus %d\n", topo.num_cpus);
2413 * remember the last one seen, it will be the max
2415 int count_cpus(int cpu)
2417 if (topo.max_cpu_num < cpu)
2418 topo.max_cpu_num = cpu;
2423 int mark_cpu_present(int cpu)
2425 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set);
2430 * snapshot_proc_interrupts()
2432 * read and record summary of /proc/interrupts
2434 * return 1 if config change requires a restart, else return 0
2436 int snapshot_proc_interrupts(void)
2442 fp = fopen_or_die("/proc/interrupts", "r");
2446 /* read 1st line of /proc/interrupts to get cpu* name for each column */
2447 for (column = 0; column < topo.num_cpus; ++column) {
2450 retval = fscanf(fp, " CPU%d", &cpu_number);
2454 if (cpu_number > topo.max_cpu_num) {
2455 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num);
2459 irq_column_2_cpu[column] = cpu_number;
2460 irqs_per_cpu[cpu_number] = 0;
2463 /* read /proc/interrupt count lines and sum up irqs per cpu */
2468 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */
2472 /* read the count per cpu */
2473 for (column = 0; column < topo.num_cpus; ++column) {
2475 int cpu_number, irq_count;
2477 retval = fscanf(fp, " %d", &irq_count);
2481 cpu_number = irq_column_2_cpu[column];
2482 irqs_per_cpu[cpu_number] += irq_count;
2486 while (getc(fp) != '\n')
2487 ; /* flush interrupt description */
2493 * snapshot_gfx_rc6_ms()
2495 * record snapshot of
2496 * /sys/class/drm/card0/power/rc6_residency_ms
2498 * return 1 if config change requires a restart, else return 0
2500 int snapshot_gfx_rc6_ms(void)
2505 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r");
2507 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms);
2516 * snapshot_gfx_mhz()
2518 * record snapshot of
2519 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz
2521 * return 1 if config change requires a restart, else return 0
2523 int snapshot_gfx_mhz(void)
2529 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r");
2535 retval = fscanf(fp, "%d", &gfx_cur_mhz);
2543 * snapshot /proc and /sys files
2545 * return 1 if configuration restart needed, else return 0
2547 int snapshot_proc_sysfs_files(void)
2549 if (DO_BIC(BIC_IRQ))
2550 if (snapshot_proc_interrupts())
2553 if (DO_BIC(BIC_GFX_rc6))
2554 snapshot_gfx_rc6_ms();
2556 if (DO_BIC(BIC_GFXMHz))
2562 void turbostat_loop()
2570 snapshot_proc_sysfs_files();
2571 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
2574 } else if (retval == -1) {
2575 if (restarted > 1) {
2582 gettimeofday(&tv_even, (struct timezone *)NULL);
2585 if (for_all_proc_cpus(cpu_is_not_present)) {
2589 nanosleep(&interval_ts, NULL);
2590 if (snapshot_proc_sysfs_files())
2592 retval = for_all_cpus(get_counters, ODD_COUNTERS);
2595 } else if (retval == -1) {
2599 gettimeofday(&tv_odd, (struct timezone *)NULL);
2600 timersub(&tv_odd, &tv_even, &tv_delta);
2601 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) {
2605 compute_average(EVEN_COUNTERS);
2606 format_all_counters(EVEN_COUNTERS);
2607 flush_output_stdout();
2608 nanosleep(&interval_ts, NULL);
2609 if (snapshot_proc_sysfs_files())
2611 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
2614 } else if (retval == -1) {
2618 gettimeofday(&tv_even, (struct timezone *)NULL);
2619 timersub(&tv_even, &tv_odd, &tv_delta);
2620 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) {
2624 compute_average(ODD_COUNTERS);
2625 format_all_counters(ODD_COUNTERS);
2626 flush_output_stdout();
2630 void check_dev_msr()
2635 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
2636 if (stat(pathname, &sb))
2637 if (system("/sbin/modprobe msr > /dev/null 2>&1"))
2638 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" ");
2641 void check_permissions()
2643 struct __user_cap_header_struct cap_header_data;
2644 cap_user_header_t cap_header = &cap_header_data;
2645 struct __user_cap_data_struct cap_data_data;
2646 cap_user_data_t cap_data = &cap_data_data;
2647 extern int capget(cap_user_header_t hdrp, cap_user_data_t datap);
2651 /* check for CAP_SYS_RAWIO */
2652 cap_header->pid = getpid();
2653 cap_header->version = _LINUX_CAPABILITY_VERSION;
2654 if (capget(cap_header, cap_data) < 0)
2655 err(-6, "capget(2) failed");
2657 if ((cap_data->effective & (1 << CAP_SYS_RAWIO)) == 0) {
2659 warnx("capget(CAP_SYS_RAWIO) failed,"
2660 " try \"# setcap cap_sys_rawio=ep %s\"", progname);
2663 /* test file permissions */
2664 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
2665 if (euidaccess(pathname, R_OK)) {
2667 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr");
2670 /* if all else fails, thell them to be root */
2673 warnx("... or simply run as root");
2680 * NHM adds support for additional MSRs:
2682 * MSR_SMI_COUNT 0x00000034
2684 * MSR_PLATFORM_INFO 0x000000ce
2685 * MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
2687 * MSR_MISC_PWR_MGMT 0x000001aa
2689 * MSR_PKG_C3_RESIDENCY 0x000003f8
2690 * MSR_PKG_C6_RESIDENCY 0x000003f9
2691 * MSR_CORE_C3_RESIDENCY 0x000003fc
2692 * MSR_CORE_C6_RESIDENCY 0x000003fd
2695 * sets global pkg_cstate_limit to decode MSR_PKG_CST_CONFIG_CONTROL
2696 * sets has_misc_feature_control
2698 int probe_nhm_msrs(unsigned int family, unsigned int model)
2700 unsigned long long msr;
2701 unsigned int base_ratio;
2702 int *pkg_cstate_limits;
2710 bclk = discover_bclk(family, model);
2713 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */
2714 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
2715 case 0x1F: /* Core i7 and i5 Processor - Nehalem */
2716 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */
2717 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */
2718 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
2719 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */
2720 pkg_cstate_limits = nhm_pkg_cstate_limits;
2722 case INTEL_FAM6_SANDYBRIDGE: /* SNB */
2723 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */
2724 case INTEL_FAM6_IVYBRIDGE: /* IVB */
2725 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
2726 pkg_cstate_limits = snb_pkg_cstate_limits;
2727 has_misc_feature_control = 1;
2729 case INTEL_FAM6_HASWELL_CORE: /* HSW */
2730 case INTEL_FAM6_HASWELL_X: /* HSX */
2731 case INTEL_FAM6_HASWELL_ULT: /* HSW */
2732 case INTEL_FAM6_HASWELL_GT3E: /* HSW */
2733 case INTEL_FAM6_BROADWELL_CORE: /* BDW */
2734 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
2735 case INTEL_FAM6_BROADWELL_X: /* BDX */
2736 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
2737 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
2738 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
2739 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
2740 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
2741 pkg_cstate_limits = hsw_pkg_cstate_limits;
2742 has_misc_feature_control = 1;
2744 case INTEL_FAM6_SKYLAKE_X: /* SKX */
2745 pkg_cstate_limits = skx_pkg_cstate_limits;
2746 has_misc_feature_control = 1;
2748 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
2749 no_MSR_MISC_PWR_MGMT = 1;
2750 case INTEL_FAM6_ATOM_SILVERMONT_X: /* AVN */
2751 pkg_cstate_limits = slv_pkg_cstate_limits;
2753 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */
2754 pkg_cstate_limits = amt_pkg_cstate_limits;
2755 no_MSR_MISC_PWR_MGMT = 1;
2757 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */
2758 case INTEL_FAM6_XEON_PHI_KNM:
2759 pkg_cstate_limits = phi_pkg_cstate_limits;
2761 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
2762 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
2763 case INTEL_FAM6_ATOM_GOLDMONT_X: /* DNV */
2764 pkg_cstate_limits = bxt_pkg_cstate_limits;
2769 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
2770 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF];
2772 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
2773 base_ratio = (msr >> 8) & 0xFF;
2775 base_hz = base_ratio * bclk * 1000000;
2780 * SLV client has support for unique MSRs:
2782 * MSR_CC6_DEMOTION_POLICY_CONFIG
2783 * MSR_MC6_DEMOTION_POLICY_CONFIG
2786 int has_slv_msrs(unsigned int family, unsigned int model)
2792 case INTEL_FAM6_ATOM_SILVERMONT:
2793 case INTEL_FAM6_ATOM_SILVERMONT_MID:
2794 case INTEL_FAM6_ATOM_AIRMONT_MID:
2799 int is_dnv(unsigned int family, unsigned int model)
2806 case INTEL_FAM6_ATOM_GOLDMONT_X:
2811 int is_bdx(unsigned int family, unsigned int model)
2818 case INTEL_FAM6_BROADWELL_X:
2819 case INTEL_FAM6_BROADWELL_XEON_D:
2824 int is_skx(unsigned int family, unsigned int model)
2831 case INTEL_FAM6_SKYLAKE_X:
2837 int has_turbo_ratio_limit(unsigned int family, unsigned int model)
2839 if (has_slv_msrs(family, model))
2843 /* Nehalem compatible, but do not include turbo-ratio limit support */
2844 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
2845 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */
2846 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */
2847 case INTEL_FAM6_XEON_PHI_KNM:
2853 int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model)
2855 if (has_slv_msrs(family, model))
2860 int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model)
2869 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
2870 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */
2876 int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model)
2885 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */
2892 int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model)
2901 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
2902 case INTEL_FAM6_XEON_PHI_KNM:
2908 int has_glm_turbo_ratio_limit(unsigned int family, unsigned int model)
2917 case INTEL_FAM6_ATOM_GOLDMONT:
2918 case INTEL_FAM6_SKYLAKE_X:
2924 int has_config_tdp(unsigned int family, unsigned int model)
2933 case INTEL_FAM6_IVYBRIDGE: /* IVB */
2934 case INTEL_FAM6_HASWELL_CORE: /* HSW */
2935 case INTEL_FAM6_HASWELL_X: /* HSX */
2936 case INTEL_FAM6_HASWELL_ULT: /* HSW */
2937 case INTEL_FAM6_HASWELL_GT3E: /* HSW */
2938 case INTEL_FAM6_BROADWELL_CORE: /* BDW */
2939 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
2940 case INTEL_FAM6_BROADWELL_X: /* BDX */
2941 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
2942 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
2943 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
2944 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
2945 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
2946 case INTEL_FAM6_SKYLAKE_X: /* SKX */
2948 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
2949 case INTEL_FAM6_XEON_PHI_KNM:
2957 dump_cstate_pstate_config_info(unsigned int family, unsigned int model)
2959 if (!do_nhm_platform_info)
2962 dump_nhm_platform_info();
2964 if (has_hsw_turbo_ratio_limit(family, model))
2965 dump_hsw_turbo_ratio_limits();
2967 if (has_ivt_turbo_ratio_limit(family, model))
2968 dump_ivt_turbo_ratio_limits();
2970 if (has_turbo_ratio_limit(family, model))
2971 dump_turbo_ratio_limits(family, model);
2973 if (has_atom_turbo_ratio_limit(family, model))
2974 dump_atom_turbo_ratio_limits();
2976 if (has_knl_turbo_ratio_limit(family, model))
2977 dump_knl_turbo_ratio_limits();
2979 if (has_config_tdp(family, model))
2986 dump_sysfs_cstate_config(void)
2995 if (!DO_BIC(BIC_sysfs))
2998 for (state = 0; state < 10; ++state) {
3000 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name",
3002 input = fopen(path, "r");
3005 fgets(name_buf, sizeof(name_buf), input);
3007 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
3008 sp = strchr(name_buf, '-');
3010 sp = strchrnul(name_buf, '\n');
3015 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/desc",
3017 input = fopen(path, "r");
3020 fgets(desc, sizeof(desc), input);
3022 fprintf(outf, "cpu%d: %s: %s", base_cpu, name_buf, desc);
3027 dump_sysfs_pstate_config(void)
3030 char driver_buf[64];
3031 char governor_buf[64];
3035 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_driver",
3037 input = fopen(path, "r");
3038 if (input == NULL) {
3039 fprintf(stderr, "NSFOD %s\n", path);
3042 fgets(driver_buf, sizeof(driver_buf), input);
3045 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_governor",
3047 input = fopen(path, "r");
3048 if (input == NULL) {
3049 fprintf(stderr, "NSFOD %s\n", path);
3052 fgets(governor_buf, sizeof(governor_buf), input);
3055 fprintf(outf, "cpu%d: cpufreq driver: %s", base_cpu, driver_buf);
3056 fprintf(outf, "cpu%d: cpufreq governor: %s", base_cpu, governor_buf);
3058 sprintf(path, "/sys/devices/system/cpu/cpufreq/boost");
3059 input = fopen(path, "r");
3060 if (input != NULL) {
3061 fscanf(input, "%d", &turbo);
3062 fprintf(outf, "cpufreq boost: %d\n", turbo);
3066 sprintf(path, "/sys/devices/system/cpu/intel_pstate/no_turbo");
3067 input = fopen(path, "r");
3068 if (input != NULL) {
3069 fscanf(input, "%d", &turbo);
3070 fprintf(outf, "cpufreq intel_pstate no_turbo: %d\n", turbo);
3078 * Decode the ENERGY_PERF_BIAS MSR
3080 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3082 unsigned long long msr;
3091 /* EPB is per-package */
3092 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
3095 if (cpu_migrate(cpu)) {
3096 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
3100 if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr))
3103 switch (msr & 0xF) {
3104 case ENERGY_PERF_BIAS_PERFORMANCE:
3105 epb_string = "performance";
3107 case ENERGY_PERF_BIAS_NORMAL:
3108 epb_string = "balanced";
3110 case ENERGY_PERF_BIAS_POWERSAVE:
3111 epb_string = "powersave";
3114 epb_string = "custom";
3117 fprintf(outf, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu, msr, epb_string);
3123 * Decode the MSR_HWP_CAPABILITIES
3125 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3127 unsigned long long msr;
3135 /* MSR_HWP_CAPABILITIES is per-package */
3136 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
3139 if (cpu_migrate(cpu)) {
3140 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
3144 if (get_msr(cpu, MSR_PM_ENABLE, &msr))
3147 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n",
3148 cpu, msr, (msr & (1 << 0)) ? "" : "No-");
3150 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */
3151 if ((msr & (1 << 0)) == 0)
3154 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr))
3157 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx "
3158 "(high %d guar %d eff %d low %d)\n",
3160 (unsigned int)HWP_HIGHEST_PERF(msr),
3161 (unsigned int)HWP_GUARANTEED_PERF(msr),
3162 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr),
3163 (unsigned int)HWP_LOWEST_PERF(msr));
3165 if (get_msr(cpu, MSR_HWP_REQUEST, &msr))
3168 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx "
3169 "(min %d max %d des %d epp 0x%x window 0x%x pkg 0x%x)\n",
3171 (unsigned int)(((msr) >> 0) & 0xff),
3172 (unsigned int)(((msr) >> 8) & 0xff),
3173 (unsigned int)(((msr) >> 16) & 0xff),
3174 (unsigned int)(((msr) >> 24) & 0xff),
3175 (unsigned int)(((msr) >> 32) & 0xff3),
3176 (unsigned int)(((msr) >> 42) & 0x1));
3179 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr))
3182 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx "
3183 "(min %d max %d des %d epp 0x%x window 0x%x)\n",
3185 (unsigned int)(((msr) >> 0) & 0xff),
3186 (unsigned int)(((msr) >> 8) & 0xff),
3187 (unsigned int)(((msr) >> 16) & 0xff),
3188 (unsigned int)(((msr) >> 24) & 0xff),
3189 (unsigned int)(((msr) >> 32) & 0xff3));
3191 if (has_hwp_notify) {
3192 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr))
3195 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx "
3196 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n",
3198 ((msr) & 0x1) ? "EN" : "Dis",
3199 ((msr) & 0x2) ? "EN" : "Dis");
3201 if (get_msr(cpu, MSR_HWP_STATUS, &msr))
3204 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx "
3205 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n",
3207 ((msr) & 0x1) ? "" : "No-",
3208 ((msr) & 0x2) ? "" : "No-");
3214 * print_perf_limit()
3216 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3218 unsigned long long msr;
3224 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
3227 if (cpu_migrate(cpu)) {
3228 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
3232 if (do_core_perf_limit_reasons) {
3233 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr);
3234 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
3235 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)",
3236 (msr & 1 << 15) ? "bit15, " : "",
3237 (msr & 1 << 14) ? "bit14, " : "",
3238 (msr & 1 << 13) ? "Transitions, " : "",
3239 (msr & 1 << 12) ? "MultiCoreTurbo, " : "",
3240 (msr & 1 << 11) ? "PkgPwrL2, " : "",
3241 (msr & 1 << 10) ? "PkgPwrL1, " : "",
3242 (msr & 1 << 9) ? "CorePwr, " : "",
3243 (msr & 1 << 8) ? "Amps, " : "",
3244 (msr & 1 << 6) ? "VR-Therm, " : "",
3245 (msr & 1 << 5) ? "Auto-HWP, " : "",
3246 (msr & 1 << 4) ? "Graphics, " : "",
3247 (msr & 1 << 2) ? "bit2, " : "",
3248 (msr & 1 << 1) ? "ThermStatus, " : "",
3249 (msr & 1 << 0) ? "PROCHOT, " : "");
3250 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
3251 (msr & 1 << 31) ? "bit31, " : "",
3252 (msr & 1 << 30) ? "bit30, " : "",
3253 (msr & 1 << 29) ? "Transitions, " : "",
3254 (msr & 1 << 28) ? "MultiCoreTurbo, " : "",
3255 (msr & 1 << 27) ? "PkgPwrL2, " : "",
3256 (msr & 1 << 26) ? "PkgPwrL1, " : "",
3257 (msr & 1 << 25) ? "CorePwr, " : "",
3258 (msr & 1 << 24) ? "Amps, " : "",
3259 (msr & 1 << 22) ? "VR-Therm, " : "",
3260 (msr & 1 << 21) ? "Auto-HWP, " : "",
3261 (msr & 1 << 20) ? "Graphics, " : "",
3262 (msr & 1 << 18) ? "bit18, " : "",
3263 (msr & 1 << 17) ? "ThermStatus, " : "",
3264 (msr & 1 << 16) ? "PROCHOT, " : "");
3267 if (do_gfx_perf_limit_reasons) {
3268 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr);
3269 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
3270 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)",
3271 (msr & 1 << 0) ? "PROCHOT, " : "",
3272 (msr & 1 << 1) ? "ThermStatus, " : "",
3273 (msr & 1 << 4) ? "Graphics, " : "",
3274 (msr & 1 << 6) ? "VR-Therm, " : "",
3275 (msr & 1 << 8) ? "Amps, " : "",
3276 (msr & 1 << 9) ? "GFXPwr, " : "",
3277 (msr & 1 << 10) ? "PkgPwrL1, " : "",
3278 (msr & 1 << 11) ? "PkgPwrL2, " : "");
3279 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n",
3280 (msr & 1 << 16) ? "PROCHOT, " : "",
3281 (msr & 1 << 17) ? "ThermStatus, " : "",
3282 (msr & 1 << 20) ? "Graphics, " : "",
3283 (msr & 1 << 22) ? "VR-Therm, " : "",
3284 (msr & 1 << 24) ? "Amps, " : "",
3285 (msr & 1 << 25) ? "GFXPwr, " : "",
3286 (msr & 1 << 26) ? "PkgPwrL1, " : "",
3287 (msr & 1 << 27) ? "PkgPwrL2, " : "");
3289 if (do_ring_perf_limit_reasons) {
3290 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr);
3291 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
3292 fprintf(outf, " (Active: %s%s%s%s%s%s)",
3293 (msr & 1 << 0) ? "PROCHOT, " : "",
3294 (msr & 1 << 1) ? "ThermStatus, " : "",
3295 (msr & 1 << 6) ? "VR-Therm, " : "",
3296 (msr & 1 << 8) ? "Amps, " : "",
3297 (msr & 1 << 10) ? "PkgPwrL1, " : "",
3298 (msr & 1 << 11) ? "PkgPwrL2, " : "");
3299 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n",
3300 (msr & 1 << 16) ? "PROCHOT, " : "",
3301 (msr & 1 << 17) ? "ThermStatus, " : "",
3302 (msr & 1 << 22) ? "VR-Therm, " : "",
3303 (msr & 1 << 24) ? "Amps, " : "",
3304 (msr & 1 << 26) ? "PkgPwrL1, " : "",
3305 (msr & 1 << 27) ? "PkgPwrL2, " : "");
3310 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */
3311 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */
3313 double get_tdp(unsigned int model)
3315 unsigned long long msr;
3317 if (do_rapl & RAPL_PKG_POWER_INFO)
3318 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr))
3319 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units;
3322 case INTEL_FAM6_ATOM_SILVERMONT:
3323 case INTEL_FAM6_ATOM_SILVERMONT_X:
3331 * rapl_dram_energy_units_probe()
3332 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR.
3335 rapl_dram_energy_units_probe(int model, double rapl_energy_units)
3337 /* only called for genuine_intel, family 6 */
3340 case INTEL_FAM6_HASWELL_X: /* HSX */
3341 case INTEL_FAM6_BROADWELL_X: /* BDX */
3342 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
3343 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
3344 case INTEL_FAM6_XEON_PHI_KNM:
3345 return (rapl_dram_energy_units = 15.3 / 1000000);
3347 return (rapl_energy_units);
3355 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units
3357 void rapl_probe(unsigned int family, unsigned int model)
3359 unsigned long long msr;
3360 unsigned int time_unit;
3370 case INTEL_FAM6_SANDYBRIDGE:
3371 case INTEL_FAM6_IVYBRIDGE:
3372 case INTEL_FAM6_HASWELL_CORE: /* HSW */
3373 case INTEL_FAM6_HASWELL_ULT: /* HSW */
3374 case INTEL_FAM6_HASWELL_GT3E: /* HSW */
3375 case INTEL_FAM6_BROADWELL_CORE: /* BDW */
3376 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
3377 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO;
3379 BIC_PRESENT(BIC_Pkg_J);
3380 BIC_PRESENT(BIC_Cor_J);
3381 BIC_PRESENT(BIC_GFX_J);
3383 BIC_PRESENT(BIC_PkgWatt);
3384 BIC_PRESENT(BIC_CorWatt);
3385 BIC_PRESENT(BIC_GFXWatt);
3388 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
3389 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
3390 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO;
3392 BIC_PRESENT(BIC_Pkg_J);
3394 BIC_PRESENT(BIC_PkgWatt);
3396 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3397 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
3398 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
3399 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
3400 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_GFX | RAPL_PKG_POWER_INFO;
3401 BIC_PRESENT(BIC_PKG__);
3402 BIC_PRESENT(BIC_RAM__);
3404 BIC_PRESENT(BIC_Pkg_J);
3405 BIC_PRESENT(BIC_Cor_J);
3406 BIC_PRESENT(BIC_RAM_J);
3407 BIC_PRESENT(BIC_GFX_J);
3409 BIC_PRESENT(BIC_PkgWatt);
3410 BIC_PRESENT(BIC_CorWatt);
3411 BIC_PRESENT(BIC_RAMWatt);
3412 BIC_PRESENT(BIC_GFXWatt);
3415 case INTEL_FAM6_HASWELL_X: /* HSX */
3416 case INTEL_FAM6_BROADWELL_X: /* BDX */
3417 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
3418 case INTEL_FAM6_SKYLAKE_X: /* SKX */
3419 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
3420 case INTEL_FAM6_XEON_PHI_KNM:
3421 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
3422 BIC_PRESENT(BIC_PKG__);
3423 BIC_PRESENT(BIC_RAM__);
3425 BIC_PRESENT(BIC_Pkg_J);
3426 BIC_PRESENT(BIC_RAM_J);
3428 BIC_PRESENT(BIC_PkgWatt);
3429 BIC_PRESENT(BIC_RAMWatt);
3432 case INTEL_FAM6_SANDYBRIDGE_X:
3433 case INTEL_FAM6_IVYBRIDGE_X:
3434 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO;
3435 BIC_PRESENT(BIC_PKG__);
3436 BIC_PRESENT(BIC_RAM__);
3438 BIC_PRESENT(BIC_Pkg_J);
3439 BIC_PRESENT(BIC_Cor_J);
3440 BIC_PRESENT(BIC_RAM_J);
3442 BIC_PRESENT(BIC_PkgWatt);
3443 BIC_PRESENT(BIC_CorWatt);
3444 BIC_PRESENT(BIC_RAMWatt);
3447 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
3448 case INTEL_FAM6_ATOM_SILVERMONT_X: /* AVN */
3449 do_rapl = RAPL_PKG | RAPL_CORES;
3451 BIC_PRESENT(BIC_Pkg_J);
3452 BIC_PRESENT(BIC_Cor_J);
3454 BIC_PRESENT(BIC_PkgWatt);
3455 BIC_PRESENT(BIC_CorWatt);
3458 case INTEL_FAM6_ATOM_GOLDMONT_X: /* DNV */
3459 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS;
3460 BIC_PRESENT(BIC_PKG__);
3461 BIC_PRESENT(BIC_RAM__);
3463 BIC_PRESENT(BIC_Pkg_J);
3464 BIC_PRESENT(BIC_Cor_J);
3465 BIC_PRESENT(BIC_RAM_J);
3467 BIC_PRESENT(BIC_PkgWatt);
3468 BIC_PRESENT(BIC_CorWatt);
3469 BIC_PRESENT(BIC_RAMWatt);
3476 /* units on package 0, verify later other packages match */
3477 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr))
3480 rapl_power_units = 1.0 / (1 << (msr & 0xF));
3481 if (model == INTEL_FAM6_ATOM_SILVERMONT)
3482 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000;
3484 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F));
3486 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units);
3488 time_unit = msr >> 16 & 0xF;
3492 rapl_time_units = 1.0 / (1 << (time_unit));
3494 tdp = get_tdp(model);
3496 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp;
3498 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp);
3503 void perf_limit_reasons_probe(unsigned int family, unsigned int model)
3512 case INTEL_FAM6_HASWELL_CORE: /* HSW */
3513 case INTEL_FAM6_HASWELL_ULT: /* HSW */
3514 case INTEL_FAM6_HASWELL_GT3E: /* HSW */
3515 do_gfx_perf_limit_reasons = 1;
3516 case INTEL_FAM6_HASWELL_X: /* HSX */
3517 do_core_perf_limit_reasons = 1;
3518 do_ring_perf_limit_reasons = 1;
3524 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3526 unsigned long long msr;
3527 unsigned int dts, dts2;
3530 if (!(do_dts || do_ptm))
3535 /* DTS is per-core, no need to print for each thread */
3536 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
3539 if (cpu_migrate(cpu)) {
3540 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
3544 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) {
3545 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
3548 dts = (msr >> 16) & 0x7F;
3549 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n",
3550 cpu, msr, tcc_activation_temp - dts);
3552 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr))
3555 dts = (msr >> 16) & 0x7F;
3556 dts2 = (msr >> 8) & 0x7F;
3557 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
3558 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2);
3562 if (do_dts && debug) {
3563 unsigned int resolution;
3565 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
3568 dts = (msr >> 16) & 0x7F;
3569 resolution = (msr >> 27) & 0xF;
3570 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n",
3571 cpu, msr, tcc_activation_temp - dts, resolution);
3573 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr))
3576 dts = (msr >> 16) & 0x7F;
3577 dts2 = (msr >> 8) & 0x7F;
3578 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
3579 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2);
3585 void print_power_limit_msr(int cpu, unsigned long long msr, char *label)
3587 fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n",
3589 ((msr >> 15) & 1) ? "EN" : "DIS",
3590 ((msr >> 0) & 0x7FFF) * rapl_power_units,
3591 (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units,
3592 (((msr >> 16) & 1) ? "EN" : "DIS"));
3597 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3599 unsigned long long msr;
3605 /* RAPL counters are per package, so print only for 1st thread/package */
3606 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
3610 if (cpu_migrate(cpu)) {
3611 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
3615 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr))
3618 fprintf(outf, "cpu%d: MSR_RAPL_POWER_UNIT: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu, msr,
3619 rapl_power_units, rapl_energy_units, rapl_time_units);
3621 if (do_rapl & RAPL_PKG_POWER_INFO) {
3623 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr))
3627 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
3629 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3630 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3631 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3632 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
3635 if (do_rapl & RAPL_PKG) {
3637 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr))
3640 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n",
3641 cpu, msr, (msr >> 63) & 1 ? "" : "UN");
3643 print_power_limit_msr(cpu, msr, "PKG Limit #1");
3644 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n",
3646 ((msr >> 47) & 1) ? "EN" : "DIS",
3647 ((msr >> 32) & 0x7FFF) * rapl_power_units,
3648 (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units,
3649 ((msr >> 48) & 1) ? "EN" : "DIS");
3652 if (do_rapl & RAPL_DRAM_POWER_INFO) {
3653 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr))
3656 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
3658 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3659 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3660 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3661 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
3663 if (do_rapl & RAPL_DRAM) {
3664 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr))
3666 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n",
3667 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
3669 print_power_limit_msr(cpu, msr, "DRAM Limit");
3671 if (do_rapl & RAPL_CORE_POLICY) {
3672 if (get_msr(cpu, MSR_PP0_POLICY, &msr))
3675 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF);
3677 if (do_rapl & RAPL_CORES_POWER_LIMIT) {
3678 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr))
3680 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n",
3681 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
3682 print_power_limit_msr(cpu, msr, "Cores Limit");
3684 if (do_rapl & RAPL_GFX) {
3685 if (get_msr(cpu, MSR_PP1_POLICY, &msr))
3688 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF);
3690 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr))
3692 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n",
3693 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
3694 print_power_limit_msr(cpu, msr, "GFX Limit");
3700 * SNB adds support for additional MSRs:
3702 * MSR_PKG_C7_RESIDENCY 0x000003fa
3703 * MSR_CORE_C7_RESIDENCY 0x000003fe
3704 * MSR_PKG_C2_RESIDENCY 0x0000060d
3707 int has_snb_msrs(unsigned int family, unsigned int model)
3713 case INTEL_FAM6_SANDYBRIDGE:
3714 case INTEL_FAM6_SANDYBRIDGE_X:
3715 case INTEL_FAM6_IVYBRIDGE: /* IVB */
3716 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
3717 case INTEL_FAM6_HASWELL_CORE: /* HSW */
3718 case INTEL_FAM6_HASWELL_X: /* HSW */
3719 case INTEL_FAM6_HASWELL_ULT: /* HSW */
3720 case INTEL_FAM6_HASWELL_GT3E: /* HSW */
3721 case INTEL_FAM6_BROADWELL_CORE: /* BDW */
3722 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
3723 case INTEL_FAM6_BROADWELL_X: /* BDX */
3724 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
3725 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3726 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
3727 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
3728 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
3729 case INTEL_FAM6_SKYLAKE_X: /* SKX */
3730 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
3731 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
3732 case INTEL_FAM6_ATOM_GOLDMONT_X: /* DNV */
3739 * HSW adds support for additional MSRs:
3741 * MSR_PKG_C8_RESIDENCY 0x00000630
3742 * MSR_PKG_C9_RESIDENCY 0x00000631
3743 * MSR_PKG_C10_RESIDENCY 0x00000632
3745 * MSR_PKGC8_IRTL 0x00000633
3746 * MSR_PKGC9_IRTL 0x00000634
3747 * MSR_PKGC10_IRTL 0x00000635
3750 int has_hsw_msrs(unsigned int family, unsigned int model)
3756 case INTEL_FAM6_HASWELL_ULT: /* HSW */
3757 case INTEL_FAM6_BROADWELL_CORE: /* BDW */
3758 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3759 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
3760 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
3761 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
3762 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
3763 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
3770 * SKL adds support for additional MSRS:
3772 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
3773 * MSR_PKG_ANY_CORE_C0_RES 0x00000659
3774 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
3775 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
3777 int has_skl_msrs(unsigned int family, unsigned int model)
3783 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3784 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
3785 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
3786 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
3792 int is_slm(unsigned int family, unsigned int model)
3797 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
3798 case INTEL_FAM6_ATOM_SILVERMONT_X: /* AVN */
3804 int is_knl(unsigned int family, unsigned int model)
3809 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
3810 case INTEL_FAM6_XEON_PHI_KNM:
3816 unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model)
3818 if (is_knl(family, model))
3823 #define SLM_BCLK_FREQS 5
3824 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0};
3826 double slm_bclk(void)
3828 unsigned long long msr = 3;
3832 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr))
3833 fprintf(outf, "SLM BCLK: unknown\n");
3836 if (i >= SLM_BCLK_FREQS) {
3837 fprintf(outf, "SLM BCLK[%d] invalid\n", i);
3840 freq = slm_freq_table[i];
3843 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq);
3848 double discover_bclk(unsigned int family, unsigned int model)
3850 if (has_snb_msrs(family, model) || is_knl(family, model))
3852 else if (is_slm(family, model))
3859 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where
3860 * the Thermal Control Circuit (TCC) activates.
3861 * This is usually equal to tjMax.
3863 * Older processors do not have this MSR, so there we guess,
3864 * but also allow cmdline over-ride with -T.
3866 * Several MSR temperature values are in units of degrees-C
3867 * below this value, including the Digital Thermal Sensor (DTS),
3868 * Package Thermal Management Sensor (PTM), and thermal event thresholds.
3870 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3872 unsigned long long msr;
3873 unsigned int target_c_local;
3876 /* tcc_activation_temp is used only for dts or ptm */
3877 if (!(do_dts || do_ptm))
3880 /* this is a per-package concept */
3881 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
3885 if (cpu_migrate(cpu)) {
3886 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
3890 if (tcc_activation_temp_override != 0) {
3891 tcc_activation_temp = tcc_activation_temp_override;
3892 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n",
3893 cpu, tcc_activation_temp);
3897 /* Temperature Target MSR is Nehalem and newer only */
3898 if (!do_nhm_platform_info)
3901 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr))
3904 target_c_local = (msr >> 16) & 0xFF;
3907 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n",
3908 cpu, msr, target_c_local);
3910 if (!target_c_local)
3913 tcc_activation_temp = target_c_local;
3918 tcc_activation_temp = TJMAX_DEFAULT;
3919 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n",
3920 cpu, tcc_activation_temp);
3925 void decode_feature_control_msr(void)
3927 unsigned long long msr;
3929 if (!get_msr(base_cpu, MSR_IA32_FEATURE_CONTROL, &msr))
3930 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n",
3932 msr & FEATURE_CONTROL_LOCKED ? "" : "UN-",
3933 msr & (1 << 18) ? "SGX" : "");
3936 void decode_misc_enable_msr(void)
3938 unsigned long long msr;
3943 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr))
3944 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n",
3946 msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-",
3947 msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-",
3948 msr & MSR_IA32_MISC_ENABLE_MWAIT ? "No-" : "",
3949 msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "",
3950 msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : "");
3953 void decode_misc_feature_control(void)
3955 unsigned long long msr;
3957 if (!has_misc_feature_control)
3960 if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr))
3961 fprintf(outf, "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n",
3963 msr & (0 << 0) ? "No-" : "",
3964 msr & (1 << 0) ? "No-" : "",
3965 msr & (2 << 0) ? "No-" : "",
3966 msr & (3 << 0) ? "No-" : "");
3969 * Decode MSR_MISC_PWR_MGMT
3971 * Decode the bits according to the Nehalem documentation
3972 * bit[0] seems to continue to have same meaning going forward
3975 void decode_misc_pwr_mgmt_msr(void)
3977 unsigned long long msr;
3979 if (!do_nhm_platform_info)
3982 if (no_MSR_MISC_PWR_MGMT)
3985 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr))
3986 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n",
3988 msr & (1 << 0) ? "DIS" : "EN",
3989 msr & (1 << 1) ? "EN" : "DIS",
3990 msr & (1 << 8) ? "EN" : "DIS");
3993 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG
3995 * This MSRs are present on Silvermont processors,
3996 * Intel Atom processor E3000 series (Baytrail), and friends.
3998 void decode_c6_demotion_policy_msr(void)
4000 unsigned long long msr;
4002 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr))
4003 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n",
4004 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
4006 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr))
4007 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n",
4008 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
4011 void process_cpuid()
4013 unsigned int eax, ebx, ecx, edx, max_level, max_extended_level;
4014 unsigned int fms, family, model, stepping;
4015 unsigned int has_turbo;
4017 eax = ebx = ecx = edx = 0;
4019 __cpuid(0, max_level, ebx, ecx, edx);
4021 if (ebx == 0x756e6547 && edx == 0x49656e69 && ecx == 0x6c65746e)
4025 fprintf(outf, "CPUID(0): %.4s%.4s%.4s ",
4026 (char *)&ebx, (char *)&edx, (char *)&ecx);
4028 __cpuid(1, fms, ebx, ecx, edx);
4029 family = (fms >> 8) & 0xf;
4030 model = (fms >> 4) & 0xf;
4031 stepping = fms & 0xf;
4033 family += (fms >> 20) & 0xff;
4035 model += ((fms >> 16) & 0xf) << 4;
4038 fprintf(outf, "%d CPUID levels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n",
4039 max_level, family, model, stepping, family, model, stepping);
4040 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s\n",
4041 ecx & (1 << 0) ? "SSE3" : "-",
4042 ecx & (1 << 3) ? "MONITOR" : "-",
4043 ecx & (1 << 6) ? "SMX" : "-",
4044 ecx & (1 << 7) ? "EIST" : "-",
4045 ecx & (1 << 8) ? "TM2" : "-",
4046 edx & (1 << 4) ? "TSC" : "-",
4047 edx & (1 << 5) ? "MSR" : "-",
4048 edx & (1 << 22) ? "ACPI-TM" : "-",
4049 edx & (1 << 29) ? "TM" : "-");
4052 if (!(edx & (1 << 5)))
4053 errx(1, "CPUID: no MSR");
4056 * check max extended function levels of CPUID.
4057 * This is needed to check for invariant TSC.
4058 * This check is valid for both Intel and AMD.
4060 ebx = ecx = edx = 0;
4061 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx);
4063 if (max_extended_level >= 0x80000007) {
4066 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8
4067 * this check is valid for both Intel and AMD
4069 __cpuid(0x80000007, eax, ebx, ecx, edx);
4070 has_invariant_tsc = edx & (1 << 8);
4074 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0
4075 * this check is valid for both Intel and AMD
4078 __cpuid(0x6, eax, ebx, ecx, edx);
4079 has_aperf = ecx & (1 << 0);
4081 BIC_PRESENT(BIC_Avg_MHz);
4082 BIC_PRESENT(BIC_Busy);
4083 BIC_PRESENT(BIC_Bzy_MHz);
4085 do_dts = eax & (1 << 0);
4087 BIC_PRESENT(BIC_CoreTmp);
4088 has_turbo = eax & (1 << 1);
4089 do_ptm = eax & (1 << 6);
4091 BIC_PRESENT(BIC_PkgTmp);
4092 has_hwp = eax & (1 << 7);
4093 has_hwp_notify = eax & (1 << 8);
4094 has_hwp_activity_window = eax & (1 << 9);
4095 has_hwp_epp = eax & (1 << 10);
4096 has_hwp_pkg = eax & (1 << 11);
4097 has_epb = ecx & (1 << 3);
4100 fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, "
4101 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n",
4102 has_aperf ? "" : "No-",
4103 has_turbo ? "" : "No-",
4104 do_dts ? "" : "No-",
4105 do_ptm ? "" : "No-",
4106 has_hwp ? "" : "No-",
4107 has_hwp_notify ? "" : "No-",
4108 has_hwp_activity_window ? "" : "No-",
4109 has_hwp_epp ? "" : "No-",
4110 has_hwp_pkg ? "" : "No-",
4111 has_epb ? "" : "No-");
4114 decode_misc_enable_msr();
4117 if (max_level >= 0x7 && !quiet) {
4122 __cpuid_count(0x7, 0, eax, ebx, ecx, edx);
4124 has_sgx = ebx & (1 << 2);
4125 fprintf(outf, "CPUID(7): %sSGX\n", has_sgx ? "" : "No-");
4128 decode_feature_control_msr();
4131 if (max_level >= 0x15) {
4132 unsigned int eax_crystal;
4133 unsigned int ebx_tsc;
4136 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz
4138 eax_crystal = ebx_tsc = crystal_hz = edx = 0;
4139 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx);
4143 if (!quiet && (ebx != 0))
4144 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n",
4145 eax_crystal, ebx_tsc, crystal_hz);
4147 if (crystal_hz == 0)
4149 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
4150 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
4151 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
4152 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
4153 crystal_hz = 24000000; /* 24.0 MHz */
4155 case INTEL_FAM6_SKYLAKE_X: /* SKX */
4156 case INTEL_FAM6_ATOM_GOLDMONT_X: /* DNV */
4157 crystal_hz = 25000000; /* 25.0 MHz */
4159 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
4160 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
4161 crystal_hz = 19200000; /* 19.2 MHz */
4168 tsc_hz = (unsigned long long) crystal_hz * ebx_tsc / eax_crystal;
4170 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n",
4171 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal);
4175 if (max_level >= 0x16) {
4176 unsigned int base_mhz, max_mhz, bus_mhz, edx;
4179 * CPUID 16H Base MHz, Max MHz, Bus MHz
4181 base_mhz = max_mhz = bus_mhz = edx = 0;
4183 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx);
4185 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n",
4186 base_mhz, max_mhz, bus_mhz);
4190 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model);
4192 BIC_PRESENT(BIC_IRQ);
4193 BIC_PRESENT(BIC_TSC_MHz);
4195 if (probe_nhm_msrs(family, model)) {
4196 do_nhm_platform_info = 1;
4197 BIC_PRESENT(BIC_CPU_c1);
4198 BIC_PRESENT(BIC_CPU_c3);
4199 BIC_PRESENT(BIC_CPU_c6);
4200 BIC_PRESENT(BIC_SMI);
4202 do_snb_cstates = has_snb_msrs(family, model);
4205 BIC_PRESENT(BIC_CPU_c7);
4207 do_irtl_snb = has_snb_msrs(family, model);
4208 if (do_snb_cstates && (pkg_cstate_limit >= PCL__2))
4209 BIC_PRESENT(BIC_Pkgpc2);
4210 if (pkg_cstate_limit >= PCL__3)
4211 BIC_PRESENT(BIC_Pkgpc3);
4212 if (pkg_cstate_limit >= PCL__6)
4213 BIC_PRESENT(BIC_Pkgpc6);
4214 if (do_snb_cstates && (pkg_cstate_limit >= PCL__7))
4215 BIC_PRESENT(BIC_Pkgpc7);
4216 if (has_slv_msrs(family, model)) {
4217 BIC_NOT_PRESENT(BIC_Pkgpc2);
4218 BIC_NOT_PRESENT(BIC_Pkgpc3);
4219 BIC_PRESENT(BIC_Pkgpc6);
4220 BIC_NOT_PRESENT(BIC_Pkgpc7);
4221 BIC_PRESENT(BIC_Mod_c6);
4222 use_c1_residency_msr = 1;
4224 if (is_dnv(family, model)) {
4225 BIC_PRESENT(BIC_CPU_c1);
4226 BIC_NOT_PRESENT(BIC_CPU_c3);
4227 BIC_NOT_PRESENT(BIC_Pkgpc3);
4228 BIC_NOT_PRESENT(BIC_CPU_c7);
4229 BIC_NOT_PRESENT(BIC_Pkgpc7);
4230 use_c1_residency_msr = 1;
4232 if (is_skx(family, model)) {
4233 BIC_NOT_PRESENT(BIC_CPU_c3);
4234 BIC_NOT_PRESENT(BIC_Pkgpc3);
4235 BIC_NOT_PRESENT(BIC_CPU_c7);
4236 BIC_NOT_PRESENT(BIC_Pkgpc7);
4238 if (is_bdx(family, model)) {
4239 BIC_NOT_PRESENT(BIC_CPU_c7);
4240 BIC_NOT_PRESENT(BIC_Pkgpc7);
4242 if (has_hsw_msrs(family, model)) {
4243 BIC_PRESENT(BIC_Pkgpc8);
4244 BIC_PRESENT(BIC_Pkgpc9);
4245 BIC_PRESENT(BIC_Pkgpc10);
4247 do_irtl_hsw = has_hsw_msrs(family, model);
4248 if (has_skl_msrs(family, model)) {
4249 BIC_PRESENT(BIC_Totl_c0);
4250 BIC_PRESENT(BIC_Any_c0);
4251 BIC_PRESENT(BIC_GFX_c0);
4252 BIC_PRESENT(BIC_CPUGFX);
4254 do_slm_cstates = is_slm(family, model);
4255 do_knl_cstates = is_knl(family, model);
4258 decode_misc_pwr_mgmt_msr();
4260 if (!quiet && has_slv_msrs(family, model))
4261 decode_c6_demotion_policy_msr();
4263 rapl_probe(family, model);
4264 perf_limit_reasons_probe(family, model);
4267 dump_cstate_pstate_config_info(family, model);
4270 dump_sysfs_cstate_config();
4272 dump_sysfs_pstate_config();
4274 if (has_skl_msrs(family, model))
4275 calculate_tsc_tweak();
4277 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK))
4278 BIC_PRESENT(BIC_GFX_rc6);
4280 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK))
4281 BIC_PRESENT(BIC_GFXMHz);
4284 decode_misc_feature_control();
4291 * in /dev/cpu/ return success for names that are numbers
4292 * ie. filter out ".", "..", "microcode".
4294 int dir_filter(const struct dirent *dirp)
4296 if (isdigit(dirp->d_name[0]))
4302 int open_dev_cpu_msr(int dummy1)
4307 void topology_probe()
4310 int max_core_id = 0;
4311 int max_package_id = 0;
4312 int max_siblings = 0;
4313 struct cpu_topology {
4315 int physical_package_id;
4318 /* Initialize num_cpus, max_cpu_num */
4320 topo.max_cpu_num = 0;
4321 for_all_proc_cpus(count_cpus);
4322 if (!summary_only && topo.num_cpus > 1)
4323 BIC_PRESENT(BIC_CPU);
4326 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num);
4328 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology));
4330 err(1, "calloc cpus");
4333 * Allocate and initialize cpu_present_set
4335 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1));
4336 if (cpu_present_set == NULL)
4337 err(3, "CPU_ALLOC");
4338 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
4339 CPU_ZERO_S(cpu_present_setsize, cpu_present_set);
4340 for_all_proc_cpus(mark_cpu_present);
4343 * Validate that all cpus in cpu_subset are also in cpu_present_set
4345 for (i = 0; i < CPU_SUBSET_MAXCPUS; ++i) {
4346 if (CPU_ISSET_S(i, cpu_subset_size, cpu_subset))
4347 if (!CPU_ISSET_S(i, cpu_present_setsize, cpu_present_set))
4348 err(1, "cpu%d not present", i);
4352 * Allocate and initialize cpu_affinity_set
4354 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1));
4355 if (cpu_affinity_set == NULL)
4356 err(3, "CPU_ALLOC");
4357 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
4358 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
4363 * find max_core_id, max_package_id
4365 for (i = 0; i <= topo.max_cpu_num; ++i) {
4368 if (cpu_is_not_present(i)) {
4370 fprintf(outf, "cpu%d NOT PRESENT\n", i);
4373 cpus[i].core_id = get_core_id(i);
4374 if (cpus[i].core_id > max_core_id)
4375 max_core_id = cpus[i].core_id;
4377 cpus[i].physical_package_id = get_physical_package_id(i);
4378 if (cpus[i].physical_package_id > max_package_id)
4379 max_package_id = cpus[i].physical_package_id;
4381 siblings = get_num_ht_siblings(i);
4382 if (siblings > max_siblings)
4383 max_siblings = siblings;
4385 fprintf(outf, "cpu %d pkg %d core %d\n",
4386 i, cpus[i].physical_package_id, cpus[i].core_id);
4388 topo.num_cores_per_pkg = max_core_id + 1;
4390 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n",
4391 max_core_id, topo.num_cores_per_pkg);
4392 if (!summary_only && topo.num_cores_per_pkg > 1)
4393 BIC_PRESENT(BIC_Core);
4395 topo.num_packages = max_package_id + 1;
4397 fprintf(outf, "max_package_id %d, sizing for %d packages\n",
4398 max_package_id, topo.num_packages);
4399 if (!summary_only && topo.num_packages > 1)
4400 BIC_PRESENT(BIC_Package);
4402 topo.num_threads_per_core = max_siblings;
4404 fprintf(outf, "max_siblings %d\n", max_siblings);
4410 allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p)
4414 *t = calloc(topo.num_threads_per_core * topo.num_cores_per_pkg *
4415 topo.num_packages, sizeof(struct thread_data));
4419 for (i = 0; i < topo.num_threads_per_core *
4420 topo.num_cores_per_pkg * topo.num_packages; i++)
4421 (*t)[i].cpu_id = -1;
4423 *c = calloc(topo.num_cores_per_pkg * topo.num_packages,
4424 sizeof(struct core_data));
4428 for (i = 0; i < topo.num_cores_per_pkg * topo.num_packages; i++)
4429 (*c)[i].core_id = -1;
4431 *p = calloc(topo.num_packages, sizeof(struct pkg_data));
4435 for (i = 0; i < topo.num_packages; i++)
4436 (*p)[i].package_id = i;
4440 err(1, "calloc counters");
4445 * set cpu_id, core_num, pkg_num
4446 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE
4448 * increment topo.num_cores when 1st core in pkg seen
4450 void init_counter(struct thread_data *thread_base, struct core_data *core_base,
4451 struct pkg_data *pkg_base, int thread_num, int core_num,
4452 int pkg_num, int cpu_id)
4454 struct thread_data *t;
4455 struct core_data *c;
4458 t = GET_THREAD(thread_base, thread_num, core_num, pkg_num);
4459 c = GET_CORE(core_base, core_num, pkg_num);
4460 p = GET_PKG(pkg_base, pkg_num);
4463 if (thread_num == 0) {
4464 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE;
4465 if (cpu_is_first_core_in_package(cpu_id))
4466 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE;
4469 c->core_id = core_num;
4470 p->package_id = pkg_num;
4474 int initialize_counters(int cpu_id)
4476 int my_thread_id, my_core_id, my_package_id;
4478 my_package_id = get_physical_package_id(cpu_id);
4479 my_core_id = get_core_id(cpu_id);
4480 my_thread_id = get_cpu_position_in_core(cpu_id);
4484 init_counter(EVEN_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id);
4485 init_counter(ODD_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id);
4489 void allocate_output_buffer()
4491 output_buffer = calloc(1, (1 + topo.num_cpus) * 2048);
4492 outp = output_buffer;
4494 err(-1, "calloc output buffer");
4496 void allocate_fd_percpu(void)
4498 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int));
4499 if (fd_percpu == NULL)
4500 err(-1, "calloc fd_percpu");
4502 void allocate_irq_buffers(void)
4504 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int));
4505 if (irq_column_2_cpu == NULL)
4506 err(-1, "calloc %d", topo.num_cpus);
4508 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int));
4509 if (irqs_per_cpu == NULL)
4510 err(-1, "calloc %d", topo.max_cpu_num + 1);
4512 void setup_all_buffers(void)
4515 allocate_irq_buffers();
4516 allocate_fd_percpu();
4517 allocate_counters(&thread_even, &core_even, &package_even);
4518 allocate_counters(&thread_odd, &core_odd, &package_odd);
4519 allocate_output_buffer();
4520 for_all_proc_cpus(initialize_counters);
4523 void set_base_cpu(void)
4525 base_cpu = sched_getcpu();
4527 err(-ENODEV, "No valid cpus found");
4530 fprintf(outf, "base_cpu = %d\n", base_cpu);
4533 void turbostat_init()
4535 setup_all_buffers();
4538 check_permissions();
4543 for_all_cpus(print_hwp, ODD_COUNTERS);
4546 for_all_cpus(print_epb, ODD_COUNTERS);
4549 for_all_cpus(print_perf_limit, ODD_COUNTERS);
4552 for_all_cpus(print_rapl, ODD_COUNTERS);
4554 for_all_cpus(set_temperature_target, ODD_COUNTERS);
4557 for_all_cpus(print_thermal, ODD_COUNTERS);
4559 if (!quiet && do_irtl_snb)
4563 int fork_it(char **argv)
4568 snapshot_proc_sysfs_files();
4569 status = for_all_cpus(get_counters, EVEN_COUNTERS);
4572 /* clear affinity side-effect of get_counters() */
4573 sched_setaffinity(0, cpu_present_setsize, cpu_present_set);
4574 gettimeofday(&tv_even, (struct timezone *)NULL);
4579 execvp(argv[0], argv);
4580 err(errno, "exec %s", argv[0]);
4584 if (child_pid == -1)
4587 signal(SIGINT, SIG_IGN);
4588 signal(SIGQUIT, SIG_IGN);
4589 if (waitpid(child_pid, &status, 0) == -1)
4590 err(status, "waitpid");
4592 if (WIFEXITED(status))
4593 status = WEXITSTATUS(status);
4596 * n.b. fork_it() does not check for errors from for_all_cpus()
4597 * because re-starting is problematic when forking
4599 snapshot_proc_sysfs_files();
4600 for_all_cpus(get_counters, ODD_COUNTERS);
4601 gettimeofday(&tv_odd, (struct timezone *)NULL);
4602 timersub(&tv_odd, &tv_even, &tv_delta);
4603 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS))
4604 fprintf(outf, "%s: Counter reset detected\n", progname);
4606 compute_average(EVEN_COUNTERS);
4607 format_all_counters(EVEN_COUNTERS);
4610 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0);
4612 flush_output_stderr();
4617 int get_and_dump_counters(void)
4621 snapshot_proc_sysfs_files();
4622 status = for_all_cpus(get_counters, ODD_COUNTERS);
4626 status = for_all_cpus(dump_counters, ODD_COUNTERS);
4630 flush_output_stdout();
4635 void print_version() {
4636 fprintf(outf, "turbostat version 17.06.23"
4637 " - Len Brown <lenb@kernel.org>\n");
4640 int add_counter(unsigned int msr_num, char *path, char *name,
4641 unsigned int width, enum counter_scope scope,
4642 enum counter_type type, enum counter_format format, int flags)
4644 struct msr_counter *msrp;
4646 msrp = calloc(1, sizeof(struct msr_counter));
4652 msrp->msr_num = msr_num;
4653 strncpy(msrp->name, name, NAME_BYTES - 1);
4655 strncpy(msrp->path, path, PATH_BYTES - 1);
4656 msrp->width = width;
4658 msrp->format = format;
4659 msrp->flags = flags;
4664 msrp->next = sys.tp;
4666 sys.added_thread_counters++;
4667 if (sys.added_thread_counters > MAX_ADDED_COUNTERS) {
4668 fprintf(stderr, "exceeded max %d added thread counters\n",
4669 MAX_ADDED_COUNTERS);
4675 msrp->next = sys.cp;
4677 sys.added_core_counters++;
4678 if (sys.added_core_counters > MAX_ADDED_COUNTERS) {
4679 fprintf(stderr, "exceeded max %d added core counters\n",
4680 MAX_ADDED_COUNTERS);
4686 msrp->next = sys.pp;
4688 sys.added_package_counters++;
4689 if (sys.added_package_counters > MAX_ADDED_COUNTERS) {
4690 fprintf(stderr, "exceeded max %d added package counters\n",
4691 MAX_ADDED_COUNTERS);
4700 void parse_add_command(char *add_command)
4704 char name_buffer[NAME_BYTES] = "";
4707 enum counter_scope scope = SCOPE_CPU;
4708 enum counter_type type = COUNTER_CYCLES;
4709 enum counter_format format = FORMAT_DELTA;
4711 while (add_command) {
4713 if (sscanf(add_command, "msr0x%x", &msr_num) == 1)
4716 if (sscanf(add_command, "msr%d", &msr_num) == 1)
4719 if (*add_command == '/') {
4724 if (sscanf(add_command, "u%d", &width) == 1) {
4725 if ((width == 32) || (width == 64))
4729 if (!strncmp(add_command, "cpu", strlen("cpu"))) {
4733 if (!strncmp(add_command, "core", strlen("core"))) {
4737 if (!strncmp(add_command, "package", strlen("package"))) {
4738 scope = SCOPE_PACKAGE;
4741 if (!strncmp(add_command, "cycles", strlen("cycles"))) {
4742 type = COUNTER_CYCLES;
4745 if (!strncmp(add_command, "seconds", strlen("seconds"))) {
4746 type = COUNTER_SECONDS;
4749 if (!strncmp(add_command, "usec", strlen("usec"))) {
4750 type = COUNTER_USEC;
4753 if (!strncmp(add_command, "raw", strlen("raw"))) {
4754 format = FORMAT_RAW;
4757 if (!strncmp(add_command, "delta", strlen("delta"))) {
4758 format = FORMAT_DELTA;
4761 if (!strncmp(add_command, "percent", strlen("percent"))) {
4762 format = FORMAT_PERCENT;
4766 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */
4769 eos = strchr(name_buffer, ',');
4776 add_command = strchr(add_command, ',');
4778 *add_command = '\0';
4783 if ((msr_num == 0) && (path == NULL)) {
4784 fprintf(stderr, "--add: (msrDDD | msr0xXXX | /path_to_counter ) required\n");
4788 /* generate default column header */
4789 if (*name_buffer == '\0') {
4791 sprintf(name_buffer, "M0x%x%s", msr_num, format == FORMAT_PERCENT ? "%" : "");
4793 sprintf(name_buffer, "M0X%x%s", msr_num, format == FORMAT_PERCENT ? "%" : "");
4796 if (add_counter(msr_num, path, name_buffer, width, scope, type, format, 0))
4805 int is_deferred_skip(char *name)
4809 for (i = 0; i < deferred_skip_index; ++i)
4810 if (!strcmp(name, deferred_skip_names[i]))
4815 void probe_sysfs(void)
4823 if (!DO_BIC(BIC_sysfs))
4826 for (state = 10; state > 0; --state) {
4828 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name",
4830 input = fopen(path, "r");
4833 fgets(name_buf, sizeof(name_buf), input);
4835 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
4836 sp = strchr(name_buf, '-');
4838 sp = strchrnul(name_buf, '\n');
4844 sprintf(path, "cpuidle/state%d/time", state);
4846 if (is_deferred_skip(name_buf))
4849 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_USEC,
4850 FORMAT_PERCENT, SYSFS_PERCPU);
4853 for (state = 10; state > 0; --state) {
4855 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name",
4857 input = fopen(path, "r");
4860 fgets(name_buf, sizeof(name_buf), input);
4861 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
4862 sp = strchr(name_buf, '-');
4864 sp = strchrnul(name_buf, '\n');
4868 sprintf(path, "cpuidle/state%d/usage", state);
4870 if (is_deferred_skip(name_buf))
4873 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_ITEMS,
4874 FORMAT_DELTA, SYSFS_PERCPU);
4881 * parse cpuset with following syntax
4882 * 1,2,4..6,8-10 and set bits in cpu_subset
4884 void parse_cpu_command(char *optarg)
4886 unsigned int start, end;
4889 if (!strcmp(optarg, "core")) {
4895 if (!strcmp(optarg, "package")) {
4901 if (show_core_only || show_pkg_only)
4904 cpu_subset = CPU_ALLOC(CPU_SUBSET_MAXCPUS);
4905 if (cpu_subset == NULL)
4906 err(3, "CPU_ALLOC");
4907 cpu_subset_size = CPU_ALLOC_SIZE(CPU_SUBSET_MAXCPUS);
4909 CPU_ZERO_S(cpu_subset_size, cpu_subset);
4913 while (next && *next) {
4915 if (*next == '-') /* no negative cpu numbers */
4918 start = strtoul(next, &next, 10);
4920 if (start >= CPU_SUBSET_MAXCPUS)
4922 CPU_SET_S(start, cpu_subset_size, cpu_subset);
4933 next += 1; /* start range */
4934 } else if (*next == '.') {
4937 next += 1; /* start range */
4942 end = strtoul(next, &next, 10);
4946 while (++start <= end) {
4947 if (start >= CPU_SUBSET_MAXCPUS)
4949 CPU_SET_S(start, cpu_subset_size, cpu_subset);
4954 else if (*next != '\0')
4961 fprintf(stderr, "\"--cpu %s\" malformed\n", optarg);
4968 * parse_show_hide() - process cmdline to set default counter action
4970 void parse_show_hide(char *optarg, enum show_hide_mode new_mode)
4973 * --show: show only those specified
4974 * The 1st invocation will clear and replace the enabled mask
4975 * subsequent invocations can add to it.
4977 if (new_mode == SHOW_LIST) {
4979 bic_enabled = bic_lookup(optarg, new_mode);
4981 bic_enabled |= bic_lookup(optarg, new_mode);
4988 * --hide: do not show those specified
4989 * multiple invocations simply clear more bits in enabled mask
4991 bic_enabled &= ~bic_lookup(optarg, new_mode);
4995 void cmdline(int argc, char **argv)
4998 int option_index = 0;
4999 static struct option long_options[] = {
5000 {"add", required_argument, 0, 'a'},
5001 {"cpu", required_argument, 0, 'c'},
5002 {"Dump", no_argument, 0, 'D'},
5003 {"debug", no_argument, 0, 'd'}, /* internal, not documented */
5004 {"interval", required_argument, 0, 'i'},
5005 {"help", no_argument, 0, 'h'},
5006 {"hide", required_argument, 0, 'H'}, // meh, -h taken by --help
5007 {"Joules", no_argument, 0, 'J'},
5008 {"list", no_argument, 0, 'l'},
5009 {"out", required_argument, 0, 'o'},
5010 {"quiet", no_argument, 0, 'q'},
5011 {"show", required_argument, 0, 's'},
5012 {"Summary", no_argument, 0, 'S'},
5013 {"TCC", required_argument, 0, 'T'},
5014 {"version", no_argument, 0, 'v' },
5020 while ((opt = getopt_long_only(argc, argv, "+C:c:Ddhi:JM:m:o:qST:v",
5021 long_options, &option_index)) != -1) {
5024 parse_add_command(optarg);
5027 parse_cpu_command(optarg);
5036 parse_show_hide(optarg, HIDE_LIST);
5044 double interval = strtod(optarg, NULL);
5046 if (interval < 0.001) {
5047 fprintf(outf, "interval %f seconds is too small\n",
5052 interval_ts.tv_sec = interval;
5053 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000;
5064 outf = fopen_or_die(optarg, "w");
5070 parse_show_hide(optarg, SHOW_LIST);
5076 tcc_activation_temp_override = atoi(optarg);
5086 int main(int argc, char **argv)
5090 cmdline(argc, argv);
5099 /* dump counters and exit */
5101 return get_and_dump_counters();
5103 /* list header and exit */
5104 if (list_header_only) {
5106 flush_output_stdout();
5111 * if any params left, it must be a command to fork
5114 return fork_it(argv + optind);