1 // SPDX-License-Identifier: GPL-2.0
8 #include "helpers/helpers.h"
10 static const char *cpu_vendor_table[X86_VENDOR_MAX] = {
11 "Unknown", "GenuineIntel", "AuthenticAMD", "HygonGenuine",
14 #if defined(__i386__) || defined(__x86_64__)
20 * CPUID functions returning a single datum
22 * Define unsigned int cpuid_e[abcd]x(unsigned int op)
24 #define cpuid_func(reg) \
25 unsigned int cpuid_##reg(unsigned int op) \
27 unsigned int eax, ebx, ecx, edx; \
28 __cpuid(op, eax, ebx, ecx, edx); \
36 #endif /* defined(__i386__) || defined(__x86_64__) */
40 * Extract CPU vendor, family, model, stepping info from /proc/cpuinfo
42 * Returns 0 on success or a negativ error code
44 * TBD: Should there be a cpuid alternative for this if /proc is not mounted?
46 int get_cpu_info(struct cpupower_cpu_info *cpu_info)
51 unsigned int unknown = 0xffffff;
52 unsigned int cpuid_level, ext_cpuid_level;
56 cpu_info->vendor = X86_VENDOR_UNKNOWN;
57 cpu_info->family = unknown;
58 cpu_info->model = unknown;
59 cpu_info->stepping = unknown;
62 fp = fopen("/proc/cpuinfo", "r");
67 if (!fgets(value, 64, fp))
71 if (!strncmp(value, "processor\t: ", 12))
72 sscanf(value, "processor\t: %u", &proc);
74 if (proc != (unsigned int)base_cpu)
78 if (!strncmp(value, "vendor_id", 9)) {
79 for (x = 1; x < X86_VENDOR_MAX; x++) {
80 if (strstr(value, cpu_vendor_table[x]))
83 /* Get CPU family, etc. */
84 } else if (!strncmp(value, "cpu family\t: ", 13)) {
85 sscanf(value, "cpu family\t: %u",
87 } else if (!strncmp(value, "model\t\t: ", 9)) {
88 sscanf(value, "model\t\t: %u",
90 } else if (!strncmp(value, "stepping\t: ", 10)) {
91 sscanf(value, "stepping\t: %u",
94 /* Exit -> all values must have been set */
95 if (cpu_info->vendor == X86_VENDOR_UNKNOWN ||
96 cpu_info->family == unknown ||
97 cpu_info->model == unknown ||
98 cpu_info->stepping == unknown) {
110 /* Get some useful CPU capabilities from cpuid */
111 if (cpu_info->vendor != X86_VENDOR_AMD &&
112 cpu_info->vendor != X86_VENDOR_HYGON &&
113 cpu_info->vendor != X86_VENDOR_INTEL)
116 cpuid_level = cpuid_eax(0);
117 ext_cpuid_level = cpuid_eax(0x80000000);
120 if (ext_cpuid_level >= 0x80000007 &&
121 (cpuid_edx(0x80000007) & (1 << 8)))
122 cpu_info->caps |= CPUPOWER_CAP_INV_TSC;
124 /* Aperf/Mperf registers support */
125 if (cpuid_level >= 6 && (cpuid_ecx(6) & 0x1))
126 cpu_info->caps |= CPUPOWER_CAP_APERF;
128 /* AMD or Hygon Boost state enable/disable register */
129 if (cpu_info->vendor == X86_VENDOR_AMD ||
130 cpu_info->vendor == X86_VENDOR_HYGON) {
131 if (ext_cpuid_level >= 0x80000007) {
132 if (cpuid_edx(0x80000007) & (1 << 9)) {
133 cpu_info->caps |= CPUPOWER_CAP_AMD_CPB;
135 if (cpu_info->family >= 0x17)
136 cpu_info->caps |= CPUPOWER_CAP_AMD_CPB_MSR;
139 if ((cpuid_edx(0x80000007) & (1 << 7)) &&
140 cpu_info->family != 0x14) {
141 /* HW pstate was not implemented in family 0x14 */
142 cpu_info->caps |= CPUPOWER_CAP_AMD_HW_PSTATE;
144 if (cpu_info->family >= 0x17)
145 cpu_info->caps |= CPUPOWER_CAP_AMD_PSTATEDEF;
149 if (ext_cpuid_level >= 0x80000008 &&
150 cpuid_ebx(0x80000008) & (1 << 4))
151 cpu_info->caps |= CPUPOWER_CAP_AMD_RDPRU;
153 if (cpupower_amd_pstate_enabled()) {
154 cpu_info->caps |= CPUPOWER_CAP_AMD_PSTATE;
157 * If AMD P-State is enabled, the firmware will treat
158 * AMD P-State function as high priority.
160 cpu_info->caps &= ~CPUPOWER_CAP_AMD_CPB;
161 cpu_info->caps &= ~CPUPOWER_CAP_AMD_CPB_MSR;
162 cpu_info->caps &= ~CPUPOWER_CAP_AMD_HW_PSTATE;
163 cpu_info->caps &= ~CPUPOWER_CAP_AMD_PSTATEDEF;
167 if (cpu_info->vendor == X86_VENDOR_INTEL) {
168 if (cpuid_level >= 6 &&
169 (cpuid_eax(6) & (1 << 1)))
170 cpu_info->caps |= CPUPOWER_CAP_INTEL_IDA;
173 if (cpu_info->vendor == X86_VENDOR_INTEL) {
174 /* Intel's perf-bias MSR support */
175 if (cpuid_level >= 6 && (cpuid_ecx(6) & (1 << 3)))
176 cpu_info->caps |= CPUPOWER_CAP_PERF_BIAS;
178 /* Intel's Turbo Ratio Limit support */
179 if (cpu_info->family == 6) {
180 switch (cpu_info->model) {
181 case 0x1A: /* Core i7, Xeon 5500 series
182 * Bloomfield, Gainstown NHM-EP
184 case 0x1E: /* Core i7 and i5 Processor
185 * Clarksfield, Lynnfield, Jasper Forest
187 case 0x1F: /* Core i7 and i5 Processor - Nehalem */
188 case 0x25: /* Westmere Client
189 * Clarkdale, Arrandale
191 case 0x2C: /* Westmere EP - Gulftown */
192 cpu_info->caps |= CPUPOWER_CAP_HAS_TURBO_RATIO;
195 case 0x2D: /* SNB Xeon */
197 case 0x3E: /* IVB Xeon */
198 cpu_info->caps |= CPUPOWER_CAP_HAS_TURBO_RATIO;
199 cpu_info->caps |= CPUPOWER_CAP_IS_SNB;
201 case 0x2E: /* Nehalem-EX Xeon - Beckton */
202 case 0x2F: /* Westmere-EX Xeon - Eagleton */
209 /* printf("ID: %u - Extid: 0x%x - Caps: 0x%llx\n",
210 cpuid_level, ext_cpuid_level, cpu_info->caps);