tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json

   1 [
   2     {
   3         "BriefDescription": "DTLB load misses",
   4         "EventCode": "0x8",
   5         "EventName": "DTLB_LOAD_MISSES.ANY",
   6         "SampleAfterValue": "200000",
   7         "UMask": "0x1"
   8     },
   9     {
  10         "BriefDescription": "DTLB load miss large page walks",
  11         "EventCode": "0x8",
  12         "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED",
  13         "SampleAfterValue": "200000",
  14         "UMask": "0x80"
  15     },
  16     {
  17         "BriefDescription": "DTLB load miss caused by low part of address",
  18         "EventCode": "0x8",
  19         "EventName": "DTLB_LOAD_MISSES.PDE_MISS",
  20         "SampleAfterValue": "200000",
  21         "UMask": "0x20"
  22     },
  23     {
  24         "BriefDescription": "DTLB second level hit",
  25         "EventCode": "0x8",
  26         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
  27         "SampleAfterValue": "2000000",
  28         "UMask": "0x10"
  29     },
  30     {
  31         "BriefDescription": "DTLB load miss page walks complete",
  32         "EventCode": "0x8",
  33         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
  34         "SampleAfterValue": "200000",
  35         "UMask": "0x2"
  36     },
  37     {
  38         "BriefDescription": "DTLB load miss page walk cycles",
  39         "EventCode": "0x8",
  40         "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES",
  41         "SampleAfterValue": "200000",
  42         "UMask": "0x4"
  43     },
  44     {
  45         "BriefDescription": "DTLB misses",
  46         "EventCode": "0x49",
  47         "EventName": "DTLB_MISSES.ANY",
  48         "SampleAfterValue": "200000",
  49         "UMask": "0x1"
  50     },
  51     {
  52         "BriefDescription": "DTLB miss large page walks",
  53         "EventCode": "0x49",
  54         "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED",
  55         "SampleAfterValue": "200000",
  56         "UMask": "0x80"
  57     },
  58     {
  59         "BriefDescription": "DTLB misses caused by low part of address",
  60         "EventCode": "0x49",
  61         "EventName": "DTLB_MISSES.PDE_MISS",
  62         "SampleAfterValue": "200000",
  63         "UMask": "0x20"
  64     },
  65     {
  66         "BriefDescription": "DTLB first level misses but second level hit",
  67         "EventCode": "0x49",
  68         "EventName": "DTLB_MISSES.STLB_HIT",
  69         "SampleAfterValue": "200000",
  70         "UMask": "0x10"
  71     },
  72     {
  73         "BriefDescription": "DTLB miss page walks",
  74         "EventCode": "0x49",
  75         "EventName": "DTLB_MISSES.WALK_COMPLETED",
  76         "SampleAfterValue": "200000",
  77         "UMask": "0x2"
  78     },
  79     {
  80         "BriefDescription": "DTLB miss page walk cycles",
  81         "EventCode": "0x49",
  82         "EventName": "DTLB_MISSES.WALK_CYCLES",
  83         "SampleAfterValue": "2000000",
  84         "UMask": "0x4"
  85     },
  86     {
  87         "BriefDescription": "Extended Page Table walk cycles",
  88         "EventCode": "0x4F",
  89         "EventName": "EPT.WALK_CYCLES",
  90         "SampleAfterValue": "2000000",
  91         "UMask": "0x10"
  92     },
  93     {
  94         "BriefDescription": "ITLB flushes",
  95         "EventCode": "0xAE",
  96         "EventName": "ITLB_FLUSH",
  97         "SampleAfterValue": "2000000",
  98         "UMask": "0x1"
  99     },
 100     {
 101         "BriefDescription": "ITLB miss",
 102         "EventCode": "0x85",
 103         "EventName": "ITLB_MISSES.ANY",
 104         "SampleAfterValue": "200000",
 105         "UMask": "0x1"
 106     },
 107     {
 108         "BriefDescription": "ITLB miss large page walks",
 109         "EventCode": "0x85",
 110         "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED",
 111         "SampleAfterValue": "200000",
 112         "UMask": "0x80"
 113     },
 114     {
 115         "BriefDescription": "ITLB miss page walks",
 116         "EventCode": "0x85",
 117         "EventName": "ITLB_MISSES.WALK_COMPLETED",
 118         "SampleAfterValue": "200000",
 119         "UMask": "0x2"
 120     },
 121     {
 122         "BriefDescription": "ITLB miss page walk cycles",
 123         "EventCode": "0x85",
 124         "EventName": "ITLB_MISSES.WALK_CYCLES",
 125         "SampleAfterValue": "2000000",
 126         "UMask": "0x4"
 127     },
 128     {
 129         "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
 130         "EventCode": "0xC8",
 131         "EventName": "ITLB_MISS_RETIRED",
 132         "PEBS": "1",
 133         "SampleAfterValue": "200000",
 134         "UMask": "0x20"
 135     },
 136     {
 137         "BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
 138         "EventCode": "0xCB",
 139         "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
 140         "PEBS": "1",
 141         "SampleAfterValue": "200000",
 142         "UMask": "0x80"
 143     },
 144     {
 145         "BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
 146         "EventCode": "0xC",
 147         "EventName": "MEM_STORE_RETIRED.DTLB_MISS",
 148         "PEBS": "1",
 149         "SampleAfterValue": "200000",
 150         "UMask": "0x1"
 151     }
 152 ]