tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json

   1 [
   2     {
   3         "BriefDescription": "Cycles the divider is busy",
   4         "EventCode": "0x14",
   5         "EventName": "ARITH.CYCLES_DIV_BUSY",
   6         "SampleAfterValue": "2000000",
   7         "UMask": "0x1"
   8     },
   9     {
  10         "BriefDescription": "Divide Operations executed",
  11         "CounterMask": "1",
  12         "EdgeDetect": "1",
  13         "EventCode": "0x14",
  14         "EventName": "ARITH.DIV",
  15         "Invert": "1",
  16         "SampleAfterValue": "2000000",
  17         "UMask": "0x1"
  18     },
  19     {
  20         "BriefDescription": "Multiply operations executed",
  21         "EventCode": "0x14",
  22         "EventName": "ARITH.MUL",
  23         "SampleAfterValue": "2000000",
  24         "UMask": "0x2"
  25     },
  26     {
  27         "BriefDescription": "BACLEAR asserted with bad target address",
  28         "EventCode": "0xE6",
  29         "EventName": "BACLEAR.BAD_TARGET",
  30         "SampleAfterValue": "2000000",
  31         "UMask": "0x2"
  32     },
  33     {
  34         "BriefDescription": "BACLEAR asserted, regardless of cause",
  35         "EventCode": "0xE6",
  36         "EventName": "BACLEAR.CLEAR",
  37         "SampleAfterValue": "2000000",
  38         "UMask": "0x1"
  39     },
  40     {
  41         "BriefDescription": "Instruction queue forced BACLEAR",
  42         "EventCode": "0xA7",
  43         "EventName": "BACLEAR_FORCE_IQ",
  44         "SampleAfterValue": "2000000",
  45         "UMask": "0x1"
  46     },
  47     {
  48         "BriefDescription": "Early Branch Prediciton Unit clears",
  49         "EventCode": "0xE8",
  50         "EventName": "BPU_CLEARS.EARLY",
  51         "SampleAfterValue": "2000000",
  52         "UMask": "0x1"
  53     },
  54     {
  55         "BriefDescription": "Late Branch Prediction Unit clears",
  56         "EventCode": "0xE8",
  57         "EventName": "BPU_CLEARS.LATE",
  58         "SampleAfterValue": "2000000",
  59         "UMask": "0x2"
  60     },
  61     {
  62         "BriefDescription": "Branch prediction unit missed call or return",
  63         "EventCode": "0xE5",
  64         "EventName": "BPU_MISSED_CALL_RET",
  65         "SampleAfterValue": "2000000",
  66         "UMask": "0x1"
  67     },
  68     {
  69         "BriefDescription": "Branch instructions decoded",
  70         "EventCode": "0xE0",
  71         "EventName": "BR_INST_DECODED",
  72         "SampleAfterValue": "2000000",
  73         "UMask": "0x1"
  74     },
  75     {
  76         "BriefDescription": "Branch instructions executed",
  77         "EventCode": "0x88",
  78         "EventName": "BR_INST_EXEC.ANY",
  79         "SampleAfterValue": "200000",
  80         "UMask": "0x7f"
  81     },
  82     {
  83         "BriefDescription": "Conditional branch instructions executed",
  84         "EventCode": "0x88",
  85         "EventName": "BR_INST_EXEC.COND",
  86         "SampleAfterValue": "200000",
  87         "UMask": "0x1"
  88     },
  89     {
  90         "BriefDescription": "Unconditional branches executed",
  91         "EventCode": "0x88",
  92         "EventName": "BR_INST_EXEC.DIRECT",
  93         "SampleAfterValue": "200000",
  94         "UMask": "0x2"
  95     },
  96     {
  97         "BriefDescription": "Unconditional call branches executed",
  98         "EventCode": "0x88",
  99         "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
 100         "SampleAfterValue": "20000",
 101         "UMask": "0x10"
 102     },
 103     {
 104         "BriefDescription": "Indirect call branches executed",
 105         "EventCode": "0x88",
 106         "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
 107         "SampleAfterValue": "20000",
 108         "UMask": "0x20"
 109     },
 110     {
 111         "BriefDescription": "Indirect non call branches executed",
 112         "EventCode": "0x88",
 113         "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
 114         "SampleAfterValue": "20000",
 115         "UMask": "0x4"
 116     },
 117     {
 118         "BriefDescription": "Call branches executed",
 119         "EventCode": "0x88",
 120         "EventName": "BR_INST_EXEC.NEAR_CALLS",
 121         "SampleAfterValue": "20000",
 122         "UMask": "0x30"
 123     },
 124     {
 125         "BriefDescription": "All non call branches executed",
 126         "EventCode": "0x88",
 127         "EventName": "BR_INST_EXEC.NON_CALLS",
 128         "SampleAfterValue": "200000",
 129         "UMask": "0x7"
 130     },
 131     {
 132         "BriefDescription": "Indirect return branches executed",
 133         "EventCode": "0x88",
 134         "EventName": "BR_INST_EXEC.RETURN_NEAR",
 135         "SampleAfterValue": "20000",
 136         "UMask": "0x8"
 137     },
 138     {
 139         "BriefDescription": "Taken branches executed",
 140         "EventCode": "0x88",
 141         "EventName": "BR_INST_EXEC.TAKEN",
 142         "SampleAfterValue": "200000",
 143         "UMask": "0x40"
 144     },
 145     {
 146         "BriefDescription": "Retired branch instructions (Precise Event)",
 147         "EventCode": "0xC4",
 148         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
 149         "PEBS": "1",
 150         "SampleAfterValue": "200000",
 151         "UMask": "0x4"
 152     },
 153     {
 154         "BriefDescription": "Retired conditional branch instructions (Precise Event)",
 155         "EventCode": "0xC4",
 156         "EventName": "BR_INST_RETIRED.CONDITIONAL",
 157         "PEBS": "1",
 158         "SampleAfterValue": "200000",
 159         "UMask": "0x1"
 160     },
 161     {
 162         "BriefDescription": "Retired near call instructions (Precise Event)",
 163         "EventCode": "0xC4",
 164         "EventName": "BR_INST_RETIRED.NEAR_CALL",
 165         "PEBS": "1",
 166         "SampleAfterValue": "20000",
 167         "UMask": "0x2"
 168     },
 169     {
 170         "BriefDescription": "Mispredicted branches executed",
 171         "EventCode": "0x89",
 172         "EventName": "BR_MISP_EXEC.ANY",
 173         "SampleAfterValue": "20000",
 174         "UMask": "0x7f"
 175     },
 176     {
 177         "BriefDescription": "Mispredicted conditional branches executed",
 178         "EventCode": "0x89",
 179         "EventName": "BR_MISP_EXEC.COND",
 180         "SampleAfterValue": "20000",
 181         "UMask": "0x1"
 182     },
 183     {
 184         "BriefDescription": "Mispredicted unconditional branches executed",
 185         "EventCode": "0x89",
 186         "EventName": "BR_MISP_EXEC.DIRECT",
 187         "SampleAfterValue": "20000",
 188         "UMask": "0x2"
 189     },
 190     {
 191         "BriefDescription": "Mispredicted non call branches executed",
 192         "EventCode": "0x89",
 193         "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
 194         "SampleAfterValue": "2000",
 195         "UMask": "0x10"
 196     },
 197     {
 198         "BriefDescription": "Mispredicted indirect call branches executed",
 199         "EventCode": "0x89",
 200         "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
 201         "SampleAfterValue": "2000",
 202         "UMask": "0x20"
 203     },
 204     {
 205         "BriefDescription": "Mispredicted indirect non call branches executed",
 206         "EventCode": "0x89",
 207         "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
 208         "SampleAfterValue": "2000",
 209         "UMask": "0x4"
 210     },
 211     {
 212         "BriefDescription": "Mispredicted call branches executed",
 213         "EventCode": "0x89",
 214         "EventName": "BR_MISP_EXEC.NEAR_CALLS",
 215         "SampleAfterValue": "2000",
 216         "UMask": "0x30"
 217     },
 218     {
 219         "BriefDescription": "Mispredicted non call branches executed",
 220         "EventCode": "0x89",
 221         "EventName": "BR_MISP_EXEC.NON_CALLS",
 222         "SampleAfterValue": "20000",
 223         "UMask": "0x7"
 224     },
 225     {
 226         "BriefDescription": "Mispredicted return branches executed",
 227         "EventCode": "0x89",
 228         "EventName": "BR_MISP_EXEC.RETURN_NEAR",
 229         "SampleAfterValue": "2000",
 230         "UMask": "0x8"
 231     },
 232     {
 233         "BriefDescription": "Mispredicted taken branches executed",
 234         "EventCode": "0x89",
 235         "EventName": "BR_MISP_EXEC.TAKEN",
 236         "SampleAfterValue": "20000",
 237         "UMask": "0x40"
 238     },
 239     {
 240         "BriefDescription": "Mispredicted retired branch instructions (Precise Event)",
 241         "EventCode": "0xC5",
 242         "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
 243         "PEBS": "1",
 244         "SampleAfterValue": "20000",
 245         "UMask": "0x4"
 246     },
 247     {
 248         "BriefDescription": "Mispredicted conditional retired branches (Precise Event)",
 249         "EventCode": "0xC5",
 250         "EventName": "BR_MISP_RETIRED.CONDITIONAL",
 251         "PEBS": "1",
 252         "SampleAfterValue": "20000",
 253         "UMask": "0x1"
 254     },
 255     {
 256         "BriefDescription": "Mispredicted near retired calls (Precise Event)",
 257         "EventCode": "0xC5",
 258         "EventName": "BR_MISP_RETIRED.NEAR_CALL",
 259         "PEBS": "1",
 260         "SampleAfterValue": "2000",
 261         "UMask": "0x2"
 262     },
 263     {
 264         "BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
 265         "EventName": "CPU_CLK_UNHALTED.REF",
 266         "SampleAfterValue": "2000000"
 267     },
 268     {
 269         "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
 270         "EventCode": "0x3C",
 271         "EventName": "CPU_CLK_UNHALTED.REF_P",
 272         "SampleAfterValue": "100000",
 273         "UMask": "0x1"
 274     },
 275     {
 276         "BriefDescription": "Cycles when thread is not halted (fixed counter)",
 277         "EventName": "CPU_CLK_UNHALTED.THREAD",
 278         "SampleAfterValue": "2000000"
 279     },
 280     {
 281         "BriefDescription": "Cycles when thread is not halted (programmable counter)",
 282         "EventCode": "0x3C",
 283         "EventName": "CPU_CLK_UNHALTED.THREAD_P",
 284         "SampleAfterValue": "2000000"
 285     },
 286     {
 287         "BriefDescription": "Total CPU cycles",
 288         "CounterMask": "2",
 289         "EventCode": "0x3C",
 290         "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
 291         "Invert": "1",
 292         "SampleAfterValue": "2000000"
 293     },
 294     {
 295         "BriefDescription": "Any Instruction Length Decoder stall cycles",
 296         "EventCode": "0x87",
 297         "EventName": "ILD_STALL.ANY",
 298         "SampleAfterValue": "2000000",
 299         "UMask": "0xf"
 300     },
 301     {
 302         "BriefDescription": "Instruction Queue full stall cycles",
 303         "EventCode": "0x87",
 304         "EventName": "ILD_STALL.IQ_FULL",
 305         "SampleAfterValue": "2000000",
 306         "UMask": "0x4"
 307     },
 308     {
 309         "BriefDescription": "Length Change Prefix stall cycles",
 310         "EventCode": "0x87",
 311         "EventName": "ILD_STALL.LCP",
 312         "SampleAfterValue": "2000000",
 313         "UMask": "0x1"
 314     },
 315     {
 316         "BriefDescription": "Stall cycles due to BPU MRU bypass",
 317         "EventCode": "0x87",
 318         "EventName": "ILD_STALL.MRU",
 319         "SampleAfterValue": "2000000",
 320         "UMask": "0x2"
 321     },
 322     {
 323         "BriefDescription": "Regen stall cycles",
 324         "EventCode": "0x87",
 325         "EventName": "ILD_STALL.REGEN",
 326         "SampleAfterValue": "2000000",
 327         "UMask": "0x8"
 328     },
 329     {
 330         "BriefDescription": "Instructions that must be decoded by decoder 0",
 331         "EventCode": "0x18",
 332         "EventName": "INST_DECODED.DEC0",
 333         "SampleAfterValue": "2000000",
 334         "UMask": "0x1"
 335     },
 336     {
 337         "BriefDescription": "Instructions written to instruction queue.",
 338         "EventCode": "0x17",
 339         "EventName": "INST_QUEUE_WRITES",
 340         "SampleAfterValue": "2000000",
 341         "UMask": "0x1"
 342     },
 343     {
 344         "BriefDescription": "Cycles instructions are written to the instruction queue",
 345         "EventCode": "0x1E",
 346         "EventName": "INST_QUEUE_WRITE_CYCLES",
 347         "SampleAfterValue": "2000000",
 348         "UMask": "0x1"
 349     },
 350     {
 351         "BriefDescription": "Instructions retired (fixed counter)",
 352         "EventName": "INST_RETIRED.ANY",
 353         "SampleAfterValue": "2000000"
 354     },
 355     {
 356         "BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
 357         "EventCode": "0xC0",
 358         "EventName": "INST_RETIRED.ANY_P",
 359         "PEBS": "1",
 360         "SampleAfterValue": "2000000",
 361         "UMask": "0x1"
 362     },
 363     {
 364         "BriefDescription": "Retired MMX instructions (Precise Event)",
 365         "EventCode": "0xC0",
 366         "EventName": "INST_RETIRED.MMX",
 367         "PEBS": "1",
 368         "SampleAfterValue": "2000000",
 369         "UMask": "0x4"
 370     },
 371     {
 372         "BriefDescription": "Total cycles (Precise Event)",
 373         "CounterMask": "16",
 374         "EventCode": "0xC0",
 375         "EventName": "INST_RETIRED.TOTAL_CYCLES",
 376         "Invert": "1",
 377         "PEBS": "1",
 378         "SampleAfterValue": "2000000",
 379         "UMask": "0x1"
 380     },
 381     {
 382         "BriefDescription": "Total cycles (Precise Event)",
 383         "CounterMask": "16",
 384         "EventCode": "0xC0",
 385         "EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
 386         "Invert": "1",
 387         "PEBS": "2",
 388         "SampleAfterValue": "2000000",
 389         "UMask": "0x1"
 390     },
 391     {
 392         "BriefDescription": "Retired floating-point operations (Precise Event)",
 393         "EventCode": "0xC0",
 394         "EventName": "INST_RETIRED.X87",
 395         "PEBS": "1",
 396         "SampleAfterValue": "2000000",
 397         "UMask": "0x2"
 398     },
 399     {
 400         "BriefDescription": "Load operations conflicting with software prefetches",
 401         "EventCode": "0x4C",
 402         "EventName": "LOAD_HIT_PRE",
 403         "SampleAfterValue": "200000",
 404         "UMask": "0x1"
 405     },
 406     {
 407         "BriefDescription": "Cycles when uops were delivered by the LSD",
 408         "CounterMask": "1",
 409         "EventCode": "0xA8",
 410         "EventName": "LSD.ACTIVE",
 411         "SampleAfterValue": "2000000",
 412         "UMask": "0x1"
 413     },
 414     {
 415         "BriefDescription": "Cycles no uops were delivered by the LSD",
 416         "CounterMask": "1",
 417         "EventCode": "0xA8",
 418         "EventName": "LSD.INACTIVE",
 419         "Invert": "1",
 420         "SampleAfterValue": "2000000",
 421         "UMask": "0x1"
 422     },
 423     {
 424         "BriefDescription": "Loops that can't stream from the instruction queue",
 425         "EventCode": "0x20",
 426         "EventName": "LSD_OVERFLOW",
 427         "SampleAfterValue": "2000000",
 428         "UMask": "0x1"
 429     },
 430     {
 431         "BriefDescription": "Cycles machine clear asserted",
 432         "EventCode": "0xC3",
 433         "EventName": "MACHINE_CLEARS.CYCLES",
 434         "SampleAfterValue": "20000",
 435         "UMask": "0x1"
 436     },
 437     {
 438         "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
 439         "EventCode": "0xC3",
 440         "EventName": "MACHINE_CLEARS.MEM_ORDER",
 441         "SampleAfterValue": "20000",
 442         "UMask": "0x2"
 443     },
 444     {
 445         "BriefDescription": "Self-Modifying Code detected",
 446         "EventCode": "0xC3",
 447         "EventName": "MACHINE_CLEARS.SMC",
 448         "SampleAfterValue": "20000",
 449         "UMask": "0x4"
 450     },
 451     {
 452         "BriefDescription": "All RAT stall cycles",
 453         "EventCode": "0xD2",
 454         "EventName": "RAT_STALLS.ANY",
 455         "SampleAfterValue": "2000000",
 456         "UMask": "0xf"
 457     },
 458     {
 459         "BriefDescription": "Flag stall cycles",
 460         "EventCode": "0xD2",
 461         "EventName": "RAT_STALLS.FLAGS",
 462         "SampleAfterValue": "2000000",
 463         "UMask": "0x1"
 464     },
 465     {
 466         "BriefDescription": "Partial register stall cycles",
 467         "EventCode": "0xD2",
 468         "EventName": "RAT_STALLS.REGISTERS",
 469         "SampleAfterValue": "2000000",
 470         "UMask": "0x2"
 471     },
 472     {
 473         "BriefDescription": "ROB read port stalls cycles",
 474         "EventCode": "0xD2",
 475         "EventName": "RAT_STALLS.ROB_READ_PORT",
 476         "SampleAfterValue": "2000000",
 477         "UMask": "0x4"
 478     },
 479     {
 480         "BriefDescription": "Scoreboard stall cycles",
 481         "EventCode": "0xD2",
 482         "EventName": "RAT_STALLS.SCOREBOARD",
 483         "SampleAfterValue": "2000000",
 484         "UMask": "0x8"
 485     },
 486     {
 487         "BriefDescription": "Resource related stall cycles",
 488         "EventCode": "0xA2",
 489         "EventName": "RESOURCE_STALLS.ANY",
 490         "SampleAfterValue": "2000000",
 491         "UMask": "0x1"
 492     },
 493     {
 494         "BriefDescription": "FPU control word write stall cycles",
 495         "EventCode": "0xA2",
 496         "EventName": "RESOURCE_STALLS.FPCW",
 497         "SampleAfterValue": "2000000",
 498         "UMask": "0x20"
 499     },
 500     {
 501         "BriefDescription": "Load buffer stall cycles",
 502         "EventCode": "0xA2",
 503         "EventName": "RESOURCE_STALLS.LOAD",
 504         "SampleAfterValue": "2000000",
 505         "UMask": "0x2"
 506     },
 507     {
 508         "BriefDescription": "MXCSR rename stall cycles",
 509         "EventCode": "0xA2",
 510         "EventName": "RESOURCE_STALLS.MXCSR",
 511         "SampleAfterValue": "2000000",
 512         "UMask": "0x40"
 513     },
 514     {
 515         "BriefDescription": "Other Resource related stall cycles",
 516         "EventCode": "0xA2",
 517         "EventName": "RESOURCE_STALLS.OTHER",
 518         "SampleAfterValue": "2000000",
 519         "UMask": "0x80"
 520     },
 521     {
 522         "BriefDescription": "ROB full stall cycles",
 523         "EventCode": "0xA2",
 524         "EventName": "RESOURCE_STALLS.ROB_FULL",
 525         "SampleAfterValue": "2000000",
 526         "UMask": "0x10"
 527     },
 528     {
 529         "BriefDescription": "Reservation Station full stall cycles",
 530         "EventCode": "0xA2",
 531         "EventName": "RESOURCE_STALLS.RS_FULL",
 532         "SampleAfterValue": "2000000",
 533         "UMask": "0x4"
 534     },
 535     {
 536         "BriefDescription": "Store buffer stall cycles",
 537         "EventCode": "0xA2",
 538         "EventName": "RESOURCE_STALLS.STORE",
 539         "SampleAfterValue": "2000000",
 540         "UMask": "0x8"
 541     },
 542     {
 543         "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
 544         "EventCode": "0xC7",
 545         "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
 546         "PEBS": "1",
 547         "SampleAfterValue": "200000",
 548         "UMask": "0x4"
 549     },
 550     {
 551         "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
 552         "EventCode": "0xC7",
 553         "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
 554         "PEBS": "1",
 555         "SampleAfterValue": "200000",
 556         "UMask": "0x1"
 557     },
 558     {
 559         "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
 560         "EventCode": "0xC7",
 561         "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
 562         "PEBS": "1",
 563         "SampleAfterValue": "200000",
 564         "UMask": "0x8"
 565     },
 566     {
 567         "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
 568         "EventCode": "0xC7",
 569         "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
 570         "PEBS": "1",
 571         "SampleAfterValue": "200000",
 572         "UMask": "0x2"
 573     },
 574     {
 575         "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
 576         "EventCode": "0xC7",
 577         "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
 578         "PEBS": "1",
 579         "SampleAfterValue": "200000",
 580         "UMask": "0x10"
 581     },
 582     {
 583         "BriefDescription": "Stack pointer instructions decoded",
 584         "EventCode": "0xD1",
 585         "EventName": "UOPS_DECODED.ESP_FOLDING",
 586         "SampleAfterValue": "2000000",
 587         "UMask": "0x4"
 588     },
 589     {
 590         "BriefDescription": "Stack pointer sync operations",
 591         "EventCode": "0xD1",
 592         "EventName": "UOPS_DECODED.ESP_SYNC",
 593         "SampleAfterValue": "2000000",
 594         "UMask": "0x8"
 595     },
 596     {
 597         "BriefDescription": "Uops decoded by Microcode Sequencer",
 598         "CounterMask": "1",
 599         "EventCode": "0xD1",
 600         "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
 601         "SampleAfterValue": "2000000",
 602         "UMask": "0x2"
 603     },
 604     {
 605         "BriefDescription": "Cycles no Uops are decoded",
 606         "CounterMask": "1",
 607         "EventCode": "0xD1",
 608         "EventName": "UOPS_DECODED.STALL_CYCLES",
 609         "Invert": "1",
 610         "SampleAfterValue": "2000000",
 611         "UMask": "0x1"
 612     },
 613     {
 614         "AnyThread": "1",
 615         "BriefDescription": "Cycles Uops executed on any port (core count)",
 616         "CounterMask": "1",
 617         "EventCode": "0xB1",
 618         "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
 619         "SampleAfterValue": "2000000",
 620         "UMask": "0x3f"
 621     },
 622     {
 623         "AnyThread": "1",
 624         "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
 625         "CounterMask": "1",
 626         "EventCode": "0xB1",
 627         "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
 628         "SampleAfterValue": "2000000",
 629         "UMask": "0x1f"
 630     },
 631     {
 632         "AnyThread": "1",
 633         "BriefDescription": "Uops executed on any port (core count)",
 634         "CounterMask": "1",
 635         "EdgeDetect": "1",
 636         "EventCode": "0xB1",
 637         "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT",
 638         "Invert": "1",
 639         "SampleAfterValue": "2000000",
 640         "UMask": "0x3f"
 641     },
 642     {
 643         "AnyThread": "1",
 644         "BriefDescription": "Uops executed on ports 0-4 (core count)",
 645         "CounterMask": "1",
 646         "EdgeDetect": "1",
 647         "EventCode": "0xB1",
 648         "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5",
 649         "Invert": "1",
 650         "SampleAfterValue": "2000000",
 651         "UMask": "0x1f"
 652     },
 653     {
 654         "AnyThread": "1",
 655         "BriefDescription": "Cycles no Uops issued on any port (core count)",
 656         "CounterMask": "1",
 657         "EventCode": "0xB1",
 658         "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
 659         "Invert": "1",
 660         "SampleAfterValue": "2000000",
 661         "UMask": "0x3f"
 662     },
 663     {
 664         "AnyThread": "1",
 665         "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
 666         "CounterMask": "1",
 667         "EventCode": "0xB1",
 668         "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
 669         "Invert": "1",
 670         "SampleAfterValue": "2000000",
 671         "UMask": "0x1f"
 672     },
 673     {
 674         "BriefDescription": "Uops executed on port 0",
 675         "EventCode": "0xB1",
 676         "EventName": "UOPS_EXECUTED.PORT0",
 677         "SampleAfterValue": "2000000",
 678         "UMask": "0x1"
 679     },
 680     {
 681         "BriefDescription": "Uops issued on ports 0, 1 or 5",
 682         "EventCode": "0xB1",
 683         "EventName": "UOPS_EXECUTED.PORT015",
 684         "SampleAfterValue": "2000000",
 685         "UMask": "0x40"
 686     },
 687     {
 688         "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
 689         "CounterMask": "1",
 690         "EventCode": "0xB1",
 691         "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
 692         "Invert": "1",
 693         "SampleAfterValue": "2000000",
 694         "UMask": "0x40"
 695     },
 696     {
 697         "BriefDescription": "Uops executed on port 1",
 698         "EventCode": "0xB1",
 699         "EventName": "UOPS_EXECUTED.PORT1",
 700         "SampleAfterValue": "2000000",
 701         "UMask": "0x2"
 702     },
 703     {
 704         "AnyThread": "1",
 705         "BriefDescription": "Uops issued on ports 2, 3 or 4",
 706         "EventCode": "0xB1",
 707         "EventName": "UOPS_EXECUTED.PORT234_CORE",
 708         "SampleAfterValue": "2000000",
 709         "UMask": "0x80"
 710     },
 711     {
 712         "AnyThread": "1",
 713         "BriefDescription": "Uops executed on port 2 (core count)",
 714         "EventCode": "0xB1",
 715         "EventName": "UOPS_EXECUTED.PORT2_CORE",
 716         "SampleAfterValue": "2000000",
 717         "UMask": "0x4"
 718     },
 719     {
 720         "AnyThread": "1",
 721         "BriefDescription": "Uops executed on port 3 (core count)",
 722         "EventCode": "0xB1",
 723         "EventName": "UOPS_EXECUTED.PORT3_CORE",
 724         "SampleAfterValue": "2000000",
 725         "UMask": "0x8"
 726     },
 727     {
 728         "AnyThread": "1",
 729         "BriefDescription": "Uops executed on port 4 (core count)",
 730         "EventCode": "0xB1",
 731         "EventName": "UOPS_EXECUTED.PORT4_CORE",
 732         "SampleAfterValue": "2000000",
 733         "UMask": "0x10"
 734     },
 735     {
 736         "BriefDescription": "Uops executed on port 5",
 737         "EventCode": "0xB1",
 738         "EventName": "UOPS_EXECUTED.PORT5",
 739         "SampleAfterValue": "2000000",
 740         "UMask": "0x20"
 741     },
 742     {
 743         "BriefDescription": "Uops issued",
 744         "EventCode": "0xE",
 745         "EventName": "UOPS_ISSUED.ANY",
 746         "SampleAfterValue": "2000000",
 747         "UMask": "0x1"
 748     },
 749     {
 750         "AnyThread": "1",
 751         "BriefDescription": "Cycles no Uops were issued on any thread",
 752         "CounterMask": "1",
 753         "EventCode": "0xE",
 754         "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
 755         "Invert": "1",
 756         "SampleAfterValue": "2000000",
 757         "UMask": "0x1"
 758     },
 759     {
 760         "AnyThread": "1",
 761         "BriefDescription": "Cycles Uops were issued on either thread",
 762         "CounterMask": "1",
 763         "EventCode": "0xE",
 764         "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
 765         "SampleAfterValue": "2000000",
 766         "UMask": "0x1"
 767     },
 768     {
 769         "BriefDescription": "Fused Uops issued",
 770         "EventCode": "0xE",
 771         "EventName": "UOPS_ISSUED.FUSED",
 772         "SampleAfterValue": "2000000",
 773         "UMask": "0x2"
 774     },
 775     {
 776         "BriefDescription": "Cycles no Uops were issued",
 777         "CounterMask": "1",
 778         "EventCode": "0xE",
 779         "EventName": "UOPS_ISSUED.STALL_CYCLES",
 780         "Invert": "1",
 781         "SampleAfterValue": "2000000",
 782         "UMask": "0x1"
 783     },
 784     {
 785         "BriefDescription": "Cycles Uops are being retired",
 786         "CounterMask": "1",
 787         "EventCode": "0xC2",
 788         "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
 789         "PEBS": "1",
 790         "SampleAfterValue": "2000000",
 791         "UMask": "0x1"
 792     },
 793     {
 794         "BriefDescription": "Uops retired (Precise Event)",
 795         "EventCode": "0xC2",
 796         "EventName": "UOPS_RETIRED.ANY",
 797         "PEBS": "1",
 798         "SampleAfterValue": "2000000",
 799         "UMask": "0x1"
 800     },
 801     {
 802         "BriefDescription": "Macro-fused Uops retired (Precise Event)",
 803         "EventCode": "0xC2",
 804         "EventName": "UOPS_RETIRED.MACRO_FUSED",
 805         "PEBS": "1",
 806         "SampleAfterValue": "2000000",
 807         "UMask": "0x4"
 808     },
 809     {
 810         "BriefDescription": "Retirement slots used (Precise Event)",
 811         "EventCode": "0xC2",
 812         "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
 813         "PEBS": "1",
 814         "SampleAfterValue": "2000000",
 815         "UMask": "0x2"
 816     },
 817     {
 818         "BriefDescription": "Cycles Uops are not retiring (Precise Event)",
 819         "CounterMask": "1",
 820         "EventCode": "0xC2",
 821         "EventName": "UOPS_RETIRED.STALL_CYCLES",
 822         "Invert": "1",
 823         "PEBS": "1",
 824         "SampleAfterValue": "2000000",
 825         "UMask": "0x1"
 826     },
 827     {
 828         "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
 829         "CounterMask": "16",
 830         "EventCode": "0xC2",
 831         "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
 832         "Invert": "1",
 833         "PEBS": "1",
 834         "SampleAfterValue": "2000000",
 835         "UMask": "0x1"
 836     },
 837     {
 838         "BriefDescription": "Uop unfusions due to FP exceptions",
 839         "EventCode": "0xDB",
 840         "EventName": "UOP_UNFUSION",
 841         "SampleAfterValue": "2000000",
 842         "UMask": "0x1"
 843     }
 844 ]