tools/perf/pmu-events/arch/x86/snowridgex/memory.json

   1 [
   2     {
   3         "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",
   4         "EventCode": "0xc3",
   5         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
   6         "SampleAfterValue": "20003",
   7         "UMask": "0x2"
   8     },
   9     {
  10         "BriefDescription": "Counts the number of misaligned load uops that are 4K page splits.",
  11         "EventCode": "0x13",
  12         "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",
  13         "PEBS": "1",
  14         "SampleAfterValue": "200003",
  15         "UMask": "0x2"
  16     },
  17     {
  18         "BriefDescription": "Counts the number of misaligned store uops that are 4K page splits.",
  19         "EventCode": "0x13",
  20         "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",
  21         "PEBS": "1",
  22         "SampleAfterValue": "200003",
  23         "UMask": "0x4"
  24     },
  25     {
  26         "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
  27         "EventCode": "0XB7",
  28         "EventName": "OCR.ALL_CODE_RD.L3_MISS",
  29         "MSRIndex": "0x1a6,0x1a7",
  30         "MSRValue": "0x2184000044",
  31         "SampleAfterValue": "100003",
  32         "UMask": "0x1"
  33     },
  34     {
  35         "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
  36         "EventCode": "0XB7",
  37         "EventName": "OCR.ALL_CODE_RD.L3_MISS_LOCAL",
  38         "MSRIndex": "0x1a6,0x1a7",
  39         "MSRValue": "0x2184000044",
  40         "SampleAfterValue": "100003",
  41         "UMask": "0x1"
  42     },
  43     {
  44         "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.",
  45         "EventCode": "0XB7",
  46         "EventName": "OCR.COREWB_M.L3_MISS",
  47         "MSRIndex": "0x1a6,0x1a7",
  48         "MSRValue": "0x3002184000000",
  49         "SampleAfterValue": "100003",
  50         "UMask": "0x1"
  51     },
  52     {
  53         "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.",
  54         "EventCode": "0XB7",
  55         "EventName": "OCR.COREWB_M.L3_MISS_LOCAL",
  56         "MSRIndex": "0x1a6,0x1a7",
  57         "MSRValue": "0x3002184000000",
  58         "SampleAfterValue": "100003",
  59         "UMask": "0x1"
  60     },
  61     {
  62         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",
  63         "EventCode": "0XB7",
  64         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
  65         "MSRIndex": "0x1a6,0x1a7",
  66         "MSRValue": "0x2184000004",
  67         "SampleAfterValue": "100003",
  68         "UMask": "0x1"
  69     },
  70     {
  71         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",
  72         "EventCode": "0XB7",
  73         "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL",
  74         "MSRIndex": "0x1a6,0x1a7",
  75         "MSRValue": "0x2184000004",
  76         "SampleAfterValue": "100003",
  77         "UMask": "0x1"
  78     },
  79     {
  80         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
  81         "EventCode": "0XB7",
  82         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",
  83         "MSRIndex": "0x1a6,0x1a7",
  84         "MSRValue": "0x2184000001",
  85         "SampleAfterValue": "100003",
  86         "UMask": "0x1"
  87     },
  88     {
  89         "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
  90         "EventCode": "0XB7",
  91         "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",
  92         "MSRIndex": "0x1a6,0x1a7",
  93         "MSRValue": "0x2184000001",
  94         "SampleAfterValue": "100003",
  95         "UMask": "0x1"
  96     },
  97     {
  98         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",
  99         "Deprecated": "1",
 100         "EventCode": "0XB7",
 101         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
 102         "MSRIndex": "0x1a6,0x1a7",
 103         "MSRValue": "0x2184000001",
 104         "SampleAfterValue": "100003",
 105         "UMask": "0x1"
 106     },
 107     {
 108         "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",
 109         "Deprecated": "1",
 110         "EventCode": "0XB7",
 111         "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
 112         "MSRIndex": "0x1a6,0x1a7",
 113         "MSRValue": "0x2184000001",
 114         "SampleAfterValue": "100003",
 115         "UMask": "0x1"
 116     },
 117     {
 118         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
 119         "EventCode": "0XB7",
 120         "EventName": "OCR.DEMAND_RFO.L3_MISS",
 121         "MSRIndex": "0x1a6,0x1a7",
 122         "MSRValue": "0x2184000002",
 123         "SampleAfterValue": "100003",
 124         "UMask": "0x1"
 125     },
 126     {
 127         "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
 128         "EventCode": "0XB7",
 129         "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
 130         "MSRIndex": "0x1a6,0x1a7",
 131         "MSRValue": "0x2184000002",
 132         "SampleAfterValue": "100003",
 133         "UMask": "0x1"
 134     },
 135     {
 136         "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.",
 137         "EventCode": "0XB7",
 138         "EventName": "OCR.FULL_STREAMING_WR.L3_MISS",
 139         "MSRIndex": "0x1a6,0x1a7",
 140         "MSRValue": "0x802184000000",
 141         "SampleAfterValue": "100003",
 142         "UMask": "0x1"
 143     },
 144     {
 145         "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.",
 146         "EventCode": "0XB7",
 147         "EventName": "OCR.FULL_STREAMING_WR.L3_MISS_LOCAL",
 148         "MSRIndex": "0x1a6,0x1a7",
 149         "MSRValue": "0x802184000000",
 150         "SampleAfterValue": "100003",
 151         "UMask": "0x1"
 152     },
 153     {
 154         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.",
 155         "EventCode": "0XB7",
 156         "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS",
 157         "MSRIndex": "0x1a6,0x1a7",
 158         "MSRValue": "0x2184000040",
 159         "SampleAfterValue": "100003",
 160         "UMask": "0x1"
 161     },
 162     {
 163         "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.",
 164         "EventCode": "0XB7",
 165         "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS_LOCAL",
 166         "MSRIndex": "0x1a6,0x1a7",
 167         "MSRValue": "0x2184000040",
 168         "SampleAfterValue": "100003",
 169         "UMask": "0x1"
 170     },
 171     {
 172         "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.",
 173         "EventCode": "0XB7",
 174         "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS",
 175         "MSRIndex": "0x1a6,0x1a7",
 176         "MSRValue": "0x2184000010",
 177         "SampleAfterValue": "100003",
 178         "UMask": "0x1"
 179     },
 180     {
 181         "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.",
 182         "EventCode": "0XB7",
 183         "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS_LOCAL",
 184         "MSRIndex": "0x1a6,0x1a7",
 185         "MSRValue": "0x2184000010",
 186         "SampleAfterValue": "100003",
 187         "UMask": "0x1"
 188     },
 189     {
 190         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.",
 191         "EventCode": "0XB7",
 192         "EventName": "OCR.HWPF_L2_RFO.L3_MISS",
 193         "MSRIndex": "0x1a6,0x1a7",
 194         "MSRValue": "0x2184000020",
 195         "SampleAfterValue": "100003",
 196         "UMask": "0x1"
 197     },
 198     {
 199         "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.",
 200         "EventCode": "0XB7",
 201         "EventName": "OCR.HWPF_L2_RFO.L3_MISS_LOCAL",
 202         "MSRIndex": "0x1a6,0x1a7",
 203         "MSRValue": "0x2184000020",
 204         "SampleAfterValue": "100003",
 205         "UMask": "0x1"
 206     },
 207     {
 208         "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.",
 209         "EventCode": "0XB7",
 210         "EventName": "OCR.L1WB_M.L3_MISS",
 211         "MSRIndex": "0x1a6,0x1a7",
 212         "MSRValue": "0x1002184000000",
 213         "SampleAfterValue": "100003",
 214         "UMask": "0x1"
 215     },
 216     {
 217         "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.",
 218         "EventCode": "0XB7",
 219         "EventName": "OCR.L1WB_M.L3_MISS_LOCAL",
 220         "MSRIndex": "0x1a6,0x1a7",
 221         "MSRValue": "0x1002184000000",
 222         "SampleAfterValue": "100003",
 223         "UMask": "0x1"
 224     },
 225     {
 226         "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.",
 227         "EventCode": "0XB7",
 228         "EventName": "OCR.L2WB_M.L3_MISS",
 229         "MSRIndex": "0x1a6,0x1a7",
 230         "MSRValue": "0x2002184000000",
 231         "SampleAfterValue": "100003",
 232         "UMask": "0x1"
 233     },
 234     {
 235         "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.",
 236         "EventCode": "0XB7",
 237         "EventName": "OCR.L2WB_M.L3_MISS_LOCAL",
 238         "MSRIndex": "0x1a6,0x1a7",
 239         "MSRValue": "0x2002184000000",
 240         "SampleAfterValue": "100003",
 241         "UMask": "0x1"
 242     },
 243     {
 244         "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.",
 245         "EventCode": "0XB7",
 246         "EventName": "OCR.OTHER.L3_MISS",
 247         "MSRIndex": "0x1a6,0x1a7",
 248         "MSRValue": "0x2184008000",
 249         "SampleAfterValue": "100003",
 250         "UMask": "0x1"
 251     },
 252     {
 253         "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.",
 254         "EventCode": "0XB7",
 255         "EventName": "OCR.OTHER.L3_MISS_LOCAL",
 256         "MSRIndex": "0x1a6,0x1a7",
 257         "MSRValue": "0x2184008000",
 258         "SampleAfterValue": "100003",
 259         "UMask": "0x1"
 260     },
 261     {
 262         "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.",
 263         "EventCode": "0XB7",
 264         "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS",
 265         "MSRIndex": "0x1a6,0x1a7",
 266         "MSRValue": "0x402184000000",
 267         "SampleAfterValue": "100003",
 268         "UMask": "0x1"
 269     },
 270     {
 271         "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.",
 272         "EventCode": "0XB7",
 273         "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS_LOCAL",
 274         "MSRIndex": "0x1a6,0x1a7",
 275         "MSRValue": "0x402184000000",
 276         "SampleAfterValue": "100003",
 277         "UMask": "0x1"
 278     },
 279     {
 280         "BriefDescription": "Counts all hardware and software prefetches that were not supplied by the L3 cache.",
 281         "EventCode": "0XB7",
 282         "EventName": "OCR.PREFETCHES.L3_MISS",
 283         "MSRIndex": "0x1a6,0x1a7",
 284         "MSRValue": "0x2184000470",
 285         "SampleAfterValue": "100003",
 286         "UMask": "0x1"
 287     },
 288     {
 289         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.",
 290         "EventCode": "0XB7",
 291         "EventName": "OCR.READS_TO_CORE.L3_MISS",
 292         "MSRIndex": "0x1a6,0x1a7",
 293         "MSRValue": "0x2184000477",
 294         "SampleAfterValue": "100003",
 295         "UMask": "0x1"
 296     },
 297     {
 298         "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.",
 299         "EventCode": "0XB7",
 300         "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL",
 301         "MSRIndex": "0x1a6,0x1a7",
 302         "MSRValue": "0x2184000477",
 303         "SampleAfterValue": "100003",
 304         "UMask": "0x1"
 305     },
 306     {
 307         "BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.",
 308         "EventCode": "0XB7",
 309         "EventName": "OCR.STREAMING_WR.L3_MISS",
 310         "MSRIndex": "0x1a6,0x1a7",
 311         "MSRValue": "0x2184000800",
 312         "SampleAfterValue": "100003",
 313         "UMask": "0x1"
 314     },
 315     {
 316         "BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.",
 317         "EventCode": "0XB7",
 318         "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL",
 319         "MSRIndex": "0x1a6,0x1a7",
 320         "MSRValue": "0x2184000800",
 321         "SampleAfterValue": "100003",
 322         "UMask": "0x1"
 323     },
 324     {
 325         "BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.",
 326         "EventCode": "0XB7",
 327         "EventName": "OCR.UC_RD.L3_MISS",
 328         "MSRIndex": "0x1a6,0x1a7",
 329         "MSRValue": "0x102184000000",
 330         "SampleAfterValue": "100003",
 331         "UMask": "0x1"
 332     },
 333     {
 334         "BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.",
 335         "EventCode": "0XB7",
 336         "EventName": "OCR.UC_RD.L3_MISS_LOCAL",
 337         "MSRIndex": "0x1a6,0x1a7",
 338         "MSRValue": "0x102184000000",
 339         "SampleAfterValue": "100003",
 340         "UMask": "0x1"
 341     },
 342     {
 343         "BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.",
 344         "EventCode": "0XB7",
 345         "EventName": "OCR.UC_WR.L3_MISS",
 346         "MSRIndex": "0x1a6,0x1a7",
 347         "MSRValue": "0x202184000000",
 348         "SampleAfterValue": "100003",
 349         "UMask": "0x1"
 350     },
 351     {
 352         "BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.",
 353         "EventCode": "0XB7",
 354         "EventName": "OCR.UC_WR.L3_MISS_LOCAL",
 355         "MSRIndex": "0x1a6,0x1a7",
 356         "MSRValue": "0x202184000000",
 357         "SampleAfterValue": "100003",
 358         "UMask": "0x1"
 359     }
 360 ]