tools/perf/pmu-events/arch/x86/skylakex/other.json

   1 [
   2     {
   3         "EventCode": "0x28",
   4         "UMask": "0x7",
   5         "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
   6         "Counter": "0,1,2,3",
   7         "EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
   8         "PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
   9         "SampleAfterValue": "200003",
  10         "CounterHTOff": "0,1,2,3,4,5,6,7"
  11     },
  12     {
  13         "EventCode": "0x28",
  14         "UMask": "0x18",
  15         "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
  16         "Counter": "0,1,2,3",
  17         "EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
  18         "PublicDescription": "Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
  19         "SampleAfterValue": "200003",
  20         "CounterHTOff": "0,1,2,3,4,5,6,7"
  21     },
  22     {
  23         "EventCode": "0x28",
  24         "UMask": "0x20",
  25         "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
  26         "Counter": "0,1,2,3",
  27         "EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
  28         "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture).  This includes high current AVX 512-bit instructions.",
  29         "SampleAfterValue": "200003",
  30         "CounterHTOff": "0,1,2,3,4,5,6,7"
  31     },
  32     {
  33         "EventCode": "0x28",
  34         "UMask": "0x40",
  35         "BriefDescription": "Core cycles the core was throttled due to a pending power level request.",
  36         "Counter": "0,1,2,3",
  37         "EventName": "CORE_POWER.THROTTLE",
  38         "PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.",
  39         "SampleAfterValue": "200003",
  40         "CounterHTOff": "0,1,2,3,4,5,6,7"
  41     },
  42     {
  43         "EventCode": "0xCB",
  44         "UMask": "0x1",
  45         "BriefDescription": "Number of hardware interrupts received by the processor.",
  46         "Counter": "0,1,2,3",
  47         "EventName": "HW_INTERRUPTS.RECEIVED",
  48         "PublicDescription": "Counts the number of hardware interruptions received by the processor.",
  49         "SampleAfterValue": "203",
  50         "CounterHTOff": "0,1,2,3,4,5,6,7"
  51     },
  52     {
  53         "EventCode": "0xFE",
  54         "UMask": "0x2",
  55         "BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly",
  56         "Counter": "0,1,2,3",
  57         "EventName": "IDI_MISC.WB_UPGRADE",
  58         "PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.",
  59         "SampleAfterValue": "100003",
  60         "CounterHTOff": "0,1,2,3,4,5,6,7"
  61     },
  62     {
  63         "EventCode": "0xFE",
  64         "UMask": "0x4",
  65         "BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly",
  66         "Counter": "0,1,2,3",
  67         "EventName": "IDI_MISC.WB_DOWNGRADE",
  68         "PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.",
  69         "SampleAfterValue": "100003",
  70         "CounterHTOff": "0,1,2,3,4,5,6,7"
  71     }
  72 ]