tools/perf/pmu-events/arch/x86/skylake/memory.json

   1 [
   2     {
   3         "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
   4         "CounterMask": "2",
   5         "EventCode": "0xA3",
   6         "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
   7         "SampleAfterValue": "2000003",
   8         "UMask": "0x2"
   9     },
  10     {
  11         "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
  12         "CounterMask": "6",
  13         "EventCode": "0xA3",
  14         "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
  15         "SampleAfterValue": "2000003",
  16         "UMask": "0x6"
  17     },
  18     {
  19         "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
  20         "EventCode": "0xC8",
  21         "EventName": "HLE_RETIRED.ABORTED",
  22         "PEBS": "1",
  23         "PublicDescription": "Number of times HLE abort was triggered.",
  24         "SampleAfterValue": "2000003",
  25         "UMask": "0x4"
  26     },
  27     {
  28         "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
  29         "EventCode": "0xC8",
  30         "EventName": "HLE_RETIRED.ABORTED_EVENTS",
  31         "SampleAfterValue": "2000003",
  32         "UMask": "0x80"
  33     },
  34     {
  35         "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
  36         "EventCode": "0xC8",
  37         "EventName": "HLE_RETIRED.ABORTED_MEM",
  38         "SampleAfterValue": "2000003",
  39         "UMask": "0x8"
  40     },
  41     {
  42         "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
  43         "EventCode": "0xC8",
  44         "EventName": "HLE_RETIRED.ABORTED_MEMTYPE",
  45         "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.",
  46         "SampleAfterValue": "2000003",
  47         "UMask": "0x40"
  48     },
  49     {
  50         "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.",
  51         "EventCode": "0xC8",
  52         "EventName": "HLE_RETIRED.ABORTED_TIMER",
  53         "SampleAfterValue": "2000003",
  54         "UMask": "0x10"
  55     },
  56     {
  57         "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
  58         "EventCode": "0xC8",
  59         "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",
  60         "SampleAfterValue": "2000003",
  61         "UMask": "0x20"
  62     },
  63     {
  64         "BriefDescription": "Number of times an HLE execution successfully committed",
  65         "EventCode": "0xC8",
  66         "EventName": "HLE_RETIRED.COMMIT",
  67         "PublicDescription": "Number of times HLE commit succeeded.",
  68         "SampleAfterValue": "2000003",
  69         "UMask": "0x2"
  70     },
  71     {
  72         "BriefDescription": "Number of times an HLE execution started.",
  73         "EventCode": "0xC8",
  74         "EventName": "HLE_RETIRED.START",
  75         "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.",
  76         "SampleAfterValue": "2000003",
  77         "UMask": "0x1"
  78     },
  79     {
  80         "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
  81         "Errata": "SKL089",
  82         "EventCode": "0xC3",
  83         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
  84         "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.",
  85         "SampleAfterValue": "100003",
  86         "UMask": "0x2"
  87     },
  88     {
  89         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
  90         "Data_LA": "1",
  91         "EventCode": "0xcd",
  92         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
  93         "MSRIndex": "0x3F6",
  94         "MSRValue": "0x80",
  95         "PEBS": "2",
  96         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",
  97         "SampleAfterValue": "1009",
  98         "UMask": "0x1"
  99     },
 100     {
 101         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
 102         "Data_LA": "1",
 103         "EventCode": "0xcd",
 104         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
 105         "MSRIndex": "0x3F6",
 106         "MSRValue": "0x10",
 107         "PEBS": "2",
 108         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",
 109         "SampleAfterValue": "20011",
 110         "UMask": "0x1"
 111     },
 112     {
 113         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
 114         "Data_LA": "1",
 115         "EventCode": "0xcd",
 116         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
 117         "MSRIndex": "0x3F6",
 118         "MSRValue": "0x100",
 119         "PEBS": "2",
 120         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",
 121         "SampleAfterValue": "503",
 122         "UMask": "0x1"
 123     },
 124     {
 125         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
 126         "Data_LA": "1",
 127         "EventCode": "0xcd",
 128         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
 129         "MSRIndex": "0x3F6",
 130         "MSRValue": "0x20",
 131         "PEBS": "2",
 132         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",
 133         "SampleAfterValue": "100007",
 134         "UMask": "0x1"
 135     },
 136     {
 137         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
 138         "Data_LA": "1",
 139         "EventCode": "0xcd",
 140         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
 141         "MSRIndex": "0x3F6",
 142         "MSRValue": "0x4",
 143         "PEBS": "2",
 144         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",
 145         "SampleAfterValue": "100003",
 146         "UMask": "0x1"
 147     },
 148     {
 149         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
 150         "Data_LA": "1",
 151         "EventCode": "0xcd",
 152         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
 153         "MSRIndex": "0x3F6",
 154         "MSRValue": "0x200",
 155         "PEBS": "2",
 156         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",
 157         "SampleAfterValue": "101",
 158         "UMask": "0x1"
 159     },
 160     {
 161         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
 162         "Data_LA": "1",
 163         "EventCode": "0xcd",
 164         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
 165         "MSRIndex": "0x3F6",
 166         "MSRValue": "0x40",
 167         "PEBS": "2",
 168         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",
 169         "SampleAfterValue": "2003",
 170         "UMask": "0x1"
 171     },
 172     {
 173         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
 174         "Data_LA": "1",
 175         "EventCode": "0xcd",
 176         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
 177         "MSRIndex": "0x3F6",
 178         "MSRValue": "0x8",
 179         "PEBS": "2",
 180         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",
 181         "SampleAfterValue": "50021",
 182         "UMask": "0x1"
 183     },
 184     {
 185         "BriefDescription": "Demand Data Read requests who miss L3 cache",
 186         "EventCode": "0xB0",
 187         "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
 188         "PublicDescription": "Demand Data Read requests who miss L3 cache.",
 189         "SampleAfterValue": "100003",
 190         "UMask": "0x10"
 191     },
 192     {
 193         "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.",
 194         "CounterMask": "1",
 195         "EventCode": "0x60",
 196         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
 197         "SampleAfterValue": "2000003",
 198         "UMask": "0x10"
 199     },
 200     {
 201         "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.",
 202         "EventCode": "0x60",
 203         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
 204         "SampleAfterValue": "2000003",
 205         "UMask": "0x10"
 206     },
 207     {
 208         "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.",
 209         "CounterMask": "6",
 210         "EventCode": "0x60",
 211         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
 212         "SampleAfterValue": "2000003",
 213         "UMask": "0x10"
 214     },
 215     {
 216         "BriefDescription": "Counts all demand code reads",
 217         "EventCode": "0xB7, 0xBB",
 218         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRAM",
 219         "MSRIndex": "0x1a6,0x1a7",
 220         "MSRValue": "0x20001C0004",
 221         "SampleAfterValue": "100003",
 222         "UMask": "0x1"
 223     },
 224     {
 225         "BriefDescription": "Counts all demand code reads",
 226         "EventCode": "0xB7, 0xBB",
 227         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NON_DRAM",
 228         "MSRIndex": "0x1a6,0x1a7",
 229         "MSRValue": "0x2000080004",
 230         "SampleAfterValue": "100003",
 231         "UMask": "0x1"
 232     },
 233     {
 234         "BriefDescription": "Counts all demand code reads",
 235         "EventCode": "0xB7, 0xBB",
 236         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NON_DRAM",
 237         "MSRIndex": "0x1a6,0x1a7",
 238         "MSRValue": "0x2000040004",
 239         "SampleAfterValue": "100003",
 240         "UMask": "0x1"
 241     },
 242     {
 243         "BriefDescription": "Counts all demand code reads",
 244         "EventCode": "0xB7, 0xBB",
 245         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NON_DRAM",
 246         "MSRIndex": "0x1a6,0x1a7",
 247         "MSRValue": "0x2000100004",
 248         "SampleAfterValue": "100003",
 249         "UMask": "0x1"
 250     },
 251     {
 252         "BriefDescription": "Counts all demand code reads",
 253         "EventCode": "0xB7, 0xBB",
 254         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",
 255         "MSRIndex": "0x1a6,0x1a7",
 256         "MSRValue": "0x3FFC400004",
 257         "SampleAfterValue": "100003",
 258         "UMask": "0x1"
 259     },
 260     {
 261         "BriefDescription": "Counts all demand code reads",
 262         "EventCode": "0xB7, 0xBB",
 263         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HITM",
 264         "MSRIndex": "0x1a6,0x1a7",
 265         "MSRValue": "0x103C400004",
 266         "SampleAfterValue": "100003",
 267         "UMask": "0x1"
 268     },
 269     {
 270         "BriefDescription": "Counts all demand code reads",
 271         "EventCode": "0xB7, 0xBB",
 272         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD",
 273         "MSRIndex": "0x1a6,0x1a7",
 274         "MSRValue": "0x43C400004",
 275         "SampleAfterValue": "100003",
 276         "UMask": "0x1"
 277     },
 278     {
 279         "BriefDescription": "Counts all demand code reads",
 280         "EventCode": "0xB7, 0xBB",
 281         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS",
 282         "MSRIndex": "0x1a6,0x1a7",
 283         "MSRValue": "0x23C400004",
 284         "SampleAfterValue": "100003",
 285         "UMask": "0x1"
 286     },
 287     {
 288         "BriefDescription": "Counts all demand code reads",
 289         "EventCode": "0xB7, 0xBB",
 290         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE",
 291         "MSRIndex": "0x1a6,0x1a7",
 292         "MSRValue": "0xBC400004",
 293         "SampleAfterValue": "100003",
 294         "UMask": "0x1"
 295     },
 296     {
 297         "BriefDescription": "Counts all demand code reads",
 298         "EventCode": "0xB7, 0xBB",
 299         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NON_DRAM",
 300         "MSRIndex": "0x1a6,0x1a7",
 301         "MSRValue": "0x203C400004",
 302         "SampleAfterValue": "100003",
 303         "UMask": "0x1"
 304     },
 305     {
 306         "BriefDescription": "Counts all demand code reads",
 307         "EventCode": "0xB7, 0xBB",
 308         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED",
 309         "MSRIndex": "0x1a6,0x1a7",
 310         "MSRValue": "0x13C400004",
 311         "SampleAfterValue": "100003",
 312         "UMask": "0x1"
 313     },
 314     {
 315         "BriefDescription": "Counts all demand code reads",
 316         "EventCode": "0xB7, 0xBB",
 317         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SPL_HIT",
 318         "MSRIndex": "0x1a6,0x1a7",
 319         "MSRValue": "0x7C400004",
 320         "SampleAfterValue": "100003",
 321         "UMask": "0x1"
 322     },
 323     {
 324         "BriefDescription": "Counts all demand code reads",
 325         "EventCode": "0xB7, 0xBB",
 326         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
 327         "MSRIndex": "0x1a6,0x1a7",
 328         "MSRValue": "0x3FC4000004",
 329         "SampleAfterValue": "100003",
 330         "UMask": "0x1"
 331     },
 332     {
 333         "BriefDescription": "Counts all demand code reads",
 334         "EventCode": "0xB7, 0xBB",
 335         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
 336         "MSRIndex": "0x1a6,0x1a7",
 337         "MSRValue": "0x1004000004",
 338         "SampleAfterValue": "100003",
 339         "UMask": "0x1"
 340     },
 341     {
 342         "BriefDescription": "Counts all demand code reads",
 343         "EventCode": "0xB7, 0xBB",
 344         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
 345         "MSRIndex": "0x1a6,0x1a7",
 346         "MSRValue": "0x404000004",
 347         "SampleAfterValue": "100003",
 348         "UMask": "0x1"
 349     },
 350     {
 351         "BriefDescription": "Counts all demand code reads",
 352         "EventCode": "0xB7, 0xBB",
 353         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
 354         "MSRIndex": "0x1a6,0x1a7",
 355         "MSRValue": "0x204000004",
 356         "SampleAfterValue": "100003",
 357         "UMask": "0x1"
 358     },
 359     {
 360         "BriefDescription": "Counts all demand code reads",
 361         "EventCode": "0xB7, 0xBB",
 362         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
 363         "MSRIndex": "0x1a6,0x1a7",
 364         "MSRValue": "0x84000004",
 365         "SampleAfterValue": "100003",
 366         "UMask": "0x1"
 367     },
 368     {
 369         "BriefDescription": "Counts all demand code reads",
 370         "EventCode": "0xB7, 0xBB",
 371         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
 372         "MSRIndex": "0x1a6,0x1a7",
 373         "MSRValue": "0x2004000004",
 374         "SampleAfterValue": "100003",
 375         "UMask": "0x1"
 376     },
 377     {
 378         "BriefDescription": "Counts all demand code reads",
 379         "EventCode": "0xB7, 0xBB",
 380         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
 381         "MSRIndex": "0x1a6,0x1a7",
 382         "MSRValue": "0x104000004",
 383         "SampleAfterValue": "100003",
 384         "UMask": "0x1"
 385     },
 386     {
 387         "BriefDescription": "Counts all demand code reads",
 388         "EventCode": "0xB7, 0xBB",
 389         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SPL_HIT",
 390         "MSRIndex": "0x1a6,0x1a7",
 391         "MSRValue": "0x44000004",
 392         "SampleAfterValue": "100003",
 393         "UMask": "0x1"
 394     },
 395     {
 396         "BriefDescription": "Counts all demand code reads",
 397         "EventCode": "0xB7, 0xBB",
 398         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
 399         "MSRIndex": "0x1a6,0x1a7",
 400         "MSRValue": "0x2000400004",
 401         "SampleAfterValue": "100003",
 402         "UMask": "0x1"
 403     },
 404     {
 405         "BriefDescription": "Counts all demand code reads",
 406         "EventCode": "0xB7, 0xBB",
 407         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
 408         "MSRIndex": "0x1a6,0x1a7",
 409         "MSRValue": "0x2000020004",
 410         "SampleAfterValue": "100003",
 411         "UMask": "0x1"
 412     },
 413     {
 414         "BriefDescription": "Counts demand data reads",
 415         "EventCode": "0xB7, 0xBB",
 416         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRAM",
 417         "MSRIndex": "0x1a6,0x1a7",
 418         "MSRValue": "0x20001C0001",
 419         "SampleAfterValue": "100003",
 420         "UMask": "0x1"
 421     },
 422     {
 423         "BriefDescription": "Counts demand data reads",
 424         "EventCode": "0xB7, 0xBB",
 425         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NON_DRAM",
 426         "MSRIndex": "0x1a6,0x1a7",
 427         "MSRValue": "0x2000080001",
 428         "SampleAfterValue": "100003",
 429         "UMask": "0x1"
 430     },
 431     {
 432         "BriefDescription": "Counts demand data reads",
 433         "EventCode": "0xB7, 0xBB",
 434         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NON_DRAM",
 435         "MSRIndex": "0x1a6,0x1a7",
 436         "MSRValue": "0x2000040001",
 437         "SampleAfterValue": "100003",
 438         "UMask": "0x1"
 439     },
 440     {
 441         "BriefDescription": "Counts demand data reads",
 442         "EventCode": "0xB7, 0xBB",
 443         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NON_DRAM",
 444         "MSRIndex": "0x1a6,0x1a7",
 445         "MSRValue": "0x2000100001",
 446         "SampleAfterValue": "100003",
 447         "UMask": "0x1"
 448     },
 449     {
 450         "BriefDescription": "Counts demand data reads",
 451         "EventCode": "0xB7, 0xBB",
 452         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
 453         "MSRIndex": "0x1a6,0x1a7",
 454         "MSRValue": "0x3FFC400001",
 455         "SampleAfterValue": "100003",
 456         "UMask": "0x1"
 457     },
 458     {
 459         "BriefDescription": "Counts demand data reads",
 460         "EventCode": "0xB7, 0xBB",
 461         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HITM",
 462         "MSRIndex": "0x1a6,0x1a7",
 463         "MSRValue": "0x103C400001",
 464         "SampleAfterValue": "100003",
 465         "UMask": "0x1"
 466     },
 467     {
 468         "BriefDescription": "Counts demand data reads",
 469         "EventCode": "0xB7, 0xBB",
 470         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",
 471         "MSRIndex": "0x1a6,0x1a7",
 472         "MSRValue": "0x43C400001",
 473         "SampleAfterValue": "100003",
 474         "UMask": "0x1"
 475     },
 476     {
 477         "BriefDescription": "Counts demand data reads",
 478         "EventCode": "0xB7, 0xBB",
 479         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS",
 480         "MSRIndex": "0x1a6,0x1a7",
 481         "MSRValue": "0x23C400001",
 482         "SampleAfterValue": "100003",
 483         "UMask": "0x1"
 484     },
 485     {
 486         "BriefDescription": "Counts demand data reads",
 487         "EventCode": "0xB7, 0xBB",
 488         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE",
 489         "MSRIndex": "0x1a6,0x1a7",
 490         "MSRValue": "0xBC400001",
 491         "SampleAfterValue": "100003",
 492         "UMask": "0x1"
 493     },
 494     {
 495         "BriefDescription": "Counts demand data reads",
 496         "EventCode": "0xB7, 0xBB",
 497         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NON_DRAM",
 498         "MSRIndex": "0x1a6,0x1a7",
 499         "MSRValue": "0x203C400001",
 500         "SampleAfterValue": "100003",
 501         "UMask": "0x1"
 502     },
 503     {
 504         "BriefDescription": "Counts demand data reads",
 505         "EventCode": "0xB7, 0xBB",
 506         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",
 507         "MSRIndex": "0x1a6,0x1a7",
 508         "MSRValue": "0x13C400001",
 509         "SampleAfterValue": "100003",
 510         "UMask": "0x1"
 511     },
 512     {
 513         "BriefDescription": "Counts demand data reads",
 514         "EventCode": "0xB7, 0xBB",
 515         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SPL_HIT",
 516         "MSRIndex": "0x1a6,0x1a7",
 517         "MSRValue": "0x7C400001",
 518         "SampleAfterValue": "100003",
 519         "UMask": "0x1"
 520     },
 521     {
 522         "BriefDescription": "Counts demand data reads",
 523         "EventCode": "0xB7, 0xBB",
 524         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
 525         "MSRIndex": "0x1a6,0x1a7",
 526         "MSRValue": "0x3FC4000001",
 527         "SampleAfterValue": "100003",
 528         "UMask": "0x1"
 529     },
 530     {
 531         "BriefDescription": "Counts demand data reads",
 532         "EventCode": "0xB7, 0xBB",
 533         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
 534         "MSRIndex": "0x1a6,0x1a7",
 535         "MSRValue": "0x1004000001",
 536         "SampleAfterValue": "100003",
 537         "UMask": "0x1"
 538     },
 539     {
 540         "BriefDescription": "Counts demand data reads",
 541         "EventCode": "0xB7, 0xBB",
 542         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
 543         "MSRIndex": "0x1a6,0x1a7",
 544         "MSRValue": "0x404000001",
 545         "SampleAfterValue": "100003",
 546         "UMask": "0x1"
 547     },
 548     {
 549         "BriefDescription": "Counts demand data reads",
 550         "EventCode": "0xB7, 0xBB",
 551         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
 552         "MSRIndex": "0x1a6,0x1a7",
 553         "MSRValue": "0x204000001",
 554         "SampleAfterValue": "100003",
 555         "UMask": "0x1"
 556     },
 557     {
 558         "BriefDescription": "Counts demand data reads",
 559         "EventCode": "0xB7, 0xBB",
 560         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
 561         "MSRIndex": "0x1a6,0x1a7",
 562         "MSRValue": "0x84000001",
 563         "SampleAfterValue": "100003",
 564         "UMask": "0x1"
 565     },
 566     {
 567         "BriefDescription": "Counts demand data reads",
 568         "EventCode": "0xB7, 0xBB",
 569         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
 570         "MSRIndex": "0x1a6,0x1a7",
 571         "MSRValue": "0x2004000001",
 572         "SampleAfterValue": "100003",
 573         "UMask": "0x1"
 574     },
 575     {
 576         "BriefDescription": "Counts demand data reads",
 577         "EventCode": "0xB7, 0xBB",
 578         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
 579         "MSRIndex": "0x1a6,0x1a7",
 580         "MSRValue": "0x104000001",
 581         "SampleAfterValue": "100003",
 582         "UMask": "0x1"
 583     },
 584     {
 585         "BriefDescription": "Counts demand data reads",
 586         "EventCode": "0xB7, 0xBB",
 587         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SPL_HIT",
 588         "MSRIndex": "0x1a6,0x1a7",
 589         "MSRValue": "0x44000001",
 590         "SampleAfterValue": "100003",
 591         "UMask": "0x1"
 592     },
 593     {
 594         "BriefDescription": "Counts demand data reads",
 595         "EventCode": "0xB7, 0xBB",
 596         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
 597         "MSRIndex": "0x1a6,0x1a7",
 598         "MSRValue": "0x2000400001",
 599         "SampleAfterValue": "100003",
 600         "UMask": "0x1"
 601     },
 602     {
 603         "BriefDescription": "Counts demand data reads",
 604         "EventCode": "0xB7, 0xBB",
 605         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
 606         "MSRIndex": "0x1a6,0x1a7",
 607         "MSRValue": "0x2000020001",
 608         "SampleAfterValue": "100003",
 609         "UMask": "0x1"
 610     },
 611     {
 612         "BriefDescription": "Counts all demand data writes (RFOs)",
 613         "EventCode": "0xB7, 0xBB",
 614         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM",
 615         "MSRIndex": "0x1a6,0x1a7",
 616         "MSRValue": "0x20001C0002",
 617         "SampleAfterValue": "100003",
 618         "UMask": "0x1"
 619     },
 620     {
 621         "BriefDescription": "Counts all demand data writes (RFOs)",
 622         "EventCode": "0xB7, 0xBB",
 623         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NON_DRAM",
 624         "MSRIndex": "0x1a6,0x1a7",
 625         "MSRValue": "0x2000080002",
 626         "SampleAfterValue": "100003",
 627         "UMask": "0x1"
 628     },
 629     {
 630         "BriefDescription": "Counts all demand data writes (RFOs)",
 631         "EventCode": "0xB7, 0xBB",
 632         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NON_DRAM",
 633         "MSRIndex": "0x1a6,0x1a7",
 634         "MSRValue": "0x2000040002",
 635         "SampleAfterValue": "100003",
 636         "UMask": "0x1"
 637     },
 638     {
 639         "BriefDescription": "Counts all demand data writes (RFOs)",
 640         "EventCode": "0xB7, 0xBB",
 641         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NON_DRAM",
 642         "MSRIndex": "0x1a6,0x1a7",
 643         "MSRValue": "0x2000100002",
 644         "SampleAfterValue": "100003",
 645         "UMask": "0x1"
 646     },
 647     {
 648         "BriefDescription": "Counts all demand data writes (RFOs)",
 649         "EventCode": "0xB7, 0xBB",
 650         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP",
 651         "MSRIndex": "0x1a6,0x1a7",
 652         "MSRValue": "0x3FFC400002",
 653         "SampleAfterValue": "100003",
 654         "UMask": "0x1"
 655     },
 656     {
 657         "BriefDescription": "Counts all demand data writes (RFOs)",
 658         "EventCode": "0xB7, 0xBB",
 659         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HITM",
 660         "MSRIndex": "0x1a6,0x1a7",
 661         "MSRValue": "0x103C400002",
 662         "SampleAfterValue": "100003",
 663         "UMask": "0x1"
 664     },
 665     {
 666         "BriefDescription": "Counts all demand data writes (RFOs)",
 667         "EventCode": "0xB7, 0xBB",
 668         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD",
 669         "MSRIndex": "0x1a6,0x1a7",
 670         "MSRValue": "0x43C400002",
 671         "SampleAfterValue": "100003",
 672         "UMask": "0x1"
 673     },
 674     {
 675         "BriefDescription": "Counts all demand data writes (RFOs)",
 676         "EventCode": "0xB7, 0xBB",
 677         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS",
 678         "MSRIndex": "0x1a6,0x1a7",
 679         "MSRValue": "0x23C400002",
 680         "SampleAfterValue": "100003",
 681         "UMask": "0x1"
 682     },
 683     {
 684         "BriefDescription": "Counts all demand data writes (RFOs)",
 685         "EventCode": "0xB7, 0xBB",
 686         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE",
 687         "MSRIndex": "0x1a6,0x1a7",
 688         "MSRValue": "0xBC400002",
 689         "SampleAfterValue": "100003",
 690         "UMask": "0x1"
 691     },
 692     {
 693         "BriefDescription": "Counts all demand data writes (RFOs)",
 694         "EventCode": "0xB7, 0xBB",
 695         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NON_DRAM",
 696         "MSRIndex": "0x1a6,0x1a7",
 697         "MSRValue": "0x203C400002",
 698         "SampleAfterValue": "100003",
 699         "UMask": "0x1"
 700     },
 701     {
 702         "BriefDescription": "Counts all demand data writes (RFOs)",
 703         "EventCode": "0xB7, 0xBB",
 704         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED",
 705         "MSRIndex": "0x1a6,0x1a7",
 706         "MSRValue": "0x13C400002",
 707         "SampleAfterValue": "100003",
 708         "UMask": "0x1"
 709     },
 710     {
 711         "BriefDescription": "Counts all demand data writes (RFOs)",
 712         "EventCode": "0xB7, 0xBB",
 713         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SPL_HIT",
 714         "MSRIndex": "0x1a6,0x1a7",
 715         "MSRValue": "0x7C400002",
 716         "SampleAfterValue": "100003",
 717         "UMask": "0x1"
 718     },
 719     {
 720         "BriefDescription": "Counts all demand data writes (RFOs)",
 721         "EventCode": "0xB7, 0xBB",
 722         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
 723         "MSRIndex": "0x1a6,0x1a7",
 724         "MSRValue": "0x3FC4000002",
 725         "SampleAfterValue": "100003",
 726         "UMask": "0x1"
 727     },
 728     {
 729         "BriefDescription": "Counts all demand data writes (RFOs)",
 730         "EventCode": "0xB7, 0xBB",
 731         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
 732         "MSRIndex": "0x1a6,0x1a7",
 733         "MSRValue": "0x1004000002",
 734         "SampleAfterValue": "100003",
 735         "UMask": "0x1"
 736     },
 737     {
 738         "BriefDescription": "Counts all demand data writes (RFOs)",
 739         "EventCode": "0xB7, 0xBB",
 740         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
 741         "MSRIndex": "0x1a6,0x1a7",
 742         "MSRValue": "0x404000002",
 743         "SampleAfterValue": "100003",
 744         "UMask": "0x1"
 745     },
 746     {
 747         "BriefDescription": "Counts all demand data writes (RFOs)",
 748         "EventCode": "0xB7, 0xBB",
 749         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
 750         "MSRIndex": "0x1a6,0x1a7",
 751         "MSRValue": "0x204000002",
 752         "SampleAfterValue": "100003",
 753         "UMask": "0x1"
 754     },
 755     {
 756         "BriefDescription": "Counts all demand data writes (RFOs)",
 757         "EventCode": "0xB7, 0xBB",
 758         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
 759         "MSRIndex": "0x1a6,0x1a7",
 760         "MSRValue": "0x84000002",
 761         "SampleAfterValue": "100003",
 762         "UMask": "0x1"
 763     },
 764     {
 765         "BriefDescription": "Counts all demand data writes (RFOs)",
 766         "EventCode": "0xB7, 0xBB",
 767         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
 768         "MSRIndex": "0x1a6,0x1a7",
 769         "MSRValue": "0x2004000002",
 770         "SampleAfterValue": "100003",
 771         "UMask": "0x1"
 772     },
 773     {
 774         "BriefDescription": "Counts all demand data writes (RFOs)",
 775         "EventCode": "0xB7, 0xBB",
 776         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
 777         "MSRIndex": "0x1a6,0x1a7",
 778         "MSRValue": "0x104000002",
 779         "SampleAfterValue": "100003",
 780         "UMask": "0x1"
 781     },
 782     {
 783         "BriefDescription": "Counts all demand data writes (RFOs)",
 784         "EventCode": "0xB7, 0xBB",
 785         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SPL_HIT",
 786         "MSRIndex": "0x1a6,0x1a7",
 787         "MSRValue": "0x44000002",
 788         "SampleAfterValue": "100003",
 789         "UMask": "0x1"
 790     },
 791     {
 792         "BriefDescription": "Counts all demand data writes (RFOs)",
 793         "EventCode": "0xB7, 0xBB",
 794         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
 795         "MSRIndex": "0x1a6,0x1a7",
 796         "MSRValue": "0x2000400002",
 797         "SampleAfterValue": "100003",
 798         "UMask": "0x1"
 799     },
 800     {
 801         "BriefDescription": "Counts all demand data writes (RFOs)",
 802         "EventCode": "0xB7, 0xBB",
 803         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM",
 804         "MSRIndex": "0x1a6,0x1a7",
 805         "MSRValue": "0x2000020002",
 806         "SampleAfterValue": "100003",
 807         "UMask": "0x1"
 808     },
 809     {
 810         "BriefDescription": "Counts any other requests",
 811         "EventCode": "0xB7, 0xBB",
 812         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM",
 813         "MSRIndex": "0x1a6,0x1a7",
 814         "MSRValue": "0x20001C8000",
 815         "SampleAfterValue": "100003",
 816         "UMask": "0x1"
 817     },
 818     {
 819         "BriefDescription": "Counts any other requests",
 820         "EventCode": "0xB7, 0xBB",
 821         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NON_DRAM",
 822         "MSRIndex": "0x1a6,0x1a7",
 823         "MSRValue": "0x2000088000",
 824         "SampleAfterValue": "100003",
 825         "UMask": "0x1"
 826     },
 827     {
 828         "BriefDescription": "Counts any other requests",
 829         "EventCode": "0xB7, 0xBB",
 830         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NON_DRAM",
 831         "MSRIndex": "0x1a6,0x1a7",
 832         "MSRValue": "0x2000048000",
 833         "SampleAfterValue": "100003",
 834         "UMask": "0x1"
 835     },
 836     {
 837         "BriefDescription": "Counts any other requests",
 838         "EventCode": "0xB7, 0xBB",
 839         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NON_DRAM",
 840         "MSRIndex": "0x1a6,0x1a7",
 841         "MSRValue": "0x2000108000",
 842         "SampleAfterValue": "100003",
 843         "UMask": "0x1"
 844     },
 845     {
 846         "BriefDescription": "Counts any other requests",
 847         "EventCode": "0xB7, 0xBB",
 848         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP",
 849         "MSRIndex": "0x1a6,0x1a7",
 850         "MSRValue": "0x3FFC408000",
 851         "SampleAfterValue": "100003",
 852         "UMask": "0x1"
 853     },
 854     {
 855         "BriefDescription": "Counts any other requests",
 856         "EventCode": "0xB7, 0xBB",
 857         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HITM",
 858         "MSRIndex": "0x1a6,0x1a7",
 859         "MSRValue": "0x103C408000",
 860         "SampleAfterValue": "100003",
 861         "UMask": "0x1"
 862     },
 863     {
 864         "BriefDescription": "Counts any other requests",
 865         "EventCode": "0xB7, 0xBB",
 866         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD",
 867         "MSRIndex": "0x1a6,0x1a7",
 868         "MSRValue": "0x43C408000",
 869         "SampleAfterValue": "100003",
 870         "UMask": "0x1"
 871     },
 872     {
 873         "BriefDescription": "Counts any other requests",
 874         "EventCode": "0xB7, 0xBB",
 875         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS",
 876         "MSRIndex": "0x1a6,0x1a7",
 877         "MSRValue": "0x23C408000",
 878         "SampleAfterValue": "100003",
 879         "UMask": "0x1"
 880     },
 881     {
 882         "BriefDescription": "Counts any other requests",
 883         "EventCode": "0xB7, 0xBB",
 884         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE",
 885         "MSRIndex": "0x1a6,0x1a7",
 886         "MSRValue": "0xBC408000",
 887         "SampleAfterValue": "100003",
 888         "UMask": "0x1"
 889     },
 890     {
 891         "BriefDescription": "Counts any other requests",
 892         "EventCode": "0xB7, 0xBB",
 893         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NON_DRAM",
 894         "MSRIndex": "0x1a6,0x1a7",
 895         "MSRValue": "0x203C408000",
 896         "SampleAfterValue": "100003",
 897         "UMask": "0x1"
 898     },
 899     {
 900         "BriefDescription": "Counts any other requests",
 901         "EventCode": "0xB7, 0xBB",
 902         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED",
 903         "MSRIndex": "0x1a6,0x1a7",
 904         "MSRValue": "0x13C408000",
 905         "SampleAfterValue": "100003",
 906         "UMask": "0x1"
 907     },
 908     {
 909         "BriefDescription": "Counts any other requests",
 910         "EventCode": "0xB7, 0xBB",
 911         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SPL_HIT",
 912         "MSRIndex": "0x1a6,0x1a7",
 913         "MSRValue": "0x7C408000",
 914         "SampleAfterValue": "100003",
 915         "UMask": "0x1"
 916     },
 917     {
 918         "BriefDescription": "Counts any other requests",
 919         "EventCode": "0xB7, 0xBB",
 920         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
 921         "MSRIndex": "0x1a6,0x1a7",
 922         "MSRValue": "0x3FC4008000",
 923         "SampleAfterValue": "100003",
 924         "UMask": "0x1"
 925     },
 926     {
 927         "BriefDescription": "Counts any other requests",
 928         "EventCode": "0xB7, 0xBB",
 929         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
 930         "MSRIndex": "0x1a6,0x1a7",
 931         "MSRValue": "0x1004008000",
 932         "SampleAfterValue": "100003",
 933         "UMask": "0x1"
 934     },
 935     {
 936         "BriefDescription": "Counts any other requests",
 937         "EventCode": "0xB7, 0xBB",
 938         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
 939         "MSRIndex": "0x1a6,0x1a7",
 940         "MSRValue": "0x404008000",
 941         "SampleAfterValue": "100003",
 942         "UMask": "0x1"
 943     },
 944     {
 945         "BriefDescription": "Counts any other requests",
 946         "EventCode": "0xB7, 0xBB",
 947         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
 948         "MSRIndex": "0x1a6,0x1a7",
 949         "MSRValue": "0x204008000",
 950         "SampleAfterValue": "100003",
 951         "UMask": "0x1"
 952     },
 953     {
 954         "BriefDescription": "Counts any other requests",
 955         "EventCode": "0xB7, 0xBB",
 956         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
 957         "MSRIndex": "0x1a6,0x1a7",
 958         "MSRValue": "0x84008000",
 959         "SampleAfterValue": "100003",
 960         "UMask": "0x1"
 961     },
 962     {
 963         "BriefDescription": "Counts any other requests",
 964         "EventCode": "0xB7, 0xBB",
 965         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
 966         "MSRIndex": "0x1a6,0x1a7",
 967         "MSRValue": "0x2004008000",
 968         "SampleAfterValue": "100003",
 969         "UMask": "0x1"
 970     },
 971     {
 972         "BriefDescription": "Counts any other requests",
 973         "EventCode": "0xB7, 0xBB",
 974         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
 975         "MSRIndex": "0x1a6,0x1a7",
 976         "MSRValue": "0x104008000",
 977         "SampleAfterValue": "100003",
 978         "UMask": "0x1"
 979     },
 980     {
 981         "BriefDescription": "Counts any other requests",
 982         "EventCode": "0xB7, 0xBB",
 983         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SPL_HIT",
 984         "MSRIndex": "0x1a6,0x1a7",
 985         "MSRValue": "0x44008000",
 986         "SampleAfterValue": "100003",
 987         "UMask": "0x1"
 988     },
 989     {
 990         "BriefDescription": "Counts any other requests",
 991         "EventCode": "0xB7, 0xBB",
 992         "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
 993         "MSRIndex": "0x1a6,0x1a7",
 994         "MSRValue": "0x2000408000",
 995         "SampleAfterValue": "100003",
 996         "UMask": "0x1"
 997     },
 998     {
 999         "BriefDescription": "Counts any other requests",
1000         "EventCode": "0xB7, 0xBB",
1001         "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM",
1002         "MSRIndex": "0x1a6,0x1a7",
1003         "MSRValue": "0x2000028000",
1004         "SampleAfterValue": "100003",
1005         "UMask": "0x1"
1006     },
1007     {
1008         "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).",
1009         "EventCode": "0xC9",
1010         "EventName": "RTM_RETIRED.ABORTED",
1011         "PEBS": "1",
1012         "PublicDescription": "Number of times RTM abort was triggered.",
1013         "SampleAfterValue": "2000003",
1014         "UMask": "0x4"
1015     },
1016     {
1017         "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
1018         "EventCode": "0xC9",
1019         "EventName": "RTM_RETIRED.ABORTED_EVENTS",
1020         "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
1021         "SampleAfterValue": "2000003",
1022         "UMask": "0x80"
1023     },
1024     {
1025         "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
1026         "EventCode": "0xC9",
1027         "EventName": "RTM_RETIRED.ABORTED_MEM",
1028         "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
1029         "SampleAfterValue": "2000003",
1030         "UMask": "0x8"
1031     },
1032     {
1033         "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
1034         "EventCode": "0xC9",
1035         "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
1036         "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.",
1037         "SampleAfterValue": "2000003",
1038         "UMask": "0x40"
1039     },
1040     {
1041         "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.",
1042         "EventCode": "0xC9",
1043         "EventName": "RTM_RETIRED.ABORTED_TIMER",
1044         "SampleAfterValue": "2000003",
1045         "UMask": "0x10"
1046     },
1047     {
1048         "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
1049         "EventCode": "0xC9",
1050         "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
1051         "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.",
1052         "SampleAfterValue": "2000003",
1053         "UMask": "0x20"
1054     },
1055     {
1056         "BriefDescription": "Number of times an RTM execution successfully committed",
1057         "EventCode": "0xC9",
1058         "EventName": "RTM_RETIRED.COMMIT",
1059         "PublicDescription": "Number of times RTM commit succeeded.",
1060         "SampleAfterValue": "2000003",
1061         "UMask": "0x2"
1062     },
1063     {
1064         "BriefDescription": "Number of times an RTM execution started.",
1065         "EventCode": "0xC9",
1066         "EventName": "RTM_RETIRED.START",
1067         "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.",
1068         "SampleAfterValue": "2000003",
1069         "UMask": "0x1"
1070     },
1071     {
1072         "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
1073         "EventCode": "0x5d",
1074         "EventName": "TX_EXEC.MISC1",
1075         "SampleAfterValue": "2000003",
1076         "UMask": "0x1"
1077     },
1078     {
1079         "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
1080         "EventCode": "0x5d",
1081         "EventName": "TX_EXEC.MISC2",
1082         "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
1083         "SampleAfterValue": "2000003",
1084         "UMask": "0x2"
1085     },
1086     {
1087         "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
1088         "EventCode": "0x5d",
1089         "EventName": "TX_EXEC.MISC3",
1090         "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
1091         "SampleAfterValue": "2000003",
1092         "UMask": "0x4"
1093     },
1094     {
1095         "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
1096         "EventCode": "0x5d",
1097         "EventName": "TX_EXEC.MISC4",
1098         "PublicDescription": "RTM region detected inside HLE.",
1099         "SampleAfterValue": "2000003",
1100         "UMask": "0x8"
1101     },
1102     {
1103         "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region",
1104         "EventCode": "0x5d",
1105         "EventName": "TX_EXEC.MISC5",
1106         "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
1107         "SampleAfterValue": "2000003",
1108         "UMask": "0x10"
1109     },
1110     {
1111         "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.",
1112         "EventCode": "0x54",
1113         "EventName": "TX_MEM.ABORT_CAPACITY",
1114         "SampleAfterValue": "2000003",
1115         "UMask": "0x2"
1116     },
1117     {
1118         "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
1119         "EventCode": "0x54",
1120         "EventName": "TX_MEM.ABORT_CONFLICT",
1121         "PublicDescription": "Number of times a TSX line had a cache conflict.",
1122         "SampleAfterValue": "2000003",
1123         "UMask": "0x1"
1124     },
1125     {
1126         "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
1127         "EventCode": "0x54",
1128         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
1129         "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
1130         "SampleAfterValue": "2000003",
1131         "UMask": "0x10"
1132     },
1133     {
1134         "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
1135         "EventCode": "0x54",
1136         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
1137         "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
1138         "SampleAfterValue": "2000003",
1139         "UMask": "0x8"
1140     },
1141     {
1142         "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
1143         "EventCode": "0x54",
1144         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
1145         "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
1146         "SampleAfterValue": "2000003",
1147         "UMask": "0x20"
1148     },
1149     {
1150         "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
1151         "EventCode": "0x54",
1152         "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
1153         "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
1154         "SampleAfterValue": "2000003",
1155         "UMask": "0x4"
1156     },
1157     {
1158         "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
1159         "EventCode": "0x54",
1160         "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
1161         "PublicDescription": "Number of times we could not allocate Lock Buffer.",
1162         "SampleAfterValue": "2000003",
1163         "UMask": "0x40"
1164     }
1165 ]