tools/perf/pmu-events/arch/x86/rocketlake/other.json

   1 [
   2     {
   3         "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
   4         "EventCode": "0x28",
   5         "EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
   6         "PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
   7         "SampleAfterValue": "200003",
   8         "UMask": "0x7"
   9     },
  10     {
  11         "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
  12         "EventCode": "0x28",
  13         "EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
  14         "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
  15         "SampleAfterValue": "200003",
  16         "UMask": "0x18"
  17     },
  18     {
  19         "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
  20         "EventCode": "0x28",
  21         "EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
  22         "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture).  This includes high current AVX 512-bit instructions.",
  23         "SampleAfterValue": "200003",
  24         "UMask": "0x20"
  25     },
  26     {
  27         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.",
  28         "EventCode": "0xB7, 0xBB",
  29         "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
  30         "MSRIndex": "0x1a6,0x1a7",
  31         "MSRValue": "0x10004",
  32         "SampleAfterValue": "100003",
  33         "UMask": "0x1"
  34     },
  35     {
  36         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.",
  37         "EventCode": "0xB7, 0xBB",
  38         "EventName": "OCR.DEMAND_CODE_RD.DRAM",
  39         "MSRIndex": "0x1a6,0x1a7",
  40         "MSRValue": "0x184000004",
  41         "SampleAfterValue": "100003",
  42         "UMask": "0x1"
  43     },
  44     {
  45         "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.",
  46         "EventCode": "0xB7, 0xBB",
  47         "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
  48         "MSRIndex": "0x1a6,0x1a7",
  49         "MSRValue": "0x184000004",
  50         "SampleAfterValue": "100003",
  51         "UMask": "0x1"
  52     },
  53     {
  54         "BriefDescription": "Counts demand data reads that have any type of response.",
  55         "EventCode": "0xB7, 0xBB",
  56         "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
  57         "MSRIndex": "0x1a6,0x1a7",
  58         "MSRValue": "0x10001",
  59         "SampleAfterValue": "100003",
  60         "UMask": "0x1"
  61     },
  62     {
  63         "BriefDescription": "Counts demand data reads that DRAM supplied the request.",
  64         "EventCode": "0xB7, 0xBB",
  65         "EventName": "OCR.DEMAND_DATA_RD.DRAM",
  66         "MSRIndex": "0x1a6,0x1a7",
  67         "MSRValue": "0x184000001",
  68         "SampleAfterValue": "100003",
  69         "UMask": "0x1"
  70     },
  71     {
  72         "BriefDescription": "Counts demand data reads that DRAM supplied the request.",
  73         "EventCode": "0xB7, 0xBB",
  74         "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
  75         "MSRIndex": "0x1a6,0x1a7",
  76         "MSRValue": "0x184000001",
  77         "SampleAfterValue": "100003",
  78         "UMask": "0x1"
  79     },
  80     {
  81         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
  82         "EventCode": "0xB7, 0xBB",
  83         "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
  84         "MSRIndex": "0x1a6,0x1a7",
  85         "MSRValue": "0x10002",
  86         "SampleAfterValue": "100003",
  87         "UMask": "0x1"
  88     },
  89     {
  90         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.",
  91         "EventCode": "0xB7, 0xBB",
  92         "EventName": "OCR.DEMAND_RFO.DRAM",
  93         "MSRIndex": "0x1a6,0x1a7",
  94         "MSRValue": "0x184000002",
  95         "SampleAfterValue": "100003",
  96         "UMask": "0x1"
  97     },
  98     {
  99         "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.",
 100         "EventCode": "0xB7, 0xBB",
 101         "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
 102         "MSRIndex": "0x1a6,0x1a7",
 103         "MSRValue": "0x184000002",
 104         "SampleAfterValue": "100003",
 105         "UMask": "0x1"
 106     },
 107     {
 108         "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.",
 109         "EventCode": "0xB7, 0xBB",
 110         "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE",
 111         "MSRIndex": "0x1a6,0x1a7",
 112         "MSRValue": "0x10400",
 113         "SampleAfterValue": "100003",
 114         "UMask": "0x1"
 115     },
 116     {
 117         "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.",
 118         "EventCode": "0xB7, 0xBB",
 119         "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM",
 120         "MSRIndex": "0x1a6,0x1a7",
 121         "MSRValue": "0x184000400",
 122         "SampleAfterValue": "100003",
 123         "UMask": "0x1"
 124     },
 125     {
 126         "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.",
 127         "EventCode": "0xB7, 0xBB",
 128         "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM",
 129         "MSRIndex": "0x1a6,0x1a7",
 130         "MSRValue": "0x184000400",
 131         "SampleAfterValue": "100003",
 132         "UMask": "0x1"
 133     },
 134     {
 135         "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2)  that have any type of response.",
 136         "EventCode": "0xB7, 0xBB",
 137         "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE",
 138         "MSRIndex": "0x1a6,0x1a7",
 139         "MSRValue": "0x10010",
 140         "SampleAfterValue": "100003",
 141         "UMask": "0x1"
 142     },
 143     {
 144         "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2)  that DRAM supplied the request.",
 145         "EventCode": "0xB7, 0xBB",
 146         "EventName": "OCR.HWPF_L2_DATA_RD.DRAM",
 147         "MSRIndex": "0x1a6,0x1a7",
 148         "MSRValue": "0x184000010",
 149         "SampleAfterValue": "100003",
 150         "UMask": "0x1"
 151     },
 152     {
 153         "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2)  that DRAM supplied the request.",
 154         "EventCode": "0xB7, 0xBB",
 155         "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM",
 156         "MSRIndex": "0x1a6,0x1a7",
 157         "MSRValue": "0x184000010",
 158         "SampleAfterValue": "100003",
 159         "UMask": "0x1"
 160     },
 161     {
 162         "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that have any type of response.",
 163         "EventCode": "0xB7, 0xBB",
 164         "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE",
 165         "MSRIndex": "0x1a6,0x1a7",
 166         "MSRValue": "0x10020",
 167         "SampleAfterValue": "100003",
 168         "UMask": "0x1"
 169     },
 170     {
 171         "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.",
 172         "EventCode": "0xB7, 0xBB",
 173         "EventName": "OCR.HWPF_L2_RFO.DRAM",
 174         "MSRIndex": "0x1a6,0x1a7",
 175         "MSRValue": "0x184000020",
 176         "SampleAfterValue": "100003",
 177         "UMask": "0x1"
 178     },
 179     {
 180         "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.",
 181         "EventCode": "0xB7, 0xBB",
 182         "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM",
 183         "MSRIndex": "0x1a6,0x1a7",
 184         "MSRValue": "0x184000020",
 185         "SampleAfterValue": "100003",
 186         "UMask": "0x1"
 187     },
 188     {
 189         "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.",
 190         "EventCode": "0xB7, 0xBB",
 191         "EventName": "OCR.OTHER.ANY_RESPONSE",
 192         "MSRIndex": "0x1a6,0x1a7",
 193         "MSRValue": "0x18000",
 194         "SampleAfterValue": "100003",
 195         "UMask": "0x1"
 196     },
 197     {
 198         "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.",
 199         "EventCode": "0xB7, 0xBB",
 200         "EventName": "OCR.OTHER.DRAM",
 201         "MSRIndex": "0x1a6,0x1a7",
 202         "MSRValue": "0x184008000",
 203         "SampleAfterValue": "100003",
 204         "UMask": "0x1"
 205     },
 206     {
 207         "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.",
 208         "EventCode": "0xB7, 0xBB",
 209         "EventName": "OCR.OTHER.LOCAL_DRAM",
 210         "MSRIndex": "0x1a6,0x1a7",
 211         "MSRValue": "0x184008000",
 212         "SampleAfterValue": "100003",
 213         "UMask": "0x1"
 214     },
 215     {
 216         "BriefDescription": "Counts streaming stores that have any type of response.",
 217         "EventCode": "0xB7, 0xBB",
 218         "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
 219         "MSRIndex": "0x1a6,0x1a7",
 220         "MSRValue": "0x10800",
 221         "SampleAfterValue": "100003",
 222         "UMask": "0x1"
 223     },
 224     {
 225         "BriefDescription": "Counts streaming stores that DRAM supplied the request.",
 226         "EventCode": "0xB7, 0xBB",
 227         "EventName": "OCR.STREAMING_WR.DRAM",
 228         "MSRIndex": "0x1a6,0x1a7",
 229         "MSRValue": "0x184000800",
 230         "SampleAfterValue": "100003",
 231         "UMask": "0x1"
 232     },
 233     {
 234         "BriefDescription": "Counts streaming stores that DRAM supplied the request.",
 235         "EventCode": "0xB7, 0xBB",
 236         "EventName": "OCR.STREAMING_WR.LOCAL_DRAM",
 237         "MSRIndex": "0x1a6,0x1a7",
 238         "MSRValue": "0x184000800",
 239         "SampleAfterValue": "100003",
 240         "UMask": "0x1"
 241     }
 242 ]