tools/perf/pmu-events/arch/x86/nehalemex/pipeline.json

   1 [
   2     {
   3         "EventCode": "0x14",
   4         "Counter": "0,1,2,3",
   5         "UMask": "0x1",
   6         "EventName": "ARITH.CYCLES_DIV_BUSY",
   7         "SampleAfterValue": "2000000",
   8         "BriefDescription": "Cycles the divider is busy"
   9     },
  10     {
  11         "EventCode": "0x14",
  12         "Invert": "1",
  13         "Counter": "0,1,2,3",
  14         "UMask": "0x1",
  15         "EventName": "ARITH.DIV",
  16         "SampleAfterValue": "2000000",
  17         "BriefDescription": "Divide Operations executed",
  18         "CounterMask": "1",
  19         "EdgeDetect": "1"
  20     },
  21     {
  22         "EventCode": "0x14",
  23         "Counter": "0,1,2,3",
  24         "UMask": "0x2",
  25         "EventName": "ARITH.MUL",
  26         "SampleAfterValue": "2000000",
  27         "BriefDescription": "Multiply operations executed"
  28     },
  29     {
  30         "EventCode": "0xE6",
  31         "Counter": "0,1,2,3",
  32         "UMask": "0x2",
  33         "EventName": "BACLEAR.BAD_TARGET",
  34         "SampleAfterValue": "2000000",
  35         "BriefDescription": "BACLEAR asserted with bad target address"
  36     },
  37     {
  38         "EventCode": "0xE6",
  39         "Counter": "0,1,2,3",
  40         "UMask": "0x1",
  41         "EventName": "BACLEAR.CLEAR",
  42         "SampleAfterValue": "2000000",
  43         "BriefDescription": "BACLEAR asserted, regardless of cause "
  44     },
  45     {
  46         "EventCode": "0xA7",
  47         "Counter": "0,1,2,3",
  48         "UMask": "0x1",
  49         "EventName": "BACLEAR_FORCE_IQ",
  50         "SampleAfterValue": "2000000",
  51         "BriefDescription": "Instruction queue forced BACLEAR"
  52     },
  53     {
  54         "EventCode": "0xE0",
  55         "Counter": "0,1,2,3",
  56         "UMask": "0x1",
  57         "EventName": "BR_INST_DECODED",
  58         "SampleAfterValue": "2000000",
  59         "BriefDescription": "Branch instructions decoded"
  60     },
  61     {
  62         "EventCode": "0x88",
  63         "Counter": "0,1,2,3",
  64         "UMask": "0x7f",
  65         "EventName": "BR_INST_EXEC.ANY",
  66         "SampleAfterValue": "200000",
  67         "BriefDescription": "Branch instructions executed"
  68     },
  69     {
  70         "EventCode": "0x88",
  71         "Counter": "0,1,2,3",
  72         "UMask": "0x1",
  73         "EventName": "BR_INST_EXEC.COND",
  74         "SampleAfterValue": "200000",
  75         "BriefDescription": "Conditional branch instructions executed"
  76     },
  77     {
  78         "EventCode": "0x88",
  79         "Counter": "0,1,2,3",
  80         "UMask": "0x2",
  81         "EventName": "BR_INST_EXEC.DIRECT",
  82         "SampleAfterValue": "200000",
  83         "BriefDescription": "Unconditional branches executed"
  84     },
  85     {
  86         "EventCode": "0x88",
  87         "Counter": "0,1,2,3",
  88         "UMask": "0x10",
  89         "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
  90         "SampleAfterValue": "20000",
  91         "BriefDescription": "Unconditional call branches executed"
  92     },
  93     {
  94         "EventCode": "0x88",
  95         "Counter": "0,1,2,3",
  96         "UMask": "0x20",
  97         "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
  98         "SampleAfterValue": "20000",
  99         "BriefDescription": "Indirect call branches executed"
 100     },
 101     {
 102         "EventCode": "0x88",
 103         "Counter": "0,1,2,3",
 104         "UMask": "0x4",
 105         "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
 106         "SampleAfterValue": "20000",
 107         "BriefDescription": "Indirect non call branches executed"
 108     },
 109     {
 110         "EventCode": "0x88",
 111         "Counter": "0,1,2,3",
 112         "UMask": "0x30",
 113         "EventName": "BR_INST_EXEC.NEAR_CALLS",
 114         "SampleAfterValue": "20000",
 115         "BriefDescription": "Call branches executed"
 116     },
 117     {
 118         "EventCode": "0x88",
 119         "Counter": "0,1,2,3",
 120         "UMask": "0x7",
 121         "EventName": "BR_INST_EXEC.NON_CALLS",
 122         "SampleAfterValue": "200000",
 123         "BriefDescription": "All non call branches executed"
 124     },
 125     {
 126         "EventCode": "0x88",
 127         "Counter": "0,1,2,3",
 128         "UMask": "0x8",
 129         "EventName": "BR_INST_EXEC.RETURN_NEAR",
 130         "SampleAfterValue": "20000",
 131         "BriefDescription": "Indirect return branches executed"
 132     },
 133     {
 134         "EventCode": "0x88",
 135         "Counter": "0,1,2,3",
 136         "UMask": "0x40",
 137         "EventName": "BR_INST_EXEC.TAKEN",
 138         "SampleAfterValue": "200000",
 139         "BriefDescription": "Taken branches executed"
 140     },
 141     {
 142         "PEBS": "1",
 143         "EventCode": "0xC4",
 144         "Counter": "0,1,2,3",
 145         "UMask": "0x4",
 146         "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
 147         "SampleAfterValue": "200000",
 148         "BriefDescription": "Retired branch instructions (Precise Event)"
 149     },
 150     {
 151         "PEBS": "1",
 152         "EventCode": "0xC4",
 153         "Counter": "0,1,2,3",
 154         "UMask": "0x1",
 155         "EventName": "BR_INST_RETIRED.CONDITIONAL",
 156         "SampleAfterValue": "200000",
 157         "BriefDescription": "Retired conditional branch instructions (Precise Event)"
 158     },
 159     {
 160         "PEBS": "1",
 161         "EventCode": "0xC4",
 162         "Counter": "0,1,2,3",
 163         "UMask": "0x2",
 164         "EventName": "BR_INST_RETIRED.NEAR_CALL",
 165         "SampleAfterValue": "20000",
 166         "BriefDescription": "Retired near call instructions (Precise Event)"
 167     },
 168     {
 169         "EventCode": "0x89",
 170         "Counter": "0,1,2,3",
 171         "UMask": "0x7f",
 172         "EventName": "BR_MISP_EXEC.ANY",
 173         "SampleAfterValue": "20000",
 174         "BriefDescription": "Mispredicted branches executed"
 175     },
 176     {
 177         "EventCode": "0x89",
 178         "Counter": "0,1,2,3",
 179         "UMask": "0x1",
 180         "EventName": "BR_MISP_EXEC.COND",
 181         "SampleAfterValue": "20000",
 182         "BriefDescription": "Mispredicted conditional branches executed"
 183     },
 184     {
 185         "EventCode": "0x89",
 186         "Counter": "0,1,2,3",
 187         "UMask": "0x2",
 188         "EventName": "BR_MISP_EXEC.DIRECT",
 189         "SampleAfterValue": "20000",
 190         "BriefDescription": "Mispredicted unconditional branches executed"
 191     },
 192     {
 193         "EventCode": "0x89",
 194         "Counter": "0,1,2,3",
 195         "UMask": "0x10",
 196         "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
 197         "SampleAfterValue": "2000",
 198         "BriefDescription": "Mispredicted non call branches executed"
 199     },
 200     {
 201         "EventCode": "0x89",
 202         "Counter": "0,1,2,3",
 203         "UMask": "0x20",
 204         "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
 205         "SampleAfterValue": "2000",
 206         "BriefDescription": "Mispredicted indirect call branches executed"
 207     },
 208     {
 209         "EventCode": "0x89",
 210         "Counter": "0,1,2,3",
 211         "UMask": "0x4",
 212         "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
 213         "SampleAfterValue": "2000",
 214         "BriefDescription": "Mispredicted indirect non call branches executed"
 215     },
 216     {
 217         "EventCode": "0x89",
 218         "Counter": "0,1,2,3",
 219         "UMask": "0x30",
 220         "EventName": "BR_MISP_EXEC.NEAR_CALLS",
 221         "SampleAfterValue": "2000",
 222         "BriefDescription": "Mispredicted call branches executed"
 223     },
 224     {
 225         "EventCode": "0x89",
 226         "Counter": "0,1,2,3",
 227         "UMask": "0x7",
 228         "EventName": "BR_MISP_EXEC.NON_CALLS",
 229         "SampleAfterValue": "20000",
 230         "BriefDescription": "Mispredicted non call branches executed"
 231     },
 232     {
 233         "EventCode": "0x89",
 234         "Counter": "0,1,2,3",
 235         "UMask": "0x8",
 236         "EventName": "BR_MISP_EXEC.RETURN_NEAR",
 237         "SampleAfterValue": "2000",
 238         "BriefDescription": "Mispredicted return branches executed"
 239     },
 240     {
 241         "EventCode": "0x89",
 242         "Counter": "0,1,2,3",
 243         "UMask": "0x40",
 244         "EventName": "BR_MISP_EXEC.TAKEN",
 245         "SampleAfterValue": "20000",
 246         "BriefDescription": "Mispredicted taken branches executed"
 247     },
 248     {
 249         "PEBS": "1",
 250         "EventCode": "0xC5",
 251         "Counter": "0,1,2,3",
 252         "UMask": "0x2",
 253         "EventName": "BR_MISP_RETIRED.NEAR_CALL",
 254         "SampleAfterValue": "2000",
 255         "BriefDescription": "Mispredicted near retired calls (Precise Event)"
 256     },
 257     {
 258         "EventCode": "0x0",
 259         "Counter": "Fixed counter 3",
 260         "UMask": "0x0",
 261         "EventName": "CPU_CLK_UNHALTED.REF",
 262         "SampleAfterValue": "2000000",
 263         "BriefDescription": "Reference cycles when thread is not halted (fixed counter)"
 264     },
 265     {
 266         "EventCode": "0x3C",
 267         "Counter": "0,1,2,3",
 268         "UMask": "0x1",
 269         "EventName": "CPU_CLK_UNHALTED.REF_P",
 270         "SampleAfterValue": "100000",
 271         "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)"
 272     },
 273     {
 274         "EventCode": "0x0",
 275         "Counter": "Fixed counter 2",
 276         "UMask": "0x0",
 277         "EventName": "CPU_CLK_UNHALTED.THREAD",
 278         "SampleAfterValue": "2000000",
 279         "BriefDescription": "Cycles when thread is not halted (fixed counter)"
 280     },
 281     {
 282         "EventCode": "0x3C",
 283         "Counter": "0,1,2,3",
 284         "UMask": "0x0",
 285         "EventName": "CPU_CLK_UNHALTED.THREAD_P",
 286         "SampleAfterValue": "2000000",
 287         "BriefDescription": "Cycles when thread is not halted (programmable counter)"
 288     },
 289     {
 290         "EventCode": "0x3C",
 291         "Invert": "1",
 292         "Counter": "0,1,2,3",
 293         "UMask": "0x0",
 294         "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
 295         "SampleAfterValue": "2000000",
 296         "BriefDescription": "Total CPU cycles",
 297         "CounterMask": "2"
 298     },
 299     {
 300         "EventCode": "0x87",
 301         "Counter": "0,1,2,3",
 302         "UMask": "0xf",
 303         "EventName": "ILD_STALL.ANY",
 304         "SampleAfterValue": "2000000",
 305         "BriefDescription": "Any Instruction Length Decoder stall cycles"
 306     },
 307     {
 308         "EventCode": "0x87",
 309         "Counter": "0,1,2,3",
 310         "UMask": "0x4",
 311         "EventName": "ILD_STALL.IQ_FULL",
 312         "SampleAfterValue": "2000000",
 313         "BriefDescription": "Instruction Queue full stall cycles"
 314     },
 315     {
 316         "EventCode": "0x87",
 317         "Counter": "0,1,2,3",
 318         "UMask": "0x1",
 319         "EventName": "ILD_STALL.LCP",
 320         "SampleAfterValue": "2000000",
 321         "BriefDescription": "Length Change Prefix stall cycles"
 322     },
 323     {
 324         "EventCode": "0x87",
 325         "Counter": "0,1,2,3",
 326         "UMask": "0x2",
 327         "EventName": "ILD_STALL.MRU",
 328         "SampleAfterValue": "2000000",
 329         "BriefDescription": "Stall cycles due to BPU MRU bypass"
 330     },
 331     {
 332         "EventCode": "0x87",
 333         "Counter": "0,1,2,3",
 334         "UMask": "0x8",
 335         "EventName": "ILD_STALL.REGEN",
 336         "SampleAfterValue": "2000000",
 337         "BriefDescription": "Regen stall cycles"
 338     },
 339     {
 340         "EventCode": "0x18",
 341         "Counter": "0,1,2,3",
 342         "UMask": "0x1",
 343         "EventName": "INST_DECODED.DEC0",
 344         "SampleAfterValue": "2000000",
 345         "BriefDescription": "Instructions that must be decoded by decoder 0"
 346     },
 347     {
 348         "EventCode": "0x1E",
 349         "Counter": "0,1,2,3",
 350         "UMask": "0x1",
 351         "EventName": "INST_QUEUE_WRITE_CYCLES",
 352         "SampleAfterValue": "2000000",
 353         "BriefDescription": "Cycles instructions are written to the instruction queue"
 354     },
 355     {
 356         "EventCode": "0x17",
 357         "Counter": "0,1,2,3",
 358         "UMask": "0x1",
 359         "EventName": "INST_QUEUE_WRITES",
 360         "SampleAfterValue": "2000000",
 361         "BriefDescription": "Instructions written to instruction queue."
 362     },
 363     {
 364         "EventCode": "0x0",
 365         "Counter": "Fixed counter 1",
 366         "UMask": "0x0",
 367         "EventName": "INST_RETIRED.ANY",
 368         "SampleAfterValue": "2000000",
 369         "BriefDescription": "Instructions retired (fixed counter)"
 370     },
 371     {
 372         "PEBS": "1",
 373         "EventCode": "0xC0",
 374         "Counter": "0,1,2,3",
 375         "UMask": "0x1",
 376         "EventName": "INST_RETIRED.ANY_P",
 377         "SampleAfterValue": "2000000",
 378         "BriefDescription": "Instructions retired (Programmable counter and Precise Event)"
 379     },
 380     {
 381         "PEBS": "1",
 382         "EventCode": "0xC0",
 383         "Counter": "0,1,2,3",
 384         "UMask": "0x4",
 385         "EventName": "INST_RETIRED.MMX",
 386         "SampleAfterValue": "2000000",
 387         "BriefDescription": "Retired MMX instructions (Precise Event)"
 388     },
 389     {
 390         "PEBS": "1",
 391         "EventCode": "0xC0",
 392         "Invert": "1",
 393         "Counter": "0,1,2,3",
 394         "UMask": "0x1",
 395         "EventName": "INST_RETIRED.TOTAL_CYCLES",
 396         "SampleAfterValue": "2000000",
 397         "BriefDescription": "Total cycles (Precise Event)",
 398         "CounterMask": "16"
 399     },
 400     {
 401         "PEBS": "1",
 402         "EventCode": "0xC0",
 403         "Counter": "0,1,2,3",
 404         "UMask": "0x2",
 405         "EventName": "INST_RETIRED.X87",
 406         "SampleAfterValue": "2000000",
 407         "BriefDescription": "Retired floating-point operations (Precise Event)"
 408     },
 409     {
 410         "EventCode": "0x4C",
 411         "Counter": "0,1",
 412         "UMask": "0x1",
 413         "EventName": "LOAD_HIT_PRE",
 414         "SampleAfterValue": "200000",
 415         "BriefDescription": "Load operations conflicting with software prefetches"
 416     },
 417     {
 418         "EventCode": "0xA8",
 419         "Counter": "0,1,2,3",
 420         "UMask": "0x1",
 421         "EventName": "LSD.ACTIVE",
 422         "SampleAfterValue": "2000000",
 423         "BriefDescription": "Cycles when uops were delivered by the LSD",
 424         "CounterMask": "1"
 425     },
 426     {
 427         "EventCode": "0xA8",
 428         "Invert": "1",
 429         "Counter": "0,1,2,3",
 430         "UMask": "0x1",
 431         "EventName": "LSD.INACTIVE",
 432         "SampleAfterValue": "2000000",
 433         "BriefDescription": "Cycles no uops were delivered by the LSD",
 434         "CounterMask": "1"
 435     },
 436     {
 437         "EventCode": "0x20",
 438         "Counter": "0,1,2,3",
 439         "UMask": "0x1",
 440         "EventName": "LSD_OVERFLOW",
 441         "SampleAfterValue": "2000000",
 442         "BriefDescription": "Loops that can't stream from the instruction queue"
 443     },
 444     {
 445         "EventCode": "0xC3",
 446         "Counter": "0,1,2,3",
 447         "UMask": "0x1",
 448         "EventName": "MACHINE_CLEARS.CYCLES",
 449         "SampleAfterValue": "20000",
 450         "BriefDescription": "Cycles machine clear asserted"
 451     },
 452     {
 453         "EventCode": "0xC3",
 454         "Counter": "0,1,2,3",
 455         "UMask": "0x2",
 456         "EventName": "MACHINE_CLEARS.MEM_ORDER",
 457         "SampleAfterValue": "20000",
 458         "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts"
 459     },
 460     {
 461         "EventCode": "0xC3",
 462         "Counter": "0,1,2,3",
 463         "UMask": "0x4",
 464         "EventName": "MACHINE_CLEARS.SMC",
 465         "SampleAfterValue": "20000",
 466         "BriefDescription": "Self-Modifying Code detected"
 467     },
 468     {
 469         "EventCode": "0xA2",
 470         "Counter": "0,1,2,3",
 471         "UMask": "0x1",
 472         "EventName": "RESOURCE_STALLS.ANY",
 473         "SampleAfterValue": "2000000",
 474         "BriefDescription": "Resource related stall cycles"
 475     },
 476     {
 477         "EventCode": "0xA2",
 478         "Counter": "0,1,2,3",
 479         "UMask": "0x20",
 480         "EventName": "RESOURCE_STALLS.FPCW",
 481         "SampleAfterValue": "2000000",
 482         "BriefDescription": "FPU control word write stall cycles"
 483     },
 484     {
 485         "EventCode": "0xA2",
 486         "Counter": "0,1,2,3",
 487         "UMask": "0x2",
 488         "EventName": "RESOURCE_STALLS.LOAD",
 489         "SampleAfterValue": "2000000",
 490         "BriefDescription": "Load buffer stall cycles"
 491     },
 492     {
 493         "EventCode": "0xA2",
 494         "Counter": "0,1,2,3",
 495         "UMask": "0x40",
 496         "EventName": "RESOURCE_STALLS.MXCSR",
 497         "SampleAfterValue": "2000000",
 498         "BriefDescription": "MXCSR rename stall cycles"
 499     },
 500     {
 501         "EventCode": "0xA2",
 502         "Counter": "0,1,2,3",
 503         "UMask": "0x80",
 504         "EventName": "RESOURCE_STALLS.OTHER",
 505         "SampleAfterValue": "2000000",
 506         "BriefDescription": "Other Resource related stall cycles"
 507     },
 508     {
 509         "EventCode": "0xA2",
 510         "Counter": "0,1,2,3",
 511         "UMask": "0x10",
 512         "EventName": "RESOURCE_STALLS.ROB_FULL",
 513         "SampleAfterValue": "2000000",
 514         "BriefDescription": "ROB full stall cycles"
 515     },
 516     {
 517         "EventCode": "0xA2",
 518         "Counter": "0,1,2,3",
 519         "UMask": "0x4",
 520         "EventName": "RESOURCE_STALLS.RS_FULL",
 521         "SampleAfterValue": "2000000",
 522         "BriefDescription": "Reservation Station full stall cycles"
 523     },
 524     {
 525         "EventCode": "0xA2",
 526         "Counter": "0,1,2,3",
 527         "UMask": "0x8",
 528         "EventName": "RESOURCE_STALLS.STORE",
 529         "SampleAfterValue": "2000000",
 530         "BriefDescription": "Store buffer stall cycles"
 531     },
 532     {
 533         "PEBS": "1",
 534         "EventCode": "0xC7",
 535         "Counter": "0,1,2,3",
 536         "UMask": "0x4",
 537         "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
 538         "SampleAfterValue": "200000",
 539         "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)"
 540     },
 541     {
 542         "PEBS": "1",
 543         "EventCode": "0xC7",
 544         "Counter": "0,1,2,3",
 545         "UMask": "0x1",
 546         "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
 547         "SampleAfterValue": "200000",
 548         "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)"
 549     },
 550     {
 551         "PEBS": "1",
 552         "EventCode": "0xC7",
 553         "Counter": "0,1,2,3",
 554         "UMask": "0x8",
 555         "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
 556         "SampleAfterValue": "200000",
 557         "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)"
 558     },
 559     {
 560         "PEBS": "1",
 561         "EventCode": "0xC7",
 562         "Counter": "0,1,2,3",
 563         "UMask": "0x2",
 564         "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
 565         "SampleAfterValue": "200000",
 566         "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)"
 567     },
 568     {
 569         "PEBS": "1",
 570         "EventCode": "0xC7",
 571         "Counter": "0,1,2,3",
 572         "UMask": "0x10",
 573         "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
 574         "SampleAfterValue": "200000",
 575         "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)"
 576     },
 577     {
 578         "EventCode": "0xDB",
 579         "Counter": "0,1,2,3",
 580         "UMask": "0x1",
 581         "EventName": "UOP_UNFUSION",
 582         "SampleAfterValue": "2000000",
 583         "BriefDescription": "Uop unfusions due to FP exceptions"
 584     },
 585     {
 586         "EventCode": "0xD1",
 587         "Counter": "0,1,2,3",
 588         "UMask": "0x4",
 589         "EventName": "UOPS_DECODED.ESP_FOLDING",
 590         "SampleAfterValue": "2000000",
 591         "BriefDescription": "Stack pointer instructions decoded"
 592     },
 593     {
 594         "EventCode": "0xD1",
 595         "Counter": "0,1,2,3",
 596         "UMask": "0x8",
 597         "EventName": "UOPS_DECODED.ESP_SYNC",
 598         "SampleAfterValue": "2000000",
 599         "BriefDescription": "Stack pointer sync operations"
 600     },
 601     {
 602         "EventCode": "0xD1",
 603         "Counter": "0,1,2,3",
 604         "UMask": "0x2",
 605         "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
 606         "SampleAfterValue": "2000000",
 607         "BriefDescription": "Uops decoded by Microcode Sequencer",
 608         "CounterMask": "1"
 609     },
 610     {
 611         "EventCode": "0xD1",
 612         "Invert": "1",
 613         "Counter": "0,1,2,3",
 614         "UMask": "0x1",
 615         "EventName": "UOPS_DECODED.STALL_CYCLES",
 616         "SampleAfterValue": "2000000",
 617         "BriefDescription": "Cycles no Uops are decoded",
 618         "CounterMask": "1"
 619     },
 620     {
 621         "EventCode": "0xB1",
 622         "Counter": "0,1,2,3",
 623         "UMask": "0x3f",
 624         "AnyThread": "1",
 625         "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
 626         "SampleAfterValue": "2000000",
 627         "BriefDescription": "Cycles Uops executed on any port (core count)",
 628         "CounterMask": "1"
 629     },
 630     {
 631         "EventCode": "0xB1",
 632         "Counter": "0,1,2,3",
 633         "UMask": "0x1f",
 634         "AnyThread": "1",
 635         "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
 636         "SampleAfterValue": "2000000",
 637         "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
 638         "CounterMask": "1"
 639     },
 640     {
 641         "EventCode": "0xB1",
 642         "Invert": "1",
 643         "Counter": "0,1,2,3",
 644         "UMask": "0x3f",
 645         "AnyThread": "1",
 646         "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT",
 647         "SampleAfterValue": "2000000",
 648         "BriefDescription": "Uops executed on any port (core count)",
 649         "CounterMask": "1",
 650         "EdgeDetect": "1"
 651     },
 652     {
 653         "EventCode": "0xB1",
 654         "Invert": "1",
 655         "Counter": "0,1,2,3",
 656         "UMask": "0x1f",
 657         "AnyThread": "1",
 658         "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5",
 659         "SampleAfterValue": "2000000",
 660         "BriefDescription": "Uops executed on ports 0-4 (core count)",
 661         "CounterMask": "1",
 662         "EdgeDetect": "1"
 663     },
 664     {
 665         "EventCode": "0xB1",
 666         "Invert": "1",
 667         "Counter": "0,1,2,3",
 668         "UMask": "0x3f",
 669         "AnyThread": "1",
 670         "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
 671         "SampleAfterValue": "2000000",
 672         "BriefDescription": "Cycles no Uops issued on any port (core count)",
 673         "CounterMask": "1"
 674     },
 675     {
 676         "EventCode": "0xB1",
 677         "Invert": "1",
 678         "Counter": "0,1,2,3",
 679         "UMask": "0x1f",
 680         "AnyThread": "1",
 681         "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
 682         "SampleAfterValue": "2000000",
 683         "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
 684         "CounterMask": "1"
 685     },
 686     {
 687         "EventCode": "0xB1",
 688         "Counter": "0,1,2,3",
 689         "UMask": "0x1",
 690         "EventName": "UOPS_EXECUTED.PORT0",
 691         "SampleAfterValue": "2000000",
 692         "BriefDescription": "Uops executed on port 0"
 693     },
 694     {
 695         "EventCode": "0xB1",
 696         "Counter": "0,1,2,3",
 697         "UMask": "0x40",
 698         "EventName": "UOPS_EXECUTED.PORT015",
 699         "SampleAfterValue": "2000000",
 700         "BriefDescription": "Uops issued on ports 0, 1 or 5"
 701     },
 702     {
 703         "EventCode": "0xB1",
 704         "Invert": "1",
 705         "Counter": "0,1,2,3",
 706         "UMask": "0x40",
 707         "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
 708         "SampleAfterValue": "2000000",
 709         "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
 710         "CounterMask": "1"
 711     },
 712     {
 713         "EventCode": "0xB1",
 714         "Counter": "0,1,2,3",
 715         "UMask": "0x2",
 716         "EventName": "UOPS_EXECUTED.PORT1",
 717         "SampleAfterValue": "2000000",
 718         "BriefDescription": "Uops executed on port 1"
 719     },
 720     {
 721         "EventCode": "0xB1",
 722         "Counter": "0,1,2,3",
 723         "UMask": "0x4",
 724         "AnyThread": "1",
 725         "EventName": "UOPS_EXECUTED.PORT2_CORE",
 726         "SampleAfterValue": "2000000",
 727         "BriefDescription": "Uops executed on port 2 (core count)"
 728     },
 729     {
 730         "EventCode": "0xB1",
 731         "Counter": "0,1,2,3",
 732         "UMask": "0x80",
 733         "AnyThread": "1",
 734         "EventName": "UOPS_EXECUTED.PORT234_CORE",
 735         "SampleAfterValue": "2000000",
 736         "BriefDescription": "Uops issued on ports 2, 3 or 4"
 737     },
 738     {
 739         "EventCode": "0xB1",
 740         "Counter": "0,1,2,3",
 741         "UMask": "0x8",
 742         "AnyThread": "1",
 743         "EventName": "UOPS_EXECUTED.PORT3_CORE",
 744         "SampleAfterValue": "2000000",
 745         "BriefDescription": "Uops executed on port 3 (core count)"
 746     },
 747     {
 748         "EventCode": "0xB1",
 749         "Counter": "0,1,2,3",
 750         "UMask": "0x10",
 751         "AnyThread": "1",
 752         "EventName": "UOPS_EXECUTED.PORT4_CORE",
 753         "SampleAfterValue": "2000000",
 754         "BriefDescription": "Uops executed on port 4 (core count)"
 755     },
 756     {
 757         "EventCode": "0xB1",
 758         "Counter": "0,1,2,3",
 759         "UMask": "0x20",
 760         "EventName": "UOPS_EXECUTED.PORT5",
 761         "SampleAfterValue": "2000000",
 762         "BriefDescription": "Uops executed on port 5"
 763     },
 764     {
 765         "EventCode": "0xE",
 766         "Counter": "0,1,2,3",
 767         "UMask": "0x1",
 768         "EventName": "UOPS_ISSUED.ANY",
 769         "SampleAfterValue": "2000000",
 770         "BriefDescription": "Uops issued"
 771     },
 772     {
 773         "EventCode": "0xE",
 774         "Invert": "1",
 775         "Counter": "0,1,2,3",
 776         "UMask": "0x1",
 777         "AnyThread": "1",
 778         "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
 779         "SampleAfterValue": "2000000",
 780         "BriefDescription": "Cycles no Uops were issued on any thread",
 781         "CounterMask": "1"
 782     },
 783     {
 784         "EventCode": "0xE",
 785         "Counter": "0,1,2,3",
 786         "UMask": "0x1",
 787         "AnyThread": "1",
 788         "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
 789         "SampleAfterValue": "2000000",
 790         "BriefDescription": "Cycles Uops were issued on either thread",
 791         "CounterMask": "1"
 792     },
 793     {
 794         "EventCode": "0xE",
 795         "Counter": "0,1,2,3",
 796         "UMask": "0x2",
 797         "EventName": "UOPS_ISSUED.FUSED",
 798         "SampleAfterValue": "2000000",
 799         "BriefDescription": "Fused Uops issued"
 800     },
 801     {
 802         "EventCode": "0xE",
 803         "Invert": "1",
 804         "Counter": "0,1,2,3",
 805         "UMask": "0x1",
 806         "EventName": "UOPS_ISSUED.STALL_CYCLES",
 807         "SampleAfterValue": "2000000",
 808         "BriefDescription": "Cycles no Uops were issued",
 809         "CounterMask": "1"
 810     },
 811     {
 812         "PEBS": "1",
 813         "EventCode": "0xC2",
 814         "Counter": "0,1,2,3",
 815         "UMask": "0x1",
 816         "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
 817         "SampleAfterValue": "2000000",
 818         "BriefDescription": "Cycles Uops are being retired",
 819         "CounterMask": "1"
 820     },
 821     {
 822         "PEBS": "1",
 823         "EventCode": "0xC2",
 824         "Counter": "0,1,2,3",
 825         "UMask": "0x1",
 826         "EventName": "UOPS_RETIRED.ANY",
 827         "SampleAfterValue": "2000000",
 828         "BriefDescription": "Uops retired (Precise Event)"
 829     },
 830     {
 831         "PEBS": "1",
 832         "EventCode": "0xC2",
 833         "Counter": "0,1,2,3",
 834         "UMask": "0x4",
 835         "EventName": "UOPS_RETIRED.MACRO_FUSED",
 836         "SampleAfterValue": "2000000",
 837         "BriefDescription": "Macro-fused Uops retired (Precise Event)"
 838     },
 839     {
 840         "PEBS": "1",
 841         "EventCode": "0xC2",
 842         "Counter": "0,1,2,3",
 843         "UMask": "0x2",
 844         "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
 845         "SampleAfterValue": "2000000",
 846         "BriefDescription": "Retirement slots used (Precise Event)"
 847     },
 848     {
 849         "PEBS": "1",
 850         "EventCode": "0xC2",
 851         "Invert": "1",
 852         "Counter": "0,1,2,3",
 853         "UMask": "0x1",
 854         "EventName": "UOPS_RETIRED.STALL_CYCLES",
 855         "SampleAfterValue": "2000000",
 856         "BriefDescription": "Cycles Uops are not retiring (Precise Event)",
 857         "CounterMask": "1"
 858     },
 859     {
 860         "PEBS": "1",
 861         "EventCode": "0xC2",
 862         "Invert": "1",
 863         "Counter": "0,1,2,3",
 864         "UMask": "0x1",
 865         "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
 866         "SampleAfterValue": "2000000",
 867         "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
 868         "CounterMask": "16"
 869     },
 870     {
 871         "PEBS": "2",
 872         "EventCode": "0xC0",
 873         "Invert": "1",
 874         "Counter": "0,1,2,3",
 875         "UMask": "0x1",
 876         "EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
 877         "SampleAfterValue": "2000000",
 878         "BriefDescription": "Total cycles (Precise Event)",
 879         "CounterMask": "16"
 880     }
 881 ]