tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json

   1 [
   2     {
   3         "EventCode": "0x08",
   4         "UMask": "0x1",
   5         "BriefDescription": "Load misses in all DTLB levels that cause page walks",
   6         "Counter": "0,1,2,3",
   7         "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
   8         "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
   9         "SampleAfterValue": "100003",
  10         "CounterHTOff": "0,1,2,3,4,5,6,7"
  11     },
  12     {
  13         "EventCode": "0x08",
  14         "UMask": "0x2",
  15         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
  16         "Counter": "0,1,2,3",
  17         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
  18         "PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.",
  19         "SampleAfterValue": "2000003",
  20         "CounterHTOff": "0,1,2,3,4,5,6,7"
  21     },
  22     {
  23         "EventCode": "0x08",
  24         "UMask": "0x4",
  25         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
  26         "Counter": "0,1,2,3",
  27         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
  28         "PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.",
  29         "SampleAfterValue": "2000003",
  30         "CounterHTOff": "0,1,2,3,4,5,6,7"
  31     },
  32     {
  33         "EventCode": "0x08",
  34         "UMask": "0x8",
  35         "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
  36         "Counter": "0,1,2,3",
  37         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
  38         "SampleAfterValue": "2000003",
  39         "CounterHTOff": "0,1,2,3,4,5,6,7"
  40     },
  41     {
  42         "EventCode": "0x08",
  43         "UMask": "0x10",
  44         "BriefDescription": "Cycles when PMH is busy with page walks",
  45         "Counter": "0,1,2,3",
  46         "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
  47         "PublicDescription": "This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
  48         "SampleAfterValue": "2000003",
  49         "CounterHTOff": "0,1,2,3,4,5,6,7"
  50     },
  51     {
  52         "EventCode": "0x08",
  53         "UMask": "0x20",
  54         "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (4K)",
  55         "Counter": "0,1,2,3",
  56         "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
  57         "PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
  58         "SampleAfterValue": "2000003",
  59         "CounterHTOff": "0,1,2,3,4,5,6,7"
  60     },
  61     {
  62         "EventCode": "0x08",
  63         "UMask": "0x40",
  64         "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (2M)",
  65         "Counter": "0,1,2,3",
  66         "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
  67         "PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
  68         "SampleAfterValue": "2000003",
  69         "CounterHTOff": "0,1,2,3,4,5,6,7"
  70     },
  71     {
  72         "EventCode": "0x08",
  73         "UMask": "0x80",
  74         "BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed",
  75         "Counter": "0,1,2,3",
  76         "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS",
  77         "PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.",
  78         "SampleAfterValue": "100003",
  79         "CounterHTOff": "0,1,2,3,4,5,6,7"
  80     },
  81     {
  82         "EventCode": "0x49",
  83         "UMask": "0x1",
  84         "BriefDescription": "Store misses in all DTLB levels that cause page walks",
  85         "Counter": "0,1,2,3",
  86         "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
  87         "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
  88         "SampleAfterValue": "100003",
  89         "CounterHTOff": "0,1,2,3,4,5,6,7"
  90     },
  91     {
  92         "EventCode": "0x49",
  93         "UMask": "0x2",
  94         "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
  95         "Counter": "0,1,2,3",
  96         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
  97         "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.",
  98         "SampleAfterValue": "100003",
  99         "CounterHTOff": "0,1,2,3,4,5,6,7"
 100     },
 101     {
 102         "EventCode": "0x49",
 103         "UMask": "0x4",
 104         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
 105         "Counter": "0,1,2,3",
 106         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
 107         "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.",
 108         "SampleAfterValue": "100003",
 109         "CounterHTOff": "0,1,2,3,4,5,6,7"
 110     },
 111     {
 112         "EventCode": "0x49",
 113         "UMask": "0x8",
 114         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)",
 115         "Counter": "0,1,2,3",
 116         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
 117         "SampleAfterValue": "100003",
 118         "CounterHTOff": "0,1,2,3,4,5,6,7"
 119     },
 120     {
 121         "EventCode": "0x49",
 122         "UMask": "0x10",
 123         "BriefDescription": "Cycles when PMH is busy with page walks",
 124         "Counter": "0,1,2,3",
 125         "EventName": "DTLB_STORE_MISSES.WALK_DURATION",
 126         "PublicDescription": "This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by DTLB store misses.",
 127         "SampleAfterValue": "100003",
 128         "CounterHTOff": "0,1,2,3,4,5,6,7"
 129     },
 130     {
 131         "EventCode": "0x49",
 132         "UMask": "0x20",
 133         "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (4K)",
 134         "Counter": "0,1,2,3",
 135         "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
 136         "PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
 137         "SampleAfterValue": "100003",
 138         "CounterHTOff": "0,1,2,3,4,5,6,7"
 139     },
 140     {
 141         "EventCode": "0x49",
 142         "UMask": "0x40",
 143         "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (2M)",
 144         "Counter": "0,1,2,3",
 145         "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
 146         "PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
 147         "SampleAfterValue": "100003",
 148         "CounterHTOff": "0,1,2,3,4,5,6,7"
 149     },
 150     {
 151         "EventCode": "0x49",
 152         "UMask": "0x80",
 153         "BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed",
 154         "Counter": "0,1,2,3",
 155         "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS",
 156         "PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed.",
 157         "SampleAfterValue": "100003",
 158         "CounterHTOff": "0,1,2,3,4,5,6,7"
 159     },
 160     {
 161         "EventCode": "0x4f",
 162         "UMask": "0x10",
 163         "BriefDescription": "Cycle count for an Extended Page table walk.",
 164         "Counter": "0,1,2,3",
 165         "EventName": "EPT.WALK_CYCLES",
 166         "SampleAfterValue": "2000003",
 167         "CounterHTOff": "0,1,2,3,4,5,6,7"
 168     },
 169     {
 170         "EventCode": "0x85",
 171         "UMask": "0x1",
 172         "BriefDescription": "Misses at all ITLB levels that cause page walks",
 173         "Counter": "0,1,2,3",
 174         "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
 175         "PublicDescription": "Misses in ITLB that causes a page walk of any page size.",
 176         "SampleAfterValue": "100003",
 177         "CounterHTOff": "0,1,2,3,4,5,6,7"
 178     },
 179     {
 180         "EventCode": "0x85",
 181         "UMask": "0x2",
 182         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
 183         "Counter": "0,1,2,3",
 184         "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
 185         "PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.",
 186         "SampleAfterValue": "100003",
 187         "CounterHTOff": "0,1,2,3,4,5,6,7"
 188     },
 189     {
 190         "EventCode": "0x85",
 191         "UMask": "0x4",
 192         "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
 193         "Counter": "0,1,2,3",
 194         "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
 195         "PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.",
 196         "SampleAfterValue": "100003",
 197         "CounterHTOff": "0,1,2,3,4,5,6,7"
 198     },
 199     {
 200         "EventCode": "0x85",
 201         "UMask": "0x8",
 202         "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
 203         "Counter": "0,1,2,3",
 204         "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
 205         "SampleAfterValue": "100003",
 206         "CounterHTOff": "0,1,2,3,4,5,6,7"
 207     },
 208     {
 209         "EventCode": "0x85",
 210         "UMask": "0x10",
 211         "BriefDescription": "Cycles when PMH is busy with page walks",
 212         "Counter": "0,1,2,3",
 213         "EventName": "ITLB_MISSES.WALK_DURATION",
 214         "PublicDescription": "This event counts cycles when the  page miss handler (PMH) is servicing page walks caused by ITLB misses.",
 215         "SampleAfterValue": "100003",
 216         "CounterHTOff": "0,1,2,3,4,5,6,7"
 217     },
 218     {
 219         "EventCode": "0x85",
 220         "UMask": "0x20",
 221         "BriefDescription": "Core misses that miss the  DTLB and hit the STLB (4K)",
 222         "Counter": "0,1,2,3",
 223         "EventName": "ITLB_MISSES.STLB_HIT_4K",
 224         "PublicDescription": "ITLB misses that hit STLB (4K).",
 225         "SampleAfterValue": "100003",
 226         "CounterHTOff": "0,1,2,3,4,5,6,7"
 227     },
 228     {
 229         "EventCode": "0x85",
 230         "UMask": "0x40",
 231         "BriefDescription": "Code misses that miss the  DTLB and hit the STLB (2M)",
 232         "Counter": "0,1,2,3",
 233         "EventName": "ITLB_MISSES.STLB_HIT_2M",
 234         "PublicDescription": "ITLB misses that hit STLB (2M).",
 235         "SampleAfterValue": "100003",
 236         "CounterHTOff": "0,1,2,3,4,5,6,7"
 237     },
 238     {
 239         "EventCode": "0xae",
 240         "UMask": "0x1",
 241         "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
 242         "Counter": "0,1,2,3",
 243         "EventName": "ITLB.ITLB_FLUSH",
 244         "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.",
 245         "SampleAfterValue": "100003",
 246         "CounterHTOff": "0,1,2,3,4,5,6,7"
 247     },
 248     {
 249         "EventCode": "0xBC",
 250         "UMask": "0x11",
 251         "BriefDescription": "Number of DTLB page walker hits in the L1+FB",
 252         "Counter": "0,1,2,3",
 253         "EventName": "PAGE_WALKER_LOADS.DTLB_L1",
 254         "PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.",
 255         "SampleAfterValue": "2000003",
 256         "CounterHTOff": "0,1,2,3"
 257     },
 258     {
 259         "EventCode": "0xBC",
 260         "UMask": "0x21",
 261         "BriefDescription": "Number of ITLB page walker hits in the L1+FB",
 262         "Counter": "0,1,2,3",
 263         "EventName": "PAGE_WALKER_LOADS.ITLB_L1",
 264         "PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.",
 265         "SampleAfterValue": "2000003",
 266         "CounterHTOff": "0,1,2,3"
 267     },
 268     {
 269         "EventCode": "0xBC",
 270         "UMask": "0x41",
 271         "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.",
 272         "Counter": "0,1,2,3",
 273         "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1",
 274         "SampleAfterValue": "2000003",
 275         "CounterHTOff": "0,1,2,3"
 276     },
 277     {
 278         "EventCode": "0xBC",
 279         "UMask": "0x81",
 280         "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.",
 281         "Counter": "0,1,2,3",
 282         "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1",
 283         "SampleAfterValue": "2000003",
 284         "CounterHTOff": "0,1,2,3"
 285     },
 286     {
 287         "EventCode": "0xBC",
 288         "UMask": "0x12",
 289         "BriefDescription": "Number of DTLB page walker hits in the L2",
 290         "Counter": "0,1,2,3",
 291         "EventName": "PAGE_WALKER_LOADS.DTLB_L2",
 292         "PublicDescription": "Number of DTLB page walker loads that hit in the L2.",
 293         "SampleAfterValue": "2000003",
 294         "CounterHTOff": "0,1,2,3"
 295     },
 296     {
 297         "EventCode": "0xBC",
 298         "UMask": "0x22",
 299         "BriefDescription": "Number of ITLB page walker hits in the L2",
 300         "Counter": "0,1,2,3",
 301         "EventName": "PAGE_WALKER_LOADS.ITLB_L2",
 302         "PublicDescription": "Number of ITLB page walker loads that hit in the L2.",
 303         "SampleAfterValue": "2000003",
 304         "CounterHTOff": "0,1,2,3"
 305     },
 306     {
 307         "EventCode": "0xBC",
 308         "UMask": "0x42",
 309         "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.",
 310         "Counter": "0,1,2,3",
 311         "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2",
 312         "SampleAfterValue": "2000003",
 313         "CounterHTOff": "0,1,2,3"
 314     },
 315     {
 316         "EventCode": "0xBC",
 317         "UMask": "0x82",
 318         "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
 319         "Counter": "0,1,2,3",
 320         "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2",
 321         "SampleAfterValue": "2000003",
 322         "CounterHTOff": "0,1,2,3"
 323     },
 324     {
 325         "EventCode": "0xBC",
 326         "UMask": "0x14",
 327         "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP",
 328         "Counter": "0,1,2,3",
 329         "EventName": "PAGE_WALKER_LOADS.DTLB_L3",
 330         "Errata": "HSD25",
 331         "PublicDescription": "Number of DTLB page walker loads that hit in the L3.",
 332         "SampleAfterValue": "2000003",
 333         "CounterHTOff": "0,1,2,3"
 334     },
 335     {
 336         "EventCode": "0xBC",
 337         "UMask": "0x24",
 338         "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP",
 339         "Counter": "0,1,2,3",
 340         "EventName": "PAGE_WALKER_LOADS.ITLB_L3",
 341         "Errata": "HSD25",
 342         "PublicDescription": "Number of ITLB page walker loads that hit in the L3.",
 343         "SampleAfterValue": "2000003",
 344         "CounterHTOff": "0,1,2,3"
 345     },
 346     {
 347         "EventCode": "0xBC",
 348         "UMask": "0x44",
 349         "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.",
 350         "Counter": "0,1,2,3",
 351         "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3",
 352         "SampleAfterValue": "2000003",
 353         "CounterHTOff": "0,1,2,3"
 354     },
 355     {
 356         "EventCode": "0xBC",
 357         "UMask": "0x84",
 358         "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
 359         "Counter": "0,1,2,3",
 360         "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3",
 361         "SampleAfterValue": "2000003",
 362         "CounterHTOff": "0,1,2,3"
 363     },
 364     {
 365         "EventCode": "0xBC",
 366         "UMask": "0x18",
 367         "BriefDescription": "Number of DTLB page walker hits in Memory",
 368         "Counter": "0,1,2,3",
 369         "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
 370         "Errata": "HSD25",
 371         "PublicDescription": "Number of DTLB page walker loads from memory.",
 372         "SampleAfterValue": "2000003",
 373         "CounterHTOff": "0,1,2,3"
 374     },
 375     {
 376         "EventCode": "0xBC",
 377         "UMask": "0x28",
 378         "BriefDescription": "Number of ITLB page walker hits in Memory",
 379         "Counter": "0,1,2,3",
 380         "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY",
 381         "Errata": "HSD25",
 382         "PublicDescription": "Number of ITLB page walker loads from memory.",
 383         "SampleAfterValue": "2000003",
 384         "CounterHTOff": "0,1,2,3"
 385     },
 386     {
 387         "EventCode": "0xBC",
 388         "UMask": "0x48",
 389         "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.",
 390         "Counter": "0,1,2,3",
 391         "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY",
 392         "SampleAfterValue": "2000003",
 393         "CounterHTOff": "0,1,2,3"
 394     },
 395     {
 396         "EventCode": "0xBC",
 397         "UMask": "0x88",
 398         "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.",
 399         "Counter": "0,1,2,3",
 400         "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY",
 401         "SampleAfterValue": "2000003",
 402         "CounterHTOff": "0,1,2,3"
 403     },
 404     {
 405         "EventCode": "0xBD",
 406         "UMask": "0x1",
 407         "BriefDescription": "DTLB flush attempts of the thread-specific entries",
 408         "Counter": "0,1,2,3",
 409         "EventName": "TLB_FLUSH.DTLB_THREAD",
 410         "PublicDescription": "DTLB flush attempts of the thread-specific entries.",
 411         "SampleAfterValue": "100003",
 412         "CounterHTOff": "0,1,2,3,4,5,6,7"
 413     },
 414     {
 415         "EventCode": "0xBD",
 416         "UMask": "0x20",
 417         "BriefDescription": "STLB flush attempts",
 418         "Counter": "0,1,2,3",
 419         "EventName": "TLB_FLUSH.STLB_ANY",
 420         "PublicDescription": "Count number of STLB flush attempts.",
 421         "SampleAfterValue": "100003",
 422         "CounterHTOff": "0,1,2,3,4,5,6,7"
 423     },
 424     {
 425         "EventCode": "0x08",
 426         "UMask": "0xe",
 427         "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
 428         "Counter": "0,1,2,3",
 429         "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
 430         "PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.",
 431         "SampleAfterValue": "100003",
 432         "CounterHTOff": "0,1,2,3,4,5,6,7"
 433     },
 434     {
 435         "EventCode": "0x08",
 436         "UMask": "0x60",
 437         "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
 438         "Counter": "0,1,2,3",
 439         "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
 440         "PublicDescription": "Number of cache load STLB hits. No page walk.",
 441         "SampleAfterValue": "2000003",
 442         "CounterHTOff": "0,1,2,3,4,5,6,7"
 443     },
 444     {
 445         "EventCode": "0x49",
 446         "UMask": "0xe",
 447         "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
 448         "Counter": "0,1,2,3",
 449         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
 450         "PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).",
 451         "SampleAfterValue": "100003",
 452         "CounterHTOff": "0,1,2,3,4,5,6,7"
 453     },
 454     {
 455         "EventCode": "0x49",
 456         "UMask": "0x60",
 457         "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
 458         "Counter": "0,1,2,3",
 459         "EventName": "DTLB_STORE_MISSES.STLB_HIT",
 460         "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
 461         "SampleAfterValue": "100003",
 462         "CounterHTOff": "0,1,2,3,4,5,6,7"
 463     },
 464     {
 465         "EventCode": "0x85",
 466         "UMask": "0xe",
 467         "BriefDescription": "Misses in all ITLB levels that cause completed page walks",
 468         "Counter": "0,1,2,3",
 469         "EventName": "ITLB_MISSES.WALK_COMPLETED",
 470         "PublicDescription": "Completed page walks in ITLB of any page size.",
 471         "SampleAfterValue": "100003",
 472         "CounterHTOff": "0,1,2,3,4,5,6,7"
 473     },
 474     {
 475         "EventCode": "0x85",
 476         "UMask": "0x60",
 477         "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",
 478         "Counter": "0,1,2,3",
 479         "EventName": "ITLB_MISSES.STLB_HIT",
 480         "PublicDescription": "ITLB misses that hit STLB. No page walk.",
 481         "SampleAfterValue": "100003",
 482         "CounterHTOff": "0,1,2,3,4,5,6,7"
 483     }
 484 ]