5 "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
7 "EventName": "MISALIGN_MEM_REF.LOADS",
8 "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.",
9 "SampleAfterValue": "2000003",
10 "CounterHTOff": "0,1,2,3,4,5,6,7"
15 "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
17 "EventName": "MISALIGN_MEM_REF.STORES",
18 "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.",
19 "SampleAfterValue": "2000003",
20 "CounterHTOff": "0,1,2,3,4,5,6,7"
25 "BriefDescription": "Number of times a TSX line had a cache conflict",
27 "EventName": "TX_MEM.ABORT_CONFLICT",
28 "PublicDescription": "Number of times a TSX line had a cache conflict.",
29 "SampleAfterValue": "2000003",
30 "CounterHTOff": "0,1,2,3,4,5,6,7"
35 "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
37 "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
38 "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.",
39 "SampleAfterValue": "2000003",
40 "CounterHTOff": "0,1,2,3,4,5,6,7"
45 "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",
47 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
48 "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
49 "SampleAfterValue": "2000003",
50 "CounterHTOff": "0,1,2,3,4,5,6,7"
55 "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",
57 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
58 "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
59 "SampleAfterValue": "2000003",
60 "CounterHTOff": "0,1,2,3,4,5,6,7"
65 "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",
67 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
68 "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
69 "SampleAfterValue": "2000003",
70 "CounterHTOff": "0,1,2,3,4,5,6,7"
75 "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",
77 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
78 "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
79 "SampleAfterValue": "2000003",
80 "CounterHTOff": "0,1,2,3,4,5,6,7"
85 "BriefDescription": "Number of times we could not allocate Lock Buffer",
87 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
88 "PublicDescription": "Number of times we could not allocate Lock Buffer.",
89 "SampleAfterValue": "2000003",
90 "CounterHTOff": "0,1,2,3,4,5,6,7"
95 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
97 "EventName": "TX_EXEC.MISC1",
98 "PublicDescription": "Unfriendly TSX abort triggered by a flowmarker.",
99 "SampleAfterValue": "2000003",
100 "CounterHTOff": "0,1,2,3,4,5,6,7"
105 "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
106 "Counter": "0,1,2,3",
107 "EventName": "TX_EXEC.MISC2",
108 "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
109 "SampleAfterValue": "2000003",
110 "CounterHTOff": "0,1,2,3,4,5,6,7"
115 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
116 "Counter": "0,1,2,3",
117 "EventName": "TX_EXEC.MISC3",
118 "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
119 "SampleAfterValue": "2000003",
120 "CounterHTOff": "0,1,2,3,4,5,6,7"
125 "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
126 "Counter": "0,1,2,3",
127 "EventName": "TX_EXEC.MISC4",
128 "PublicDescription": "RTM region detected inside HLE.",
129 "SampleAfterValue": "2000003",
130 "CounterHTOff": "0,1,2,3,4,5,6,7"
135 "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
136 "Counter": "0,1,2,3",
137 "EventName": "TX_EXEC.MISC5",
138 "SampleAfterValue": "2000003",
139 "CounterHTOff": "0,1,2,3,4,5,6,7"
144 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
145 "Counter": "0,1,2,3",
146 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
147 "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.",
148 "SampleAfterValue": "100003",
149 "CounterHTOff": "0,1,2,3,4,5,6,7"
154 "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions",
155 "Counter": "0,1,2,3",
156 "EventName": "HLE_RETIRED.START",
157 "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.",
158 "SampleAfterValue": "2000003",
159 "CounterHTOff": "0,1,2,3,4,5,6,7"
164 "BriefDescription": "Number of times HLE commit succeeded",
165 "Counter": "0,1,2,3",
166 "EventName": "HLE_RETIRED.COMMIT",
167 "PublicDescription": "Number of times HLE commit succeeded.",
168 "SampleAfterValue": "2000003",
169 "CounterHTOff": "0,1,2,3,4,5,6,7"
174 "BriefDescription": "Number of times HLE abort was triggered",
176 "Counter": "0,1,2,3",
177 "EventName": "HLE_RETIRED.ABORTED",
178 "PublicDescription": "Number of times HLE abort was triggered.",
179 "SampleAfterValue": "2000003",
180 "CounterHTOff": "0,1,2,3,4,5,6,7"
185 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
186 "Counter": "0,1,2,3",
187 "EventName": "HLE_RETIRED.ABORTED_MISC1",
188 "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
189 "SampleAfterValue": "2000003",
190 "CounterHTOff": "0,1,2,3,4,5,6,7"
195 "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",
196 "Counter": "0,1,2,3",
197 "EventName": "HLE_RETIRED.ABORTED_MISC2",
198 "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.",
199 "SampleAfterValue": "2000003",
200 "CounterHTOff": "0,1,2,3,4,5,6,7"
205 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",
206 "Counter": "0,1,2,3",
207 "EventName": "HLE_RETIRED.ABORTED_MISC3",
208 "PublicDescription": "Number of times a disallowed operation caused an HLE abort.",
209 "SampleAfterValue": "2000003",
210 "CounterHTOff": "0,1,2,3,4,5,6,7"
215 "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
216 "Counter": "0,1,2,3",
217 "EventName": "HLE_RETIRED.ABORTED_MISC4",
218 "PublicDescription": "Number of times HLE caused a fault.",
219 "SampleAfterValue": "2000003",
220 "CounterHTOff": "0,1,2,3,4,5,6,7"
225 "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
226 "Counter": "0,1,2,3",
227 "EventName": "HLE_RETIRED.ABORTED_MISC5",
228 "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.",
229 "SampleAfterValue": "2000003",
230 "CounterHTOff": "0,1,2,3,4,5,6,7"
235 "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions",
236 "Counter": "0,1,2,3",
237 "EventName": "RTM_RETIRED.START",
238 "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.",
239 "SampleAfterValue": "2000003",
240 "CounterHTOff": "0,1,2,3"
245 "BriefDescription": "Number of times RTM commit succeeded",
246 "Counter": "0,1,2,3",
247 "EventName": "RTM_RETIRED.COMMIT",
248 "PublicDescription": "Number of times RTM commit succeeded.",
249 "SampleAfterValue": "2000003",
250 "CounterHTOff": "0,1,2,3"
255 "BriefDescription": "Number of times RTM abort was triggered",
257 "Counter": "0,1,2,3",
258 "EventName": "RTM_RETIRED.ABORTED",
259 "PublicDescription": "Number of times RTM abort was triggered .",
260 "SampleAfterValue": "2000003",
261 "CounterHTOff": "0,1,2,3"
266 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
267 "Counter": "0,1,2,3",
268 "EventName": "RTM_RETIRED.ABORTED_MISC1",
269 "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
270 "SampleAfterValue": "2000003",
271 "CounterHTOff": "0,1,2,3"
276 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
277 "Counter": "0,1,2,3",
278 "EventName": "RTM_RETIRED.ABORTED_MISC2",
279 "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.",
280 "SampleAfterValue": "2000003",
281 "CounterHTOff": "0,1,2,3"
286 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
287 "Counter": "0,1,2,3",
288 "EventName": "RTM_RETIRED.ABORTED_MISC3",
289 "PublicDescription": "Number of times a disallowed operation caused an RTM abort.",
290 "SampleAfterValue": "2000003",
291 "CounterHTOff": "0,1,2,3"
296 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
297 "Counter": "0,1,2,3",
298 "EventName": "RTM_RETIRED.ABORTED_MISC4",
299 "PublicDescription": "Number of times a RTM caused a fault.",
300 "SampleAfterValue": "2000003",
301 "CounterHTOff": "0,1,2,3"
306 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
307 "Counter": "0,1,2,3",
308 "EventName": "RTM_RETIRED.ABORTED_MISC5",
309 "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.",
310 "SampleAfterValue": "2000003",
311 "CounterHTOff": "0,1,2,3"
316 "BriefDescription": "Loads with latency value being above 4",
320 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
322 "Errata": "BDM100, BDM35",
323 "PublicDescription": "This event counts loads with latency value being above four.",
325 "SampleAfterValue": "100003",
331 "BriefDescription": "Loads with latency value being above 8",
335 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
337 "Errata": "BDM100, BDM35",
338 "PublicDescription": "This event counts loads with latency value being above eight.",
340 "SampleAfterValue": "50021",
346 "BriefDescription": "Loads with latency value being above 16",
350 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
352 "Errata": "BDM100, BDM35",
353 "PublicDescription": "This event counts loads with latency value being above 16.",
355 "SampleAfterValue": "20011",
361 "BriefDescription": "Loads with latency value being above 32",
365 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
367 "Errata": "BDM100, BDM35",
368 "PublicDescription": "This event counts loads with latency value being above 32.",
370 "SampleAfterValue": "100007",
376 "BriefDescription": "Loads with latency value being above 64",
380 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
382 "Errata": "BDM100, BDM35",
383 "PublicDescription": "This event counts loads with latency value being above 64.",
385 "SampleAfterValue": "2003",
391 "BriefDescription": "Loads with latency value being above 128",
395 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
397 "Errata": "BDM100, BDM35",
398 "PublicDescription": "This event counts loads with latency value being above 128.",
400 "SampleAfterValue": "1009",
406 "BriefDescription": "Loads with latency value being above 256",
410 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
412 "Errata": "BDM100, BDM35",
413 "PublicDescription": "This event counts loads with latency value being above 256.",
415 "SampleAfterValue": "503",
421 "BriefDescription": "Loads with latency value being above 512",
425 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
427 "Errata": "BDM100, BDM35",
428 "PublicDescription": "This event counts loads with latency value being above 512.",
430 "SampleAfterValue": "101",
435 "EventCode": "0xB7, 0xBB",
437 "BriefDescription": "Counts all requests that miss in the L3",
438 "MSRValue": "0x3fbfc08fff",
439 "Counter": "0,1,2,3",
440 "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE",
441 "MSRIndex": "0x1a6,0x1a7",
442 "SampleAfterValue": "100003",
443 "CounterHTOff": "0,1,2,3"
447 "EventCode": "0xB7, 0xBB",
449 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and clean or shared data is transferred from remote cache",
450 "MSRValue": "0x087fc007f7",
451 "Counter": "0,1,2,3",
452 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",
453 "MSRIndex": "0x1a6,0x1a7",
454 "SampleAfterValue": "100003",
455 "CounterHTOff": "0,1,2,3"
459 "EventCode": "0xB7, 0xBB",
461 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the modified data is transferred from remote cache",
462 "MSRValue": "0x103fc007f7",
463 "Counter": "0,1,2,3",
464 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM",
465 "MSRIndex": "0x1a6,0x1a7",
466 "SampleAfterValue": "100003",
467 "CounterHTOff": "0,1,2,3"
471 "EventCode": "0xB7, 0xBB",
473 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from remote dram",
474 "MSRValue": "0x063bc007f7",
475 "Counter": "0,1,2,3",
476 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM",
477 "MSRIndex": "0x1a6,0x1a7",
478 "SampleAfterValue": "100003",
479 "CounterHTOff": "0,1,2,3"
483 "EventCode": "0xB7, 0xBB",
485 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram",
486 "MSRValue": "0x06040007f7",
487 "Counter": "0,1,2,3",
488 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",
489 "MSRIndex": "0x1a6,0x1a7",
490 "SampleAfterValue": "100003",
491 "CounterHTOff": "0,1,2,3"
495 "EventCode": "0xB7, 0xBB",
497 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss in the L3",
498 "MSRValue": "0x3fbfc007f7",
499 "Counter": "0,1,2,3",
500 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE",
501 "MSRIndex": "0x1a6,0x1a7",
502 "SampleAfterValue": "100003",
503 "CounterHTOff": "0,1,2,3"
507 "EventCode": "0xB7, 0xBB",
509 "BriefDescription": "Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram",
510 "MSRValue": "0x0604000244",
511 "Counter": "0,1,2,3",
512 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM",
513 "MSRIndex": "0x1a6,0x1a7",
514 "SampleAfterValue": "100003",
515 "CounterHTOff": "0,1,2,3"
519 "EventCode": "0xB7, 0xBB",
521 "BriefDescription": "Counts all demand & prefetch code reads that miss in the L3",
522 "MSRValue": "0x3fbfc00244",
523 "Counter": "0,1,2,3",
524 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE",
525 "MSRIndex": "0x1a6,0x1a7",
526 "SampleAfterValue": "100003",
527 "CounterHTOff": "0,1,2,3"
531 "EventCode": "0xB7, 0xBB",
533 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram",
534 "MSRValue": "0x0604000122",
535 "Counter": "0,1,2,3",
536 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM",
537 "MSRIndex": "0x1a6,0x1a7",
538 "SampleAfterValue": "100003",
539 "CounterHTOff": "0,1,2,3"
543 "EventCode": "0xB7, 0xBB",
545 "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3",
546 "MSRValue": "0x3fbfc00122",
547 "Counter": "0,1,2,3",
548 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE",
549 "MSRIndex": "0x1a6,0x1a7",
550 "SampleAfterValue": "100003",
551 "CounterHTOff": "0,1,2,3"
555 "EventCode": "0xB7, 0xBB",
557 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache",
558 "MSRValue": "0x087fc00091",
559 "Counter": "0,1,2,3",
560 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
561 "MSRIndex": "0x1a6,0x1a7",
562 "SampleAfterValue": "100003",
563 "CounterHTOff": "0,1,2,3"
567 "EventCode": "0xB7, 0xBB",
569 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache",
570 "MSRValue": "0x103fc00091",
571 "Counter": "0,1,2,3",
572 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM",
573 "MSRIndex": "0x1a6,0x1a7",
574 "SampleAfterValue": "100003",
575 "CounterHTOff": "0,1,2,3"
579 "EventCode": "0xB7, 0xBB",
581 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram",
582 "MSRValue": "0x063bc00091",
583 "Counter": "0,1,2,3",
584 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM",
585 "MSRIndex": "0x1a6,0x1a7",
586 "SampleAfterValue": "100003",
587 "CounterHTOff": "0,1,2,3"
591 "EventCode": "0xB7, 0xBB",
593 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram",
594 "MSRValue": "0x0604000091",
595 "Counter": "0,1,2,3",
596 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM",
597 "MSRIndex": "0x1a6,0x1a7",
598 "SampleAfterValue": "100003",
599 "CounterHTOff": "0,1,2,3"
603 "EventCode": "0xB7, 0xBB",
605 "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3",
606 "MSRValue": "0x3fbfc00091",
607 "Counter": "0,1,2,3",
608 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE",
609 "MSRIndex": "0x1a6,0x1a7",
610 "SampleAfterValue": "100003",
611 "CounterHTOff": "0,1,2,3"
615 "EventCode": "0xB7, 0xBB",
617 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that miss in the L3",
618 "MSRValue": "0x3fbfc00200",
619 "Counter": "0,1,2,3",
620 "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
621 "MSRIndex": "0x1a6,0x1a7",
622 "SampleAfterValue": "100003",
623 "CounterHTOff": "0,1,2,3"
627 "EventCode": "0xB7, 0xBB",
629 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3",
630 "MSRValue": "0x3fbfc00100",
631 "Counter": "0,1,2,3",
632 "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE",
633 "MSRIndex": "0x1a6,0x1a7",
634 "SampleAfterValue": "100003",
635 "CounterHTOff": "0,1,2,3"
639 "EventCode": "0xB7, 0xBB",
641 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache",
642 "MSRValue": "0x103fc00002",
643 "Counter": "0,1,2,3",
644 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM",
645 "MSRIndex": "0x1a6,0x1a7",
646 "SampleAfterValue": "100003",
647 "CounterHTOff": "0,1,2,3"