3 "EventCode": "0x1C040",
4 "EventName": "PM_XFER_FROM_SRC_PMC1",
5 "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
8 "EventCode": "0x1C056",
9 "EventName": "PM_DERAT_MISS_4K",
10 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
13 "EventCode": "0x1C058",
14 "EventName": "PM_DTLB_MISS_16G",
15 "BriefDescription": "Data TLB reload (after a miss) page size 16G. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
18 "EventCode": "0x1C05C",
19 "EventName": "PM_DTLB_MISS_2M",
20 "BriefDescription": "Data TLB reload (after a miss) page size 2M. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
23 "EventCode": "0x10062",
24 "EventName": "PM_LD_L3MISS_PEND_CYC",
25 "BriefDescription": "Cycles in which an L3 miss was pending for this thread."
28 "EventCode": "0x2001A",
29 "EventName": "PM_ITLB_HIT",
30 "BriefDescription": "The PTE required to translate the instruction address was resident in the TLB (instruction TLB access/IERAT reload). Applies to both HPT and RPT. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches."
33 "EventCode": "0x2003E",
34 "EventName": "PM_PTESYNC_FIN",
35 "BriefDescription": "Ptesync instruction finished in the store unit. Only one ptesync can finish at a time."
38 "EventCode": "0x2C040",
39 "EventName": "PM_XFER_FROM_SRC_PMC2",
40 "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
43 "EventCode": "0x2C054",
44 "EventName": "PM_DERAT_MISS_64K",
45 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
48 "EventCode": "0x2C056",
49 "EventName": "PM_DTLB_MISS_4K",
50 "BriefDescription": "Data TLB reload (after a miss) page size 4K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
53 "EventCode": "0x2C05A",
54 "EventName": "PM_DERAT_MISS_1G",
55 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 1G. Implies radix translation. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
58 "EventCode": "0x200F6",
59 "EventName": "PM_DERAT_MISS",
60 "BriefDescription": "DERAT Reloaded to satisfy a DERAT miss. All page sizes are counted by this event. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
63 "EventCode": "0x34044",
64 "EventName": "PM_DERAT_MISS_PREF",
65 "BriefDescription": "DERAT miss (TLB access) while servicing a data prefetch."
68 "EventCode": "0x3C040",
69 "EventName": "PM_XFER_FROM_SRC_PMC3",
70 "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
73 "EventCode": "0x3C054",
74 "EventName": "PM_DERAT_MISS_16M",
75 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
78 "EventCode": "0x3C056",
79 "EventName": "PM_DTLB_MISS_64K",
80 "BriefDescription": "Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
83 "EventCode": "0x3C058",
84 "EventName": "PM_LARX_FIN",
85 "BriefDescription": "Load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock."
88 "EventCode": "0x300FC",
89 "EventName": "PM_DTLB_MISS",
90 "BriefDescription": "The DPTEG required for the load/store instruction in execution was missing from the TLB. This event only counts for demand misses."
93 "EventCode": "0x4003E",
94 "EventName": "PM_LD_CMPL",
95 "BriefDescription": "Load instruction completed."
98 "EventCode": "0x4C040",
99 "EventName": "PM_XFER_FROM_SRC_PMC4",
100 "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
103 "EventCode": "0x4C056",
104 "EventName": "PM_DTLB_MISS_16M",
105 "BriefDescription": "Data TLB reload (after a miss) page size 16M. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
108 "EventCode": "0x4C05A",
109 "EventName": "PM_DTLB_MISS_1G",
110 "BriefDescription": "Data TLB reload (after a miss) page size 1G. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."