3 "ArchStdEvent": "L1D_CACHE_RD"
6 "ArchStdEvent": "L1D_CACHE_WR"
9 "ArchStdEvent": "L1D_CACHE_REFILL_RD"
12 "ArchStdEvent": "L1D_CACHE_INVAL"
15 "ArchStdEvent": "L1D_TLB_REFILL_RD"
18 "ArchStdEvent": "L1D_TLB_REFILL_WR"
21 "ArchStdEvent": "L2D_CACHE_RD"
24 "ArchStdEvent": "L2D_CACHE_WR"
27 "ArchStdEvent": "L2D_CACHE_REFILL_RD"
30 "ArchStdEvent": "L2D_CACHE_REFILL_WR"
33 "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
36 "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
39 "ArchStdEvent": "L2D_CACHE_INVAL"
42 "ArchStdEvent": "L1I_CACHE_REFILL"
45 "ArchStdEvent": "L1I_TLB_REFILL"
48 "ArchStdEvent": "L1D_CACHE_REFILL"
51 "ArchStdEvent": "L1D_CACHE"
54 "ArchStdEvent": "L1D_TLB_REFILL"
57 "ArchStdEvent": "L1I_CACHE"
60 "ArchStdEvent": "L2D_CACHE"
63 "ArchStdEvent": "L2D_CACHE_REFILL"
66 "ArchStdEvent": "L2D_CACHE_WB"
69 "PublicDescription": "This event counts any load or store operation which accesses the data L1 TLB",
70 "ArchStdEvent": "L1D_TLB",
71 "BriefDescription": "L1D TLB access"
74 "PublicDescription": "This event counts any instruction fetch which accesses the instruction L1 TLB",
75 "ArchStdEvent": "L1I_TLB"
78 "PublicDescription": "Level 2 access to data TLB that caused a page table walk. This event counts on any data access which causes L2D_TLB_REFILL to count",
80 "EventName": "L2D_TLB_ACCESS",
81 "BriefDescription": "L2D TLB access"
84 "PublicDescription": "Level 2 access to instruciton TLB that caused a page table walk. This event counts on any instruciton access which causes L2I_TLB_REFILL to count",
86 "EventName": "L2I_TLB_ACCESS",
87 "BriefDescription": "L2I TLB access"
90 "PublicDescription": "Branch target buffer misprediction",
92 "EventName": "BTB_MIS_PRED",
93 "BriefDescription": "BTB misprediction"
96 "PublicDescription": "ITB miss",
98 "EventName": "ITB_MISS",
99 "BriefDescription": "ITB miss"
102 "PublicDescription": "DTB miss",
103 "EventCode": "0x104",
104 "EventName": "DTB_MISS",
105 "BriefDescription": "DTB miss"
108 "PublicDescription": "Level 1 data cache late miss",
109 "EventCode": "0x105",
110 "EventName": "L1D_CACHE_LATE_MISS",
111 "BriefDescription": "L1D cache late miss"
114 "PublicDescription": "Level 1 data cache prefetch request",
115 "EventCode": "0x106",
116 "EventName": "L1D_CACHE_PREFETCH",
117 "BriefDescription": "L1D cache prefetch"
120 "PublicDescription": "Level 2 data cache prefetch request",
121 "EventCode": "0x107",
122 "EventName": "L2D_CACHE_PREFETCH",
123 "BriefDescription": "L2D cache prefetch"
126 "PublicDescription": "Level 1 stage 2 TLB refill",
127 "EventCode": "0x111",
128 "EventName": "L1_STAGE2_TLB_REFILL",
129 "BriefDescription": "L1 stage 2 TLB refill"
132 "PublicDescription": "Page walk cache level-0 stage-1 hit",
133 "EventCode": "0x112",
134 "EventName": "PAGE_WALK_L0_STAGE1_HIT",
135 "BriefDescription": "Page walk, L0 stage-1 hit"
138 "PublicDescription": "Page walk cache level-1 stage-1 hit",
139 "EventCode": "0x113",
140 "EventName": "PAGE_WALK_L1_STAGE1_HIT",
141 "BriefDescription": "Page walk, L1 stage-1 hit"
144 "PublicDescription": "Page walk cache level-2 stage-1 hit",
145 "EventCode": "0x114",
146 "EventName": "PAGE_WALK_L2_STAGE1_HIT",
147 "BriefDescription": "Page walk, L2 stage-1 hit"
150 "PublicDescription": "Page walk cache level-1 stage-2 hit",
151 "EventCode": "0x115",
152 "EventName": "PAGE_WALK_L1_STAGE2_HIT",
153 "BriefDescription": "Page walk, L1 stage-2 hit"
156 "PublicDescription": "Page walk cache level-2 stage-2 hit",
157 "EventCode": "0x116",
158 "EventName": "PAGE_WALK_L2_STAGE2_HIT",
159 "BriefDescription": "Page walk, L2 stage-2 hit"