1 // SPDX-License-Identifier: GPL-2.0
2 #ifndef ARCH_PERF_ARM64_EXCEPTION_TYPES_H
3 #define ARCH_PERF_ARM64_EXCEPTION_TYPES_H
6 #define HVC_STUB_ERR 0xbadca11
8 /* Per asm/kvm_asm.h */
9 #define ARM_EXCEPTION_IRQ 0
10 #define ARM_EXCEPTION_EL1_SERROR 1
11 #define ARM_EXCEPTION_TRAP 2
12 #define ARM_EXCEPTION_IL 3
13 /* The hyp-stub will return this for any kvm_call_hyp() call */
14 #define ARM_EXCEPTION_HYP_GONE HVC_STUB_ERR
16 #define kvm_arm_exception_type \
17 {ARM_EXCEPTION_IRQ, "IRQ" }, \
18 {ARM_EXCEPTION_EL1_SERROR, "SERROR" }, \
19 {ARM_EXCEPTION_TRAP, "TRAP" }, \
20 {ARM_EXCEPTION_IL, "ILLEGAL" }, \
21 {ARM_EXCEPTION_HYP_GONE, "HYP_GONE" }
24 #define ESR_ELx_EC_UNKNOWN (0x00)
25 #define ESR_ELx_EC_WFx (0x01)
26 /* Unallocated EC: 0x02 */
27 #define ESR_ELx_EC_CP15_32 (0x03)
28 #define ESR_ELx_EC_CP15_64 (0x04)
29 #define ESR_ELx_EC_CP14_MR (0x05)
30 #define ESR_ELx_EC_CP14_LS (0x06)
31 #define ESR_ELx_EC_FP_ASIMD (0x07)
32 #define ESR_ELx_EC_CP10_ID (0x08) /* EL2 only */
33 #define ESR_ELx_EC_PAC (0x09) /* EL2 and above */
34 /* Unallocated EC: 0x0A - 0x0B */
35 #define ESR_ELx_EC_CP14_64 (0x0C)
36 /* Unallocated EC: 0x0d */
37 #define ESR_ELx_EC_ILL (0x0E)
38 /* Unallocated EC: 0x0F - 0x10 */
39 #define ESR_ELx_EC_SVC32 (0x11)
40 #define ESR_ELx_EC_HVC32 (0x12) /* EL2 only */
41 #define ESR_ELx_EC_SMC32 (0x13) /* EL2 and above */
42 /* Unallocated EC: 0x14 */
43 #define ESR_ELx_EC_SVC64 (0x15)
44 #define ESR_ELx_EC_HVC64 (0x16) /* EL2 and above */
45 #define ESR_ELx_EC_SMC64 (0x17) /* EL2 and above */
46 #define ESR_ELx_EC_SYS64 (0x18)
47 #define ESR_ELx_EC_SVE (0x19)
48 #define ESR_ELx_EC_ERET (0x1a) /* EL2 only */
49 /* Unallocated EC: 0x1b - 0x1E */
50 #define ESR_ELx_EC_IMP_DEF (0x1f) /* EL3 only */
51 #define ESR_ELx_EC_IABT_LOW (0x20)
52 #define ESR_ELx_EC_IABT_CUR (0x21)
53 #define ESR_ELx_EC_PC_ALIGN (0x22)
54 /* Unallocated EC: 0x23 */
55 #define ESR_ELx_EC_DABT_LOW (0x24)
56 #define ESR_ELx_EC_DABT_CUR (0x25)
57 #define ESR_ELx_EC_SP_ALIGN (0x26)
58 /* Unallocated EC: 0x27 */
59 #define ESR_ELx_EC_FP_EXC32 (0x28)
60 /* Unallocated EC: 0x29 - 0x2B */
61 #define ESR_ELx_EC_FP_EXC64 (0x2C)
62 /* Unallocated EC: 0x2D - 0x2E */
63 #define ESR_ELx_EC_SERROR (0x2F)
64 #define ESR_ELx_EC_BREAKPT_LOW (0x30)
65 #define ESR_ELx_EC_BREAKPT_CUR (0x31)
66 #define ESR_ELx_EC_SOFTSTP_LOW (0x32)
67 #define ESR_ELx_EC_SOFTSTP_CUR (0x33)
68 #define ESR_ELx_EC_WATCHPT_LOW (0x34)
69 #define ESR_ELx_EC_WATCHPT_CUR (0x35)
70 /* Unallocated EC: 0x36 - 0x37 */
71 #define ESR_ELx_EC_BKPT32 (0x38)
72 /* Unallocated EC: 0x39 */
73 #define ESR_ELx_EC_VECTOR32 (0x3A) /* EL2 only */
74 /* Unallocated EC: 0x3B */
75 #define ESR_ELx_EC_BRK64 (0x3C)
76 /* Unallocated EC: 0x3D - 0x3F */
77 #define ESR_ELx_EC_MAX (0x3F)
79 #define ECN(x) { ESR_ELx_EC_##x, #x }
81 #define kvm_arm_exception_class \
82 ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \
83 ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(PAC), ECN(CP14_64), \
84 ECN(SVC64), ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(SVE), \
85 ECN(IMP_DEF), ECN(IABT_LOW), ECN(IABT_CUR), \
86 ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \
87 ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \
88 ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \
89 ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \
90 ECN(BKPT32), ECN(VECTOR32), ECN(BRK64)
92 #endif /* ARCH_PERF_ARM64_EXCEPTION_TYPES_H */