2 * Copyright (C) 2015 Josh Poimboeuf <jpoimboe@redhat.com>
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
21 #define unlikely(cond) (cond)
26 #include "../../elf.h"
27 #include "../../arch.h"
28 #include "../../warn.h"
30 static unsigned char op_to_cfi_reg[][2] = {
41 static int is_x86_64(struct elf *elf)
43 switch (elf->ehdr.e_machine) {
49 WARN("unexpected ELF machine type %d", elf->ehdr.e_machine);
54 bool arch_callee_saved_reg(unsigned char reg)
81 int arch_decode_instruction(struct elf *elf, struct section *sec,
82 unsigned long offset, unsigned int maxlen,
83 unsigned int *len, unsigned char *type,
84 unsigned long *immediate, struct stack_op *op)
88 unsigned char op1, op2, rex = 0, rex_b = 0, rex_r = 0, rex_w = 0,
89 rex_x = 0, modrm = 0, modrm_mod = 0, modrm_rm = 0,
90 modrm_reg = 0, sib = 0;
92 x86_64 = is_x86_64(elf);
96 insn_init(&insn, sec->data->d_buf + offset, maxlen, x86_64);
97 insn_get_length(&insn);
99 if (!insn_complete(&insn)) {
100 WARN_FUNC("can't decode instruction", sec, offset);
107 if (insn.vex_prefix.nbytes)
110 op1 = insn.opcode.bytes[0];
111 op2 = insn.opcode.bytes[1];
113 if (insn.rex_prefix.nbytes) {
114 rex = insn.rex_prefix.bytes[0];
115 rex_w = X86_REX_W(rex) >> 3;
116 rex_r = X86_REX_R(rex) >> 2;
117 rex_x = X86_REX_X(rex) >> 1;
118 rex_b = X86_REX_B(rex);
121 if (insn.modrm.nbytes) {
122 modrm = insn.modrm.bytes[0];
123 modrm_mod = X86_MODRM_MOD(modrm);
124 modrm_reg = X86_MODRM_REG(modrm);
125 modrm_rm = X86_MODRM_RM(modrm);
129 sib = insn.sib.bytes[0];
135 if (rex_w && !rex_b && modrm_mod == 3 && modrm_rm == 4) {
137 /* add/sub reg, %rsp */
139 op->src.type = OP_SRC_ADD;
140 op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
141 op->dest.type = OP_DEST_REG;
142 op->dest.reg = CFI_SP;
150 op->src.type = OP_SRC_REG;
151 op->src.reg = op_to_cfi_reg[op1 & 0x7][rex_b];
152 op->dest.type = OP_DEST_PUSH;
160 op->src.type = OP_SRC_POP;
161 op->dest.type = OP_DEST_REG;
162 op->dest.reg = op_to_cfi_reg[op1 & 0x7][rex_b];
170 op->src.type = OP_SRC_CONST;
171 op->dest.type = OP_DEST_PUSH;
175 *type = INSN_JUMP_CONDITIONAL;
186 op->src.type = OP_SRC_AND;
187 op->src.reg = CFI_SP;
188 op->src.offset = insn.immediate.value;
189 op->dest.type = OP_DEST_REG;
190 op->dest.reg = CFI_SP;
196 else if (modrm == 0xec)
201 /* add/sub imm, %rsp */
203 op->src.type = OP_SRC_ADD;
204 op->src.reg = CFI_SP;
205 op->src.offset = insn.immediate.value * sign;
206 op->dest.type = OP_DEST_REG;
207 op->dest.reg = CFI_SP;
211 if (rex_w && !rex_r && modrm_mod == 3 && modrm_reg == 4) {
215 op->src.type = OP_SRC_REG;
216 op->src.reg = CFI_SP;
217 op->dest.type = OP_DEST_REG;
218 op->dest.reg = op_to_cfi_reg[modrm_rm][rex_b];
222 if (rex_w && !rex_b && modrm_mod == 3 && modrm_rm == 4) {
226 op->src.type = OP_SRC_REG;
227 op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
228 op->dest.type = OP_DEST_REG;
229 op->dest.reg = CFI_SP;
236 (modrm_mod == 1 || modrm_mod == 2) && modrm_rm == 5) {
238 /* mov reg, disp(%rbp) */
240 op->src.type = OP_SRC_REG;
241 op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
242 op->dest.type = OP_DEST_REG_INDIRECT;
243 op->dest.reg = CFI_BP;
244 op->dest.offset = insn.displacement.value;
246 } else if (rex_w && !rex_b && modrm_rm == 4 && sib == 0x24) {
248 /* mov reg, disp(%rsp) */
250 op->src.type = OP_SRC_REG;
251 op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
252 op->dest.type = OP_DEST_REG_INDIRECT;
253 op->dest.reg = CFI_SP;
254 op->dest.offset = insn.displacement.value;
260 if (rex_w && !rex_b && modrm_mod == 1 && modrm_rm == 5) {
262 /* mov disp(%rbp), reg */
264 op->src.type = OP_SRC_REG_INDIRECT;
265 op->src.reg = CFI_BP;
266 op->src.offset = insn.displacement.value;
267 op->dest.type = OP_DEST_REG;
268 op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r];
270 } else if (rex_w && !rex_b && sib == 0x24 &&
271 modrm_mod != 3 && modrm_rm == 4) {
273 /* mov disp(%rsp), reg */
275 op->src.type = OP_SRC_REG_INDIRECT;
276 op->src.reg = CFI_SP;
277 op->src.offset = insn.displacement.value;
278 op->dest.type = OP_DEST_REG;
279 op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r];
285 if (sib == 0x24 && rex_w && !rex_b && !rex_x) {
288 if (!insn.displacement.value) {
289 /* lea (%rsp), reg */
290 op->src.type = OP_SRC_REG;
292 /* lea disp(%rsp), reg */
293 op->src.type = OP_SRC_ADD;
294 op->src.offset = insn.displacement.value;
296 op->src.reg = CFI_SP;
297 op->dest.type = OP_DEST_REG;
298 op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r];
300 } else if (rex == 0x48 && modrm == 0x65) {
302 /* lea disp(%rbp), %rsp */
304 op->src.type = OP_SRC_ADD;
305 op->src.reg = CFI_BP;
306 op->src.offset = insn.displacement.value;
307 op->dest.type = OP_DEST_REG;
308 op->dest.reg = CFI_SP;
310 } else if (rex == 0x49 && modrm == 0x62 &&
311 insn.displacement.value == -8) {
314 * lea -0x8(%r10), %rsp
316 * Restoring rsp back to its original value after a
320 op->src.type = OP_SRC_ADD;
321 op->src.reg = CFI_R10;
323 op->dest.type = OP_DEST_REG;
324 op->dest.reg = CFI_SP;
326 } else if (rex == 0x49 && modrm == 0x65 &&
327 insn.displacement.value == -16) {
330 * lea -0x10(%r13), %rsp
332 * Restoring rsp back to its original value after a
336 op->src.type = OP_SRC_ADD;
337 op->src.reg = CFI_R13;
338 op->src.offset = -16;
339 op->dest.type = OP_DEST_REG;
340 op->dest.reg = CFI_SP;
348 op->src.type = OP_SRC_POP;
349 op->dest.type = OP_DEST_MEM;
359 op->src.type = OP_SRC_CONST;
360 op->dest.type = OP_DEST_PUSH;
366 op->src.type = OP_SRC_POP;
367 op->dest.type = OP_DEST_MEM;
372 if (op2 >= 0x80 && op2 <= 0x8f) {
374 *type = INSN_JUMP_CONDITIONAL;
376 } else if (op2 == 0x05 || op2 == 0x07 || op2 == 0x34 ||
379 /* sysenter, sysret */
380 *type = INSN_CONTEXT_SWITCH;
382 } else if (op2 == 0x0b || op2 == 0xb9) {
387 } else if (op2 == 0x0d || op2 == 0x1f) {
392 } else if (op2 == 0xa0 || op2 == 0xa8) {
396 op->src.type = OP_SRC_CONST;
397 op->dest.type = OP_DEST_PUSH;
399 } else if (op2 == 0xa1 || op2 == 0xa9) {
403 op->src.type = OP_SRC_POP;
404 op->dest.type = OP_DEST_MEM;
418 op->dest.type = OP_DEST_LEAVE;
424 *type = INSN_JUMP_CONDITIONAL;
429 *type = INSN_JUMP_UNCONDITIONAL;
437 case 0xca: /* retf */
438 case 0xcb: /* retf */
439 case 0xcf: /* iret */
440 *type = INSN_CONTEXT_SWITCH;
448 if (modrm_reg == 2 || modrm_reg == 3)
450 *type = INSN_CALL_DYNAMIC;
452 else if (modrm_reg == 4)
454 *type = INSN_JUMP_DYNAMIC;
456 else if (modrm_reg == 5)
459 *type = INSN_CONTEXT_SWITCH;
461 else if (modrm_reg == 6) {
465 op->src.type = OP_SRC_CONST;
466 op->dest.type = OP_DEST_PUSH;
475 *immediate = insn.immediate.nbytes ? insn.immediate.value : 0;
480 void arch_initial_func_cfi_state(struct cfi_state *state)
484 for (i = 0; i < CFI_NUM_REGS; i++) {
485 state->regs[i].base = CFI_UNDEFINED;
486 state->regs[i].offset = 0;
489 /* initial CFA (call frame address) */
490 state->cfa.base = CFI_SP;
491 state->cfa.offset = 8;
493 /* initial RA (return address) */
494 state->regs[16].base = CFI_CFA;
495 state->regs[16].offset = -8;