1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Transactional memory support routines to reclaim and recheckpoint
4 * transactional process state.
6 * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation.
9 #include <asm/asm-offsets.h>
10 #include <asm/ppc_asm.h>
11 #include <asm/ppc-opcode.h>
12 #include <asm/ptrace.h>
15 #include <asm/export.h>
16 #include <asm/feature-fixups.h>
19 /* See fpu.S, this is borrowed from there */
20 #define __SAVE_32FPRS_VSRS(n,c,base) \
23 END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
24 SAVE_32FPRS(n,base); \
26 2: SAVE_32VSRS(n,c,base); \
28 #define __REST_32FPRS_VSRS(n,c,base) \
31 END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
32 REST_32FPRS(n,base); \
34 2: REST_32VSRS(n,c,base); \
37 #define __SAVE_32FPRS_VSRS(n,c,base) SAVE_32FPRS(n, base)
38 #define __REST_32FPRS_VSRS(n,c,base) REST_32FPRS(n, base)
40 #define SAVE_32FPRS_VSRS(n,c,base) \
41 __SAVE_32FPRS_VSRS(n,__REG_##c,__REG_##base)
42 #define REST_32FPRS_VSRS(n,c,base) \
43 __REST_32FPRS_VSRS(n,__REG_##c,__REG_##base)
45 /* Stack frame offsets for local variables. */
46 #define TM_FRAME_L0 TM_FRAME_SIZE-16
47 #define TM_FRAME_L1 TM_FRAME_SIZE-8
50 /* In order to access the TM SPRs, TM must be enabled. So, do so: */
60 EXPORT_SYMBOL_GPL(tm_enable);
69 EXPORT_SYMBOL_GPL(tm_disable);
73 std r0, THREAD_TM_TFHAR(r3)
75 std r0, THREAD_TM_TEXASR(r3)
77 std r0, THREAD_TM_TFIAR(r3)
80 _GLOBAL(tm_restore_sprs)
81 ld r0, THREAD_TM_TFHAR(r3)
83 ld r0, THREAD_TM_TEXASR(r3)
85 ld r0, THREAD_TM_TFIAR(r3)
89 /* Passed an 8-bit failure cause as first argument. */
93 EXPORT_SYMBOL_GPL(tm_abort);
95 /* void tm_reclaim(struct thread_struct *thread,
98 * - Performs a full reclaim. This destroys outstanding
99 * transactions and updates thread->regs.tm_ckpt_* with the
100 * original checkpointed state. Note that thread->regs is
103 * Purpose is to both abort transactions of, and preserve the state of,
104 * a transactions at a context switch. We preserve/restore both sets of process
105 * state to restore them when the thread's scheduled again. We continue in
106 * userland as though nothing happened, but when the transaction is resumed
107 * they will abort back to the checkpointed state we save out here.
109 * Call with IRQs off, stacks get all out of sync for some periods in here!
117 stdu r1, -TM_FRAME_SIZE(r1)
119 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */
121 std r3, STK_PARAM(R3)(r1)
124 /* We need to setup MSR for VSX register save instructions. */
129 ori r16, r16, MSR_EE /* IRQs hard off */
131 oris r15, r15, MSR_VEC@h
134 oris r15,r15, MSR_VSX@h
135 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
138 std r14, TM_FRAME_L0(r1)
140 /* Do sanity check on MSR to make sure we are suspended */
141 li r7, (MSR_TS_S)@higher
145 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
147 /* Stash the stack pointer away for use after reclaim */
150 /* Clear MSR RI since we are about to change r1, EE is already off. */
156 * At this point we can't take an SLB miss since we have MSR_RI
157 * off. Load only to/from the stack/paca which are in SLB bolted regions
158 * until we turn MSR RI back on.
160 * The moment we treclaim, ALL of our GPRs will switch
161 * to user register state. (FPRs, CCR etc. also!)
162 * Use an sprg and a tm_scratch in the PACA to shuffle.
164 TRECLAIM(R4) /* Cause in r4 */
166 /* ******************** GPRs ******************** */
167 /* Stash the checkpointed r13 away in the scratch SPR and get the real
173 /* Stash the checkpointed r1 away in paca tm_scratch and get the real
176 std r1, PACATMSCRATCH(r13)
179 std r11, GPR11(r1) /* Temporary stash */
182 * Move the saved user r1 to the kernel stack in case PACATMSCRATCH is
183 * clobbered by an exception once we turn on MSR_RI below.
185 ld r11, PACATMSCRATCH(r13)
189 * Store r13 away so we can free up the scratch SPR for the SLB fault
190 * handler (needed once we start accessing the thread_struct).
195 /* Reset MSR RI so we can take SLB faults again */
199 /* Store the PPR in r11 and reset to decent value */
203 /* Now get some more GPRS free */
204 std r7, GPR7(r1) /* Temporary stash */
205 std r12, GPR12(r1) /* '' '' '' */
206 ld r12, STK_PARAM(R3)(r1) /* Param 0, thread_struct * */
208 std r11, THREAD_TM_PPR(r12) /* Store PPR and free r11 */
210 addi r7, r12, PT_CKPT_REGS /* Thread's ckpt_regs */
212 /* Make r7 look like an exception frame so that we
213 * can use the neat GPRx(n) macros. r7 is NOT a pt_regs ptr!
215 subi r7, r7, STACK_FRAME_OVERHEAD
217 /* Sync the userland GPRs 2-12, 14-31 to thread->regs: */
218 SAVE_GPR(0, r7) /* user r0 */
219 SAVE_GPR(2, r7) /* user r2 */
220 SAVE_4GPRS(3, r7) /* user r3-r6 */
221 SAVE_GPR(8, r7) /* user r8 */
222 SAVE_GPR(9, r7) /* user r9 */
223 SAVE_GPR(10, r7) /* user r10 */
224 ld r3, GPR1(r1) /* user r1 */
225 ld r4, GPR7(r1) /* user r7 */
226 ld r5, GPR11(r1) /* user r11 */
227 ld r6, GPR12(r1) /* user r12 */
228 ld r8, GPR13(r1) /* user r13 */
235 SAVE_NVGPRS(r7) /* user r14-r31 */
237 /* ******************** NIP ******************** */
239 std r3, _NIP(r7) /* Returns to failhandler */
240 /* The checkpointed NIP is ignored when rescheduling/rechkpting,
241 * but is used in signal return to 'wind back' to the abort handler.
244 /* ******************** CR,LR,CCR,MSR ********** */
256 /* ******************** TAR, DSCR ********** */
260 std r3, THREAD_TM_TAR(r12)
261 std r4, THREAD_TM_DSCR(r12)
263 /* MSR and flags: We don't change CRs, and we don't need to alter
268 /* ******************** FPR/VR/VSRs ************
269 * After reclaiming, capture the checkpointed FPRs/VRs.
271 * We enabled VEC/FP/VSX in the msr above, so we can execute these
276 /* Altivec (VEC/VMX/VR)*/
277 addi r7, r3, THREAD_CKVRSTATE
278 SAVE_32VRS(0, r6, r7) /* r6 scratch, r7 transact vr state */
284 mfspr r0, SPRN_VRSAVE
285 std r0, THREAD_CKVRSAVE(r3)
287 /* Floating Point (FP) */
288 addi r7, r3, THREAD_CKFPSTATE
289 SAVE_32FPRS_VSRS(0, R6, R7) /* r6 scratch, r7 transact fp state */
291 stfd fr0,FPSTATE_FPSCR(r7)
294 /* TM regs, incl TEXASR -- these live in thread_struct. Note they've
295 * been updated by the treclaim, to explain to userland the failure
298 mfspr r0, SPRN_TEXASR
301 std r0, THREAD_TM_TEXASR(r12)
302 std r3, THREAD_TM_TFHAR(r12)
303 std r4, THREAD_TM_TFIAR(r12)
305 /* AMR is checkpointed too, but is unsupported by Linux. */
307 /* Restore original MSR/IRQ state & clear TM mode */
308 ld r14, TM_FRAME_L0(r1) /* Orig MSR */
311 rldimi r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1
316 addi r1, r1, TM_FRAME_SIZE
323 /* Load CPU's default DSCR */
324 ld r0, PACA_DSCR_DEFAULT(r13)
331 * void __tm_recheckpoint(struct thread_struct *thread)
332 * - Restore the checkpointed register state saved by tm_reclaim
333 * when we switch_to a process.
335 * Call with IRQs off, stacks get all out of sync for
336 * some periods in here!
338 _GLOBAL(__tm_recheckpoint)
344 stdu r1, -TM_FRAME_SIZE(r1)
346 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD].
347 * This is used for backing up the NVGPRs:
351 /* Load complete register state from ts_ckpt* registers */
353 addi r7, r3, PT_CKPT_REGS /* Thread's ckpt_regs */
355 /* Make r7 look like an exception frame so that we
356 * can use the neat GPRx(n) macros. r7 is now NOT a pt_regs ptr!
358 subi r7, r7, STACK_FRAME_OVERHEAD
360 /* We need to setup MSR for FP/VMX/VSX register save instructions. */
364 #ifdef CONFIG_ALTIVEC
365 oris r5, r5, MSR_VEC@h
369 oris r5,r5, MSR_VSX@h
370 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
374 #ifdef CONFIG_ALTIVEC
376 * FP and VEC registers: These are recheckpointed from
377 * thread.ckfp_state and thread.ckvr_state respectively. The
378 * thread.fp_state[] version holds the 'live' (transactional)
379 * and will be loaded subsequently by any FPUnavailable trap.
381 addi r8, r3, THREAD_CKVRSTATE
385 REST_32VRS(0, r5, r8) /* r5 scratch, r8 ptr */
386 ld r5, THREAD_CKVRSAVE(r3)
387 mtspr SPRN_VRSAVE, r5
390 addi r8, r3, THREAD_CKFPSTATE
391 lfd fr0, FPSTATE_FPSCR(r8)
393 REST_32FPRS_VSRS(0, R4, R8)
395 mtmsr r6 /* FP/Vec off again! */
399 /* ******************** CR,LR,CCR,MSR ********** */
408 /* ******************** TAR ******************** */
409 ld r4, THREAD_TM_TAR(r3)
412 /* Load up the PPR and DSCR in GPRs only at this stage */
413 ld r5, THREAD_TM_DSCR(r3)
414 ld r6, THREAD_TM_PPR(r3)
416 REST_GPR(0, r7) /* GPR0 */
417 REST_2GPRS(2, r7) /* GPR2-3 */
418 REST_GPR(4, r7) /* GPR4 */
419 REST_4GPRS(8, r7) /* GPR8-11 */
420 REST_2GPRS(12, r7) /* GPR12-13 */
422 REST_NVGPRS(r7) /* GPR14-31 */
424 /* Load up PPR and DSCR here so we don't run with user values for long
429 /* Do final sanity check on TEXASR to make sure FS is set. Do this
430 * here before we load up the userspace r1 so any bugs we hit will get
432 mfspr r5, SPRN_TEXASR
437 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
439 /* Do final sanity check on MSR to make sure we are not transactional
443 li r5, (MSR_TS_MASK)@higher
447 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
456 * Store r1 and r5 on the stack so that we can access them
457 * after we clear MSR RI.
467 /* Clear MSR RI since we are about to change r1. EE is already off */
473 * At this point we can't take an SLB miss since we have MSR_RI
474 * off. Load only to/from the stack/paca which are in SLB bolted regions
475 * until we turn MSR RI back on.
482 /* Commit register state as checkpointed state: */
487 /* Our transactional state has now changed.
489 * Now just get out of here. Transactional (current) state will be
490 * updated once restore is called on the return path in the _switch-ed
497 /* R1 is restored, so we are recoverable again. EE is still off */
503 addi r1, r1, TM_FRAME_SIZE
510 /* Load CPU's default DSCR */
511 ld r0, PACA_DSCR_DEFAULT(r13)
516 /* ****************************************************************** */