1 // SPDX-License-Identifier: GPL-2.0
3 * ti-sysc.c - Texas Instruments sysc interconnect target driver
8 #include <linux/clkdev.h>
9 #include <linux/cpu_pm.h>
10 #include <linux/delay.h>
11 #include <linux/list.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_domain.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/reset.h>
17 #include <linux/of_address.h>
18 #include <linux/of_platform.h>
19 #include <linux/slab.h>
20 #include <linux/sys_soc.h>
21 #include <linux/timekeeping.h>
22 #include <linux/iopoll.h>
24 #include <linux/platform_data/ti-sysc.h>
26 #include <dt-bindings/bus/ti-sysc.h>
28 #define DIS_ISP BIT(2)
29 #define DIS_IVA BIT(1)
30 #define DIS_SGX BIT(0)
32 #define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), }
34 #define MAX_MODULE_SOFTRESET_WAIT 10000
53 struct list_head node;
58 struct list_head node;
61 struct sysc_soc_info {
62 unsigned long general_purpose:1;
64 struct mutex list_lock; /* disabled and restored modules list lock */
65 struct list_head disabled_modules;
66 struct list_head restored_modules;
67 struct notifier_block nb;
84 static struct sysc_soc_info *sysc_soc;
85 static const char * const reg_names[] = { "rev", "sysc", "syss", };
86 static const char * const clock_names[SYSC_MAX_CLOCKS] = {
87 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
88 "opt5", "opt6", "opt7",
91 #define SYSC_IDLEMODE_MASK 3
92 #define SYSC_CLOCKACTIVITY_MASK 3
95 * struct sysc - TI sysc interconnect target module registers and capabilities
96 * @dev: struct device pointer
97 * @module_pa: physical address of the interconnect target module
98 * @module_size: size of the interconnect target module
99 * @module_va: virtual address of the interconnect target module
100 * @offsets: register offsets from module base
101 * @mdata: ti-sysc to hwmod translation data for a module
102 * @clocks: clocks used by the interconnect target module
103 * @clock_roles: clock role names for the found clocks
104 * @nr_clocks: number of clocks used by the interconnect target module
105 * @rsts: resets used by the interconnect target module
106 * @legacy_mode: configured for legacy mode if set
107 * @cap: interconnect target module capabilities
108 * @cfg: interconnect target module configuration
109 * @cookie: data used by legacy platform callbacks
110 * @name: name if available
111 * @revision: interconnect target module revision
112 * @reserved: target module is reserved and already in use
113 * @enabled: sysc runtime enabled status
114 * @needs_resume: runtime resume needed on resume from suspend
115 * @child_needs_resume: runtime resume needed for child on resume from suspend
116 * @disable_on_idle: status flag used for disabling modules with resets
117 * @idle_work: work structure used to perform delayed idle on a module
118 * @pre_reset_quirk: module specific pre-reset quirk
119 * @post_reset_quirk: module specific post-reset quirk
120 * @reset_done_quirk: module specific reset done quirk
121 * @module_enable_quirk: module specific enable quirk
122 * @module_disable_quirk: module specific disable quirk
123 * @module_unlock_quirk: module specific sysconfig unlock quirk
124 * @module_lock_quirk: module specific sysconfig lock quirk
130 void __iomem *module_va;
131 int offsets[SYSC_MAX_REGS];
132 struct ti_sysc_module_data *mdata;
134 const char **clock_roles;
136 struct reset_control *rsts;
137 const char *legacy_mode;
138 const struct sysc_capabilities *cap;
139 struct sysc_config cfg;
140 struct ti_sysc_cookie cookie;
143 unsigned int reserved:1;
144 unsigned int enabled:1;
145 unsigned int needs_resume:1;
146 unsigned int child_needs_resume:1;
147 struct delayed_work idle_work;
148 void (*pre_reset_quirk)(struct sysc *sysc);
149 void (*post_reset_quirk)(struct sysc *sysc);
150 void (*reset_done_quirk)(struct sysc *sysc);
151 void (*module_enable_quirk)(struct sysc *sysc);
152 void (*module_disable_quirk)(struct sysc *sysc);
153 void (*module_unlock_quirk)(struct sysc *sysc);
154 void (*module_lock_quirk)(struct sysc *sysc);
157 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
160 static void sysc_write(struct sysc *ddata, int offset, u32 value)
162 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
163 writew_relaxed(value & 0xffff, ddata->module_va + offset);
165 /* Only i2c revision has LO and HI register with stride of 4 */
166 if (ddata->offsets[SYSC_REVISION] >= 0 &&
167 offset == ddata->offsets[SYSC_REVISION]) {
168 u16 hi = value >> 16;
170 writew_relaxed(hi, ddata->module_va + offset + 4);
176 writel_relaxed(value, ddata->module_va + offset);
179 static u32 sysc_read(struct sysc *ddata, int offset)
181 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
184 val = readw_relaxed(ddata->module_va + offset);
186 /* Only i2c revision has LO and HI register with stride of 4 */
187 if (ddata->offsets[SYSC_REVISION] >= 0 &&
188 offset == ddata->offsets[SYSC_REVISION]) {
189 u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
197 return readl_relaxed(ddata->module_va + offset);
200 static bool sysc_opt_clks_needed(struct sysc *ddata)
202 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
205 static u32 sysc_read_revision(struct sysc *ddata)
207 int offset = ddata->offsets[SYSC_REVISION];
212 return sysc_read(ddata, offset);
215 static u32 sysc_read_sysconfig(struct sysc *ddata)
217 int offset = ddata->offsets[SYSC_SYSCONFIG];
222 return sysc_read(ddata, offset);
225 static u32 sysc_read_sysstatus(struct sysc *ddata)
227 int offset = ddata->offsets[SYSC_SYSSTATUS];
232 return sysc_read(ddata, offset);
235 static int sysc_poll_reset_sysstatus(struct sysc *ddata)
238 u32 syss_done, rstval;
240 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
243 syss_done = ddata->cfg.syss_mask;
245 if (likely(!timekeeping_suspended)) {
246 error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata,
247 rstval, (rstval & ddata->cfg.syss_mask) ==
248 syss_done, 100, MAX_MODULE_SOFTRESET_WAIT);
250 retries = MAX_MODULE_SOFTRESET_WAIT;
252 rstval = sysc_read_sysstatus(ddata);
253 if ((rstval & ddata->cfg.syss_mask) == syss_done)
255 udelay(2); /* Account for udelay flakeyness */
263 static int sysc_poll_reset_sysconfig(struct sysc *ddata)
266 u32 sysc_mask, rstval;
268 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
270 if (likely(!timekeeping_suspended)) {
271 error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata,
272 rstval, !(rstval & sysc_mask),
273 100, MAX_MODULE_SOFTRESET_WAIT);
275 retries = MAX_MODULE_SOFTRESET_WAIT;
277 rstval = sysc_read_sysconfig(ddata);
278 if (!(rstval & sysc_mask))
280 udelay(2); /* Account for udelay flakeyness */
288 /* Poll on reset status */
289 static int sysc_wait_softreset(struct sysc *ddata)
291 int syss_offset, error = 0;
293 if (ddata->cap->regbits->srst_shift < 0)
296 syss_offset = ddata->offsets[SYSC_SYSSTATUS];
298 if (syss_offset >= 0)
299 error = sysc_poll_reset_sysstatus(ddata);
300 else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS)
301 error = sysc_poll_reset_sysconfig(ddata);
306 static int sysc_add_named_clock_from_child(struct sysc *ddata,
308 const char *optfck_name)
310 struct device_node *np = ddata->dev->of_node;
311 struct device_node *child;
312 struct clk_lookup *cl;
321 /* Does the clock alias already exist? */
322 clock = of_clk_get_by_name(np, n);
323 if (!IS_ERR(clock)) {
329 child = of_get_next_available_child(np, NULL);
333 clock = devm_get_clk_from_child(ddata->dev, child, name);
335 return PTR_ERR(clock);
338 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
339 * limit for clk_get(). If cl ever needs to be freed, it should be done
340 * with clkdev_drop().
342 cl = kcalloc(1, sizeof(*cl), GFP_KERNEL);
347 cl->dev_id = dev_name(ddata->dev);
356 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
358 const char *optfck_name;
361 if (ddata->nr_clocks < SYSC_OPTFCK0)
362 index = SYSC_OPTFCK0;
364 index = ddata->nr_clocks;
369 optfck_name = clock_names[index];
371 error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
375 ddata->clock_roles[index] = optfck_name;
381 static int sysc_get_one_clock(struct sysc *ddata, const char *name)
383 int error, i, index = -ENODEV;
385 if (!strncmp(clock_names[SYSC_FCK], name, 3))
387 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
391 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
392 if (!ddata->clocks[i]) {
400 dev_err(ddata->dev, "clock %s not added\n", name);
404 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
405 if (IS_ERR(ddata->clocks[index])) {
406 dev_err(ddata->dev, "clock get error for %s: %li\n",
407 name, PTR_ERR(ddata->clocks[index]));
409 return PTR_ERR(ddata->clocks[index]);
412 error = clk_prepare(ddata->clocks[index]);
414 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
423 static int sysc_get_clocks(struct sysc *ddata)
425 struct device_node *np = ddata->dev->of_node;
426 struct property *prop;
428 int nr_fck = 0, nr_ick = 0, i, error = 0;
430 ddata->clock_roles = devm_kcalloc(ddata->dev,
432 sizeof(*ddata->clock_roles),
434 if (!ddata->clock_roles)
437 of_property_for_each_string(np, "clock-names", prop, name) {
438 if (!strncmp(clock_names[SYSC_FCK], name, 3))
440 if (!strncmp(clock_names[SYSC_ICK], name, 3))
442 ddata->clock_roles[ddata->nr_clocks] = name;
446 if (ddata->nr_clocks < 1)
449 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
450 error = sysc_init_ext_opt_clock(ddata, NULL);
455 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
456 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
461 if (nr_fck > 1 || nr_ick > 1) {
462 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
467 /* Always add a slot for main clocks fck and ick even if unused */
473 ddata->clocks = devm_kcalloc(ddata->dev,
474 ddata->nr_clocks, sizeof(*ddata->clocks),
479 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
480 const char *name = ddata->clock_roles[i];
485 error = sysc_get_one_clock(ddata, name);
493 static int sysc_enable_main_clocks(struct sysc *ddata)
501 for (i = 0; i < SYSC_OPTFCK0; i++) {
502 clock = ddata->clocks[i];
504 /* Main clocks may not have ick */
505 if (IS_ERR_OR_NULL(clock))
508 error = clk_enable(clock);
516 for (i--; i >= 0; i--) {
517 clock = ddata->clocks[i];
519 /* Main clocks may not have ick */
520 if (IS_ERR_OR_NULL(clock))
529 static void sysc_disable_main_clocks(struct sysc *ddata)
537 for (i = 0; i < SYSC_OPTFCK0; i++) {
538 clock = ddata->clocks[i];
539 if (IS_ERR_OR_NULL(clock))
546 static int sysc_enable_opt_clocks(struct sysc *ddata)
551 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
554 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
555 clock = ddata->clocks[i];
557 /* Assume no holes for opt clocks */
558 if (IS_ERR_OR_NULL(clock))
561 error = clk_enable(clock);
569 for (i--; i >= 0; i--) {
570 clock = ddata->clocks[i];
571 if (IS_ERR_OR_NULL(clock))
580 static void sysc_disable_opt_clocks(struct sysc *ddata)
585 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
588 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
589 clock = ddata->clocks[i];
591 /* Assume no holes for opt clocks */
592 if (IS_ERR_OR_NULL(clock))
599 static void sysc_clkdm_deny_idle(struct sysc *ddata)
601 struct ti_sysc_platform_data *pdata;
603 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
606 pdata = dev_get_platdata(ddata->dev);
607 if (pdata && pdata->clkdm_deny_idle)
608 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
611 static void sysc_clkdm_allow_idle(struct sysc *ddata)
613 struct ti_sysc_platform_data *pdata;
615 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
618 pdata = dev_get_platdata(ddata->dev);
619 if (pdata && pdata->clkdm_allow_idle)
620 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
624 * sysc_init_resets - init rstctrl reset line if configured
625 * @ddata: device driver data
627 * See sysc_rstctrl_reset_deassert().
629 static int sysc_init_resets(struct sysc *ddata)
632 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
634 return PTR_ERR_OR_ZERO(ddata->rsts);
638 * sysc_parse_and_check_child_range - parses module IO region from ranges
639 * @ddata: device driver data
641 * In general we only need rev, syss, and sysc registers and not the whole
642 * module range. But we do want the offsets for these registers from the
643 * module base. This allows us to check them against the legacy hwmod
644 * platform data. Let's also check the ranges are configured properly.
646 static int sysc_parse_and_check_child_range(struct sysc *ddata)
648 struct device_node *np = ddata->dev->of_node;
649 const __be32 *ranges;
650 u32 nr_addr, nr_size;
653 ranges = of_get_property(np, "ranges", &len);
655 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
660 len /= sizeof(*ranges);
663 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
668 error = of_property_read_u32(np, "#address-cells", &nr_addr);
672 error = of_property_read_u32(np, "#size-cells", &nr_size);
676 if (nr_addr != 1 || nr_size != 1) {
677 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
683 ddata->module_pa = of_translate_address(np, ranges++);
684 ddata->module_size = be32_to_cpup(ranges);
689 /* Interconnect instances to probe before l4_per instances */
690 static struct resource early_bus_ranges[] = {
692 { .start = 0x44c00000, .end = 0x44c00000 + 0x300000, },
693 /* omap4/5 and dra7 l4_cfg */
694 { .start = 0x4a000000, .end = 0x4a000000 + 0x300000, },
696 { .start = 0x4a300000, .end = 0x4a300000 + 0x30000, },
697 /* omap5 and dra7 l4_wkup without dra7 dcan segment */
698 { .start = 0x4ae00000, .end = 0x4ae00000 + 0x30000, },
701 static atomic_t sysc_defer = ATOMIC_INIT(10);
704 * sysc_defer_non_critical - defer non_critical interconnect probing
705 * @ddata: device driver data
707 * We want to probe l4_cfg and l4_wkup interconnect instances before any
708 * l4_per instances as l4_per instances depend on resources on l4_cfg and
709 * l4_wkup interconnects.
711 static int sysc_defer_non_critical(struct sysc *ddata)
713 struct resource *res;
716 if (!atomic_read(&sysc_defer))
719 for (i = 0; i < ARRAY_SIZE(early_bus_ranges); i++) {
720 res = &early_bus_ranges[i];
721 if (ddata->module_pa >= res->start &&
722 ddata->module_pa <= res->end) {
723 atomic_set(&sysc_defer, 0);
729 atomic_dec_if_positive(&sysc_defer);
731 return -EPROBE_DEFER;
734 static struct device_node *stdout_path;
736 static void sysc_init_stdout_path(struct sysc *ddata)
738 struct device_node *np = NULL;
741 if (IS_ERR(stdout_path))
747 np = of_find_node_by_path("/chosen");
751 uart = of_get_property(np, "stdout-path", NULL);
755 np = of_find_node_by_path(uart);
764 stdout_path = ERR_PTR(-ENODEV);
767 static void sysc_check_quirk_stdout(struct sysc *ddata,
768 struct device_node *np)
770 sysc_init_stdout_path(ddata);
771 if (np != stdout_path)
774 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
775 SYSC_QUIRK_NO_RESET_ON_INIT;
779 * sysc_check_one_child - check child configuration
780 * @ddata: device driver data
781 * @np: child device node
783 * Let's avoid messy situations where we have new interconnect target
784 * node but children have "ti,hwmods". These belong to the interconnect
785 * target node and are managed by this driver.
787 static void sysc_check_one_child(struct sysc *ddata,
788 struct device_node *np)
792 name = of_get_property(np, "ti,hwmods", NULL);
793 if (name && !of_device_is_compatible(np, "ti,sysc"))
794 dev_warn(ddata->dev, "really a child ti,hwmods property?");
796 sysc_check_quirk_stdout(ddata, np);
797 sysc_parse_dts_quirks(ddata, np, true);
800 static void sysc_check_children(struct sysc *ddata)
802 struct device_node *child;
804 for_each_child_of_node(ddata->dev->of_node, child)
805 sysc_check_one_child(ddata, child);
809 * So far only I2C uses 16-bit read access with clockactivity with revision
810 * in two registers with stride of 4. We can detect this based on the rev
811 * register size to configure things far enough to be able to properly read
812 * the revision register.
814 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
816 if (resource_size(res) == 8)
817 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
821 * sysc_parse_one - parses the interconnect target module registers
822 * @ddata: device driver data
823 * @reg: register to parse
825 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
827 struct resource *res;
834 name = reg_names[reg];
840 res = platform_get_resource_byname(to_platform_device(ddata->dev),
841 IORESOURCE_MEM, name);
843 ddata->offsets[reg] = -ENODEV;
848 ddata->offsets[reg] = res->start - ddata->module_pa;
849 if (reg == SYSC_REVISION)
850 sysc_check_quirk_16bit(ddata, res);
855 static int sysc_parse_registers(struct sysc *ddata)
859 for (i = 0; i < SYSC_MAX_REGS; i++) {
860 error = sysc_parse_one(ddata, i);
869 * sysc_check_registers - check for misconfigured register overlaps
870 * @ddata: device driver data
872 static int sysc_check_registers(struct sysc *ddata)
874 int i, j, nr_regs = 0, nr_matches = 0;
876 for (i = 0; i < SYSC_MAX_REGS; i++) {
877 if (ddata->offsets[i] < 0)
880 if (ddata->offsets[i] > (ddata->module_size - 4)) {
881 dev_err(ddata->dev, "register outside module range");
886 for (j = 0; j < SYSC_MAX_REGS; j++) {
887 if (ddata->offsets[j] < 0)
890 if (ddata->offsets[i] == ddata->offsets[j])
896 if (nr_matches > nr_regs) {
897 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
898 nr_regs, nr_matches);
907 * syc_ioremap - ioremap register space for the interconnect target module
908 * @ddata: device driver data
910 * Note that the interconnect target module registers can be anywhere
911 * within the interconnect target module range. For example, SGX has
912 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
913 * has them at offset 0x1200 in the CPSW_WR child. Usually the
914 * the interconnect target module registers are at the beginning of
915 * the module range though.
917 static int sysc_ioremap(struct sysc *ddata)
921 if (ddata->offsets[SYSC_REVISION] < 0 &&
922 ddata->offsets[SYSC_SYSCONFIG] < 0 &&
923 ddata->offsets[SYSC_SYSSTATUS] < 0) {
924 size = ddata->module_size;
926 size = max3(ddata->offsets[SYSC_REVISION],
927 ddata->offsets[SYSC_SYSCONFIG],
928 ddata->offsets[SYSC_SYSSTATUS]);
933 if ((size + sizeof(u32)) > ddata->module_size)
934 size = ddata->module_size;
937 ddata->module_va = devm_ioremap(ddata->dev,
940 if (!ddata->module_va)
947 * sysc_map_and_check_registers - ioremap and check device registers
948 * @ddata: device driver data
950 static int sysc_map_and_check_registers(struct sysc *ddata)
954 error = sysc_parse_and_check_child_range(ddata);
958 error = sysc_defer_non_critical(ddata);
962 sysc_check_children(ddata);
964 error = sysc_parse_registers(ddata);
968 error = sysc_ioremap(ddata);
972 error = sysc_check_registers(ddata);
980 * sysc_show_rev - read and show interconnect target module revision
981 * @bufp: buffer to print the information to
982 * @ddata: device driver data
984 static int sysc_show_rev(char *bufp, struct sysc *ddata)
988 if (ddata->offsets[SYSC_REVISION] < 0)
989 return sprintf(bufp, ":NA");
991 len = sprintf(bufp, ":%08x", ddata->revision);
996 static int sysc_show_reg(struct sysc *ddata,
997 char *bufp, enum sysc_registers reg)
999 if (ddata->offsets[reg] < 0)
1000 return sprintf(bufp, ":NA");
1002 return sprintf(bufp, ":%x", ddata->offsets[reg]);
1005 static int sysc_show_name(char *bufp, struct sysc *ddata)
1010 return sprintf(bufp, ":%s", ddata->name);
1014 * sysc_show_registers - show information about interconnect target module
1015 * @ddata: device driver data
1017 static void sysc_show_registers(struct sysc *ddata)
1023 for (i = 0; i < SYSC_MAX_REGS; i++)
1024 bufp += sysc_show_reg(ddata, bufp, i);
1026 bufp += sysc_show_rev(bufp, ddata);
1027 bufp += sysc_show_name(bufp, ddata);
1029 dev_dbg(ddata->dev, "%llx:%x%s\n",
1030 ddata->module_pa, ddata->module_size,
1035 * sysc_write_sysconfig - handle sysconfig quirks for register write
1036 * @ddata: device driver data
1037 * @value: register value
1039 static void sysc_write_sysconfig(struct sysc *ddata, u32 value)
1041 if (ddata->module_unlock_quirk)
1042 ddata->module_unlock_quirk(ddata);
1044 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value);
1046 if (ddata->module_lock_quirk)
1047 ddata->module_lock_quirk(ddata);
1050 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
1051 #define SYSC_CLOCACT_ICK 2
1053 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
1054 static int sysc_enable_module(struct device *dev)
1057 const struct sysc_regbits *regbits;
1058 u32 reg, idlemodes, best_mode;
1061 ddata = dev_get_drvdata(dev);
1064 * Some modules like DSS reset automatically on idle. Enable optional
1065 * reset clocks and wait for OCP softreset to complete.
1067 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) {
1068 error = sysc_enable_opt_clocks(ddata);
1071 "Optional clocks failed for enable: %i\n",
1077 * Some modules like i2c and hdq1w have unusable reset status unless
1078 * the module reset quirk is enabled. Skip status check on enable.
1080 if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) {
1081 error = sysc_wait_softreset(ddata);
1083 dev_warn(ddata->dev, "OCP softreset timed out\n");
1085 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET)
1086 sysc_disable_opt_clocks(ddata);
1089 * Some subsystem private interconnects, like DSS top level module,
1090 * need only the automatic OCP softreset handling with no sysconfig
1091 * register bits to configure.
1093 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1096 regbits = ddata->cap->regbits;
1097 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1100 * Set CLOCKACTIVITY, we only use it for ick. And we only configure it
1101 * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware
1102 * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag.
1104 if (regbits->clkact_shift >= 0 &&
1105 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT))
1106 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
1108 /* Set SIDLE mode */
1109 idlemodes = ddata->cfg.sidlemodes;
1110 if (!idlemodes || regbits->sidle_shift < 0)
1113 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |
1114 SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
1115 best_mode = SYSC_IDLE_NO;
1117 best_mode = fls(ddata->cfg.sidlemodes) - 1;
1118 if (best_mode > SYSC_IDLE_MASK) {
1119 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1124 if (regbits->enwkup_shift >= 0 &&
1125 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
1126 reg |= BIT(regbits->enwkup_shift);
1129 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1130 reg |= best_mode << regbits->sidle_shift;
1131 sysc_write_sysconfig(ddata, reg);
1134 /* Set MIDLE mode */
1135 idlemodes = ddata->cfg.midlemodes;
1136 if (!idlemodes || regbits->midle_shift < 0)
1139 best_mode = fls(ddata->cfg.midlemodes) - 1;
1140 if (best_mode > SYSC_IDLE_MASK) {
1141 dev_err(dev, "%s: invalid midlemode\n", __func__);
1145 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
1146 best_mode = SYSC_IDLE_NO;
1148 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1149 reg |= best_mode << regbits->midle_shift;
1150 sysc_write_sysconfig(ddata, reg);
1153 /* Autoidle bit must enabled separately if available */
1154 if (regbits->autoidle_shift >= 0 &&
1155 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
1156 reg |= 1 << regbits->autoidle_shift;
1157 sysc_write_sysconfig(ddata, reg);
1160 /* Flush posted write */
1161 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1163 if (ddata->module_enable_quirk)
1164 ddata->module_enable_quirk(ddata);
1169 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
1171 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
1172 *best_mode = SYSC_IDLE_SMART_WKUP;
1173 else if (idlemodes & BIT(SYSC_IDLE_SMART))
1174 *best_mode = SYSC_IDLE_SMART;
1175 else if (idlemodes & BIT(SYSC_IDLE_FORCE))
1176 *best_mode = SYSC_IDLE_FORCE;
1183 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
1184 static int sysc_disable_module(struct device *dev)
1187 const struct sysc_regbits *regbits;
1188 u32 reg, idlemodes, best_mode;
1191 ddata = dev_get_drvdata(dev);
1192 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1195 if (ddata->module_disable_quirk)
1196 ddata->module_disable_quirk(ddata);
1198 regbits = ddata->cap->regbits;
1199 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1201 /* Set MIDLE mode */
1202 idlemodes = ddata->cfg.midlemodes;
1203 if (!idlemodes || regbits->midle_shift < 0)
1206 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1208 dev_err(dev, "%s: invalid midlemode\n", __func__);
1212 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) ||
1213 ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY))
1214 best_mode = SYSC_IDLE_FORCE;
1216 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1217 reg |= best_mode << regbits->midle_shift;
1218 sysc_write_sysconfig(ddata, reg);
1221 /* Set SIDLE mode */
1222 idlemodes = ddata->cfg.sidlemodes;
1223 if (!idlemodes || regbits->sidle_shift < 0)
1226 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
1227 best_mode = SYSC_IDLE_FORCE;
1229 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1231 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1236 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1237 reg |= best_mode << regbits->sidle_shift;
1238 if (regbits->autoidle_shift >= 0 &&
1239 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
1240 reg |= 1 << regbits->autoidle_shift;
1241 sysc_write_sysconfig(ddata, reg);
1243 /* Flush posted write */
1244 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1249 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
1252 struct ti_sysc_platform_data *pdata;
1255 pdata = dev_get_platdata(ddata->dev);
1259 if (!pdata->idle_module)
1262 error = pdata->idle_module(dev, &ddata->cookie);
1264 dev_err(dev, "%s: could not idle: %i\n",
1267 reset_control_assert(ddata->rsts);
1272 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1275 struct ti_sysc_platform_data *pdata;
1278 pdata = dev_get_platdata(ddata->dev);
1282 if (!pdata->enable_module)
1285 error = pdata->enable_module(dev, &ddata->cookie);
1287 dev_err(dev, "%s: could not enable: %i\n",
1290 reset_control_deassert(ddata->rsts);
1295 static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1300 ddata = dev_get_drvdata(dev);
1302 if (!ddata->enabled)
1305 sysc_clkdm_deny_idle(ddata);
1307 if (ddata->legacy_mode) {
1308 error = sysc_runtime_suspend_legacy(dev, ddata);
1310 goto err_allow_idle;
1312 error = sysc_disable_module(dev);
1314 goto err_allow_idle;
1317 sysc_disable_main_clocks(ddata);
1319 if (sysc_opt_clks_needed(ddata))
1320 sysc_disable_opt_clocks(ddata);
1322 ddata->enabled = false;
1325 reset_control_assert(ddata->rsts);
1327 sysc_clkdm_allow_idle(ddata);
1332 static int __maybe_unused sysc_runtime_resume(struct device *dev)
1337 ddata = dev_get_drvdata(dev);
1343 sysc_clkdm_deny_idle(ddata);
1345 if (sysc_opt_clks_needed(ddata)) {
1346 error = sysc_enable_opt_clocks(ddata);
1348 goto err_allow_idle;
1351 error = sysc_enable_main_clocks(ddata);
1353 goto err_opt_clocks;
1355 reset_control_deassert(ddata->rsts);
1357 if (ddata->legacy_mode) {
1358 error = sysc_runtime_resume_legacy(dev, ddata);
1360 goto err_main_clocks;
1362 error = sysc_enable_module(dev);
1364 goto err_main_clocks;
1367 ddata->enabled = true;
1369 sysc_clkdm_allow_idle(ddata);
1374 sysc_disable_main_clocks(ddata);
1376 if (sysc_opt_clks_needed(ddata))
1377 sysc_disable_opt_clocks(ddata);
1379 sysc_clkdm_allow_idle(ddata);
1384 static int sysc_reinit_module(struct sysc *ddata, bool leave_enabled)
1386 struct device *dev = ddata->dev;
1389 /* Disable target module if it is enabled */
1390 if (ddata->enabled) {
1391 error = sysc_runtime_suspend(dev);
1393 dev_warn(dev, "reinit suspend failed: %i\n", error);
1396 /* Enable target module */
1397 error = sysc_runtime_resume(dev);
1399 dev_warn(dev, "reinit resume failed: %i\n", error);
1404 /* Disable target module if no leave_enabled was set */
1405 error = sysc_runtime_suspend(dev);
1407 dev_warn(dev, "reinit suspend failed: %i\n", error);
1412 static int __maybe_unused sysc_noirq_suspend(struct device *dev)
1416 ddata = dev_get_drvdata(dev);
1418 if (ddata->cfg.quirks &
1419 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
1422 if (!ddata->enabled)
1425 ddata->needs_resume = 1;
1427 return sysc_runtime_suspend(dev);
1430 static int __maybe_unused sysc_noirq_resume(struct device *dev)
1435 ddata = dev_get_drvdata(dev);
1437 if (ddata->cfg.quirks &
1438 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
1441 if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_RESUME) {
1442 error = sysc_reinit_module(ddata, ddata->needs_resume);
1444 dev_warn(dev, "noirq_resume failed: %i\n", error);
1445 } else if (ddata->needs_resume) {
1446 error = sysc_runtime_resume(dev);
1448 dev_warn(dev, "noirq_resume failed: %i\n", error);
1451 ddata->needs_resume = 0;
1456 static const struct dev_pm_ops sysc_pm_ops = {
1457 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
1458 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1459 sysc_runtime_resume,
1463 /* Module revision register based quirks */
1464 struct sysc_revision_quirk {
1475 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1476 optrev_val, optrevmask, optquirkmask) \
1478 .name = (optname), \
1479 .base = (optbase), \
1480 .rev_offset = (optrev), \
1481 .sysc_offset = (optsysc), \
1482 .syss_offset = (optsyss), \
1483 .revision = (optrev_val), \
1484 .revision_mask = (optrevmask), \
1485 .quirks = (optquirkmask), \
1488 static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1489 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
1490 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
1491 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
1492 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
1493 SYSC_QUIRK_LEGACY_IDLE),
1494 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff,
1495 SYSC_QUIRK_LEGACY_IDLE),
1496 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff,
1497 SYSC_QUIRK_LEGACY_IDLE),
1498 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
1499 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1500 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
1501 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1502 /* Uarts on omap4 and later */
1503 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
1504 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1505 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
1506 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1508 /* Quirks that need to be set based on the module address */
1509 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff,
1510 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1511 SYSC_QUIRK_SWSUP_SIDLE),
1513 /* Quirks that need to be set based on detected module */
1514 SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff,
1515 SYSC_MODULE_QUIRK_AESS),
1516 /* Errata i893 handling for dra7 dcan1 and 2 */
1517 SYSC_QUIRK("dcan", 0x4ae3c000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
1518 SYSC_QUIRK_CLKDM_NOAUTO),
1519 SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
1520 SYSC_QUIRK_CLKDM_NOAUTO),
1521 SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1522 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1523 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff,
1524 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1525 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff,
1526 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1527 SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1528 SYSC_QUIRK_CLKDM_NOAUTO),
1529 SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1530 SYSC_QUIRK_CLKDM_NOAUTO),
1531 SYSC_QUIRK("gpmc", 0, 0, 0x10, 0x14, 0x00000060, 0xffffffff,
1532 SYSC_QUIRK_GPMC_DEBUG),
1533 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff,
1534 SYSC_QUIRK_OPT_CLKS_NEEDED),
1535 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
1536 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1537 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
1538 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1539 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
1540 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1541 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
1542 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1543 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
1544 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1545 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
1546 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1547 SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0),
1548 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff,
1549 SYSC_MODULE_QUIRK_SGX),
1550 SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff,
1551 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1552 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0,
1553 SYSC_MODULE_QUIRK_RTC_UNLOCK),
1554 SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff,
1555 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1556 SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff,
1557 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1558 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff,
1559 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1560 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff,
1561 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1562 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1563 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1564 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff,
1565 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY |
1566 SYSC_QUIRK_REINIT_ON_CTX_LOST),
1567 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1568 SYSC_MODULE_QUIRK_WDT),
1569 /* PRUSS on am3, am4 and am5 */
1570 SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000,
1571 SYSC_MODULE_QUIRK_PRUSS),
1572 /* Watchdog on am3 and am4 */
1573 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1574 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
1577 SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0),
1578 SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0),
1579 SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0),
1580 SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1581 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
1583 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0),
1584 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0),
1585 SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1586 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1587 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0),
1588 SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0),
1589 SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1590 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1591 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1592 SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1593 SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0),
1594 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1595 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1596 SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0),
1597 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0),
1598 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0),
1599 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0),
1600 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1601 SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0),
1602 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff, 0),
1603 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0),
1604 SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0),
1605 SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0),
1606 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
1607 SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0),
1608 SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0),
1609 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1610 SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0),
1611 SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0),
1612 SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0),
1613 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0),
1614 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0),
1615 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0),
1616 SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1617 SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1618 SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1619 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0),
1620 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0),
1621 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0),
1622 SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0),
1623 SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0),
1624 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
1625 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
1626 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0),
1627 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0),
1628 SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0),
1629 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0),
1630 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0),
1631 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0),
1632 /* Some timers on omap4 and later */
1633 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0),
1634 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0),
1635 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0),
1636 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0),
1637 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0),
1638 SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0),
1639 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
1640 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
1641 SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0),
1642 SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0),
1647 * Early quirks based on module base and register offsets only that are
1648 * needed before the module revision can be read
1650 static void sysc_init_early_quirks(struct sysc *ddata)
1652 const struct sysc_revision_quirk *q;
1655 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1656 q = &sysc_revision_quirks[i];
1661 if (q->base != ddata->module_pa)
1664 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1667 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1670 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1673 ddata->name = q->name;
1674 ddata->cfg.quirks |= q->quirks;
1678 /* Quirks that also consider the revision register value */
1679 static void sysc_init_revision_quirks(struct sysc *ddata)
1681 const struct sysc_revision_quirk *q;
1684 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1685 q = &sysc_revision_quirks[i];
1687 if (q->base && q->base != ddata->module_pa)
1690 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1693 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1696 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1699 if (q->revision == ddata->revision ||
1700 (q->revision & q->revision_mask) ==
1701 (ddata->revision & q->revision_mask)) {
1702 ddata->name = q->name;
1703 ddata->cfg.quirks |= q->quirks;
1709 * DSS needs dispc outputs disabled to reset modules. Returns mask of
1710 * enabled DSS interrupts. Eventually we may be able to do this on
1711 * dispc init rather than top-level DSS init.
1713 static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset,
1716 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
1717 const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1);
1719 bool framedonetv_irq = true;
1720 u32 val, irq_mask = 0;
1722 switch (sysc_soc->soc) {
1723 case SOC_2420 ... SOC_3630:
1725 framedonetv_irq = false;
1727 case SOC_4430 ... SOC_4470:
1736 framedonetv_irq = false;
1743 /* Remap the whole module range to be able to reset dispc outputs */
1744 devm_iounmap(ddata->dev, ddata->module_va);
1745 ddata->module_va = devm_ioremap(ddata->dev,
1747 ddata->module_size);
1748 if (!ddata->module_va)
1752 val = sysc_read(ddata, dispc_offset + 0x40);
1753 lcd_en = val & lcd_en_mask;
1754 digit_en = val & digit_en_mask;
1756 irq_mask |= BIT(0); /* FRAMEDONE */
1758 if (framedonetv_irq)
1759 irq_mask |= BIT(24); /* FRAMEDONETV */
1761 irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */
1763 if (disable & (lcd_en | digit_en))
1764 sysc_write(ddata, dispc_offset + 0x40,
1765 val & ~(lcd_en_mask | digit_en_mask));
1767 if (manager_count <= 2)
1770 /* DISPC_CONTROL2 */
1771 val = sysc_read(ddata, dispc_offset + 0x238);
1772 lcd2_en = val & lcd_en_mask;
1774 irq_mask |= BIT(22); /* FRAMEDONE2 */
1775 if (disable && lcd2_en)
1776 sysc_write(ddata, dispc_offset + 0x238,
1777 val & ~lcd_en_mask);
1779 if (manager_count <= 3)
1782 /* DISPC_CONTROL3 */
1783 val = sysc_read(ddata, dispc_offset + 0x848);
1784 lcd3_en = val & lcd_en_mask;
1786 irq_mask |= BIT(30); /* FRAMEDONE3 */
1787 if (disable && lcd3_en)
1788 sysc_write(ddata, dispc_offset + 0x848,
1789 val & ~lcd_en_mask);
1794 /* DSS needs child outputs disabled and SDI registers cleared for reset */
1795 static void sysc_pre_reset_quirk_dss(struct sysc *ddata)
1797 const int dispc_offset = 0x1000;
1801 /* Get enabled outputs */
1802 irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false);
1806 /* Clear IRQSTATUS */
1807 sysc_write(ddata, dispc_offset + 0x18, irq_mask);
1809 /* Disable outputs */
1810 val = sysc_quirk_dispc(ddata, dispc_offset, true);
1812 /* Poll IRQSTATUS */
1813 error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18,
1814 val, val != irq_mask, 100, 50);
1816 dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n",
1817 __func__, val, irq_mask);
1819 if (sysc_soc->soc == SOC_3430) {
1820 /* Clear DSS_SDI_CONTROL */
1821 sysc_write(ddata, 0x44, 0);
1823 /* Clear DSS_PLL_CONTROL */
1824 sysc_write(ddata, 0x48, 0);
1827 /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */
1828 sysc_write(ddata, 0x40, 0);
1831 /* 1-wire needs module's internal clocks enabled for reset */
1832 static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
1834 int offset = 0x0c; /* HDQ_CTRL_STATUS */
1837 val = sysc_read(ddata, offset);
1839 sysc_write(ddata, offset, val);
1842 /* AESS (Audio Engine SubSystem) needs autogating set after enable */
1843 static void sysc_module_enable_quirk_aess(struct sysc *ddata)
1845 int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */
1847 sysc_write(ddata, offset, 1);
1850 /* I2C needs to be disabled for reset */
1851 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
1856 /* I2C_CON, omap2/3 is different from omap4 and later */
1857 if ((ddata->revision & 0xffffff00) == 0x001f0000)
1863 val = sysc_read(ddata, offset);
1868 sysc_write(ddata, offset, val);
1871 static void sysc_pre_reset_quirk_i2c(struct sysc *ddata)
1873 sysc_clk_quirk_i2c(ddata, false);
1876 static void sysc_post_reset_quirk_i2c(struct sysc *ddata)
1878 sysc_clk_quirk_i2c(ddata, true);
1881 /* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */
1882 static void sysc_quirk_rtc(struct sysc *ddata, bool lock)
1884 u32 val, kick0_val = 0, kick1_val = 0;
1885 unsigned long flags;
1889 kick0_val = 0x83e70b13;
1890 kick1_val = 0x95a4f1e0;
1893 local_irq_save(flags);
1894 /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */
1895 error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val,
1896 !(val & BIT(0)), 100, 50);
1898 dev_warn(ddata->dev, "rtc busy timeout\n");
1899 /* Now we have ~15 microseconds to read/write various registers */
1900 sysc_write(ddata, 0x6c, kick0_val);
1901 sysc_write(ddata, 0x70, kick1_val);
1902 local_irq_restore(flags);
1905 static void sysc_module_unlock_quirk_rtc(struct sysc *ddata)
1907 sysc_quirk_rtc(ddata, false);
1910 static void sysc_module_lock_quirk_rtc(struct sysc *ddata)
1912 sysc_quirk_rtc(ddata, true);
1915 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
1916 static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
1918 int offset = 0xff08; /* OCP_DEBUG_CONFIG */
1919 u32 val = BIT(31); /* THALIA_INT_BYPASS */
1921 sysc_write(ddata, offset, val);
1924 /* Watchdog timer needs a disable sequence after reset */
1925 static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
1927 int wps, spr, error;
1933 sysc_write(ddata, spr, 0xaaaa);
1934 error = readl_poll_timeout(ddata->module_va + wps, val,
1936 MAX_MODULE_SOFTRESET_WAIT);
1938 dev_warn(ddata->dev, "wdt disable step1 failed\n");
1940 sysc_write(ddata, spr, 0x5555);
1941 error = readl_poll_timeout(ddata->module_va + wps, val,
1943 MAX_MODULE_SOFTRESET_WAIT);
1945 dev_warn(ddata->dev, "wdt disable step2 failed\n");
1948 /* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */
1949 static void sysc_module_disable_quirk_pruss(struct sysc *ddata)
1953 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1954 reg |= SYSC_PRUSS_STANDBY_INIT;
1955 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
1958 static void sysc_init_module_quirks(struct sysc *ddata)
1960 if (ddata->legacy_mode || !ddata->name)
1963 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
1964 ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w;
1969 #ifdef CONFIG_OMAP_GPMC_DEBUG
1970 if (ddata->cfg.quirks & SYSC_QUIRK_GPMC_DEBUG) {
1971 ddata->cfg.quirks |= SYSC_QUIRK_NO_RESET_ON_INIT;
1977 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
1978 ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c;
1979 ddata->post_reset_quirk = sysc_post_reset_quirk_i2c;
1984 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS)
1985 ddata->module_enable_quirk = sysc_module_enable_quirk_aess;
1987 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET)
1988 ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss;
1990 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) {
1991 ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc;
1992 ddata->module_lock_quirk = sysc_module_lock_quirk_rtc;
1997 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
1998 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
2000 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
2001 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
2002 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
2005 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS)
2006 ddata->module_disable_quirk = sysc_module_disable_quirk_pruss;
2009 static int sysc_clockdomain_init(struct sysc *ddata)
2011 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2012 struct clk *fck = NULL, *ick = NULL;
2015 if (!pdata || !pdata->init_clockdomain)
2018 switch (ddata->nr_clocks) {
2020 ick = ddata->clocks[SYSC_ICK];
2023 fck = ddata->clocks[SYSC_FCK];
2029 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
2030 if (!error || error == -ENODEV)
2037 * Note that pdata->init_module() typically does a reset first. After
2038 * pdata->init_module() is done, PM runtime can be used for the interconnect
2041 static int sysc_legacy_init(struct sysc *ddata)
2043 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2046 if (!pdata || !pdata->init_module)
2049 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
2050 if (error == -EEXIST)
2057 * Note that the caller must ensure the interconnect target module is enabled
2058 * before calling reset. Otherwise reset will not complete.
2060 static int sysc_reset(struct sysc *ddata)
2062 int sysc_offset, sysc_val, error;
2065 sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
2067 if (ddata->legacy_mode ||
2068 ddata->cap->regbits->srst_shift < 0 ||
2069 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
2072 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
2074 if (ddata->pre_reset_quirk)
2075 ddata->pre_reset_quirk(ddata);
2077 if (sysc_offset >= 0) {
2078 sysc_val = sysc_read_sysconfig(ddata);
2079 sysc_val |= sysc_mask;
2080 sysc_write(ddata, sysc_offset, sysc_val);
2083 if (ddata->cfg.srst_udelay)
2084 usleep_range(ddata->cfg.srst_udelay,
2085 ddata->cfg.srst_udelay * 2);
2087 if (ddata->post_reset_quirk)
2088 ddata->post_reset_quirk(ddata);
2090 error = sysc_wait_softreset(ddata);
2092 dev_warn(ddata->dev, "OCP softreset timed out\n");
2094 if (ddata->reset_done_quirk)
2095 ddata->reset_done_quirk(ddata);
2101 * At this point the module is configured enough to read the revision but
2102 * module may not be completely configured yet to use PM runtime. Enable
2103 * all clocks directly during init to configure the quirks needed for PM
2104 * runtime based on the revision register.
2106 static int sysc_init_module(struct sysc *ddata)
2110 error = sysc_clockdomain_init(ddata);
2114 sysc_clkdm_deny_idle(ddata);
2117 * Always enable clocks. The bootloader may or may not have enabled
2118 * the related clocks.
2120 error = sysc_enable_opt_clocks(ddata);
2124 error = sysc_enable_main_clocks(ddata);
2126 goto err_opt_clocks;
2128 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
2129 error = reset_control_deassert(ddata->rsts);
2131 goto err_main_clocks;
2134 ddata->revision = sysc_read_revision(ddata);
2135 sysc_init_revision_quirks(ddata);
2136 sysc_init_module_quirks(ddata);
2138 if (ddata->legacy_mode) {
2139 error = sysc_legacy_init(ddata);
2144 if (!ddata->legacy_mode) {
2145 error = sysc_enable_module(ddata->dev);
2150 error = sysc_reset(ddata);
2152 dev_err(ddata->dev, "Reset failed with %d\n", error);
2154 if (error && !ddata->legacy_mode)
2155 sysc_disable_module(ddata->dev);
2158 if (error && !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
2159 reset_control_assert(ddata->rsts);
2163 sysc_disable_main_clocks(ddata);
2165 /* No re-enable of clockdomain autoidle to prevent module autoidle */
2167 sysc_disable_opt_clocks(ddata);
2168 sysc_clkdm_allow_idle(ddata);
2174 static int sysc_init_sysc_mask(struct sysc *ddata)
2176 struct device_node *np = ddata->dev->of_node;
2180 error = of_property_read_u32(np, "ti,sysc-mask", &val);
2184 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
2189 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
2192 struct device_node *np = ddata->dev->of_node;
2193 struct property *prop;
2197 of_property_for_each_u32(np, name, prop, p, val) {
2198 if (val >= SYSC_NR_IDLEMODES) {
2199 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
2202 *idlemodes |= (1 << val);
2208 static int sysc_init_idlemodes(struct sysc *ddata)
2212 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
2217 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
2226 * Only some devices on omap4 and later have SYSCONFIG reset done
2227 * bit. We can detect this if there is no SYSSTATUS at all, or the
2228 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
2229 * have multiple bits for the child devices like OHCI and EHCI.
2230 * Depends on SYSC being parsed first.
2232 static int sysc_init_syss_mask(struct sysc *ddata)
2234 struct device_node *np = ddata->dev->of_node;
2238 error = of_property_read_u32(np, "ti,syss-mask", &val);
2240 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
2241 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
2242 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2243 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2248 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2249 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2251 ddata->cfg.syss_mask = val;
2257 * Many child device drivers need to have fck and opt clocks available
2258 * to get the clock rate for device internal configuration etc.
2260 static int sysc_child_add_named_clock(struct sysc *ddata,
2261 struct device *child,
2265 struct clk_lookup *l;
2271 clk = clk_get(child, name);
2277 clk = clk_get(ddata->dev, name);
2281 l = clkdev_create(clk, name, dev_name(child));
2290 static int sysc_child_add_clocks(struct sysc *ddata,
2291 struct device *child)
2295 for (i = 0; i < ddata->nr_clocks; i++) {
2296 error = sysc_child_add_named_clock(ddata,
2298 ddata->clock_roles[i]);
2299 if (error && error != -EEXIST) {
2300 dev_err(ddata->dev, "could not add child clock %s: %i\n",
2301 ddata->clock_roles[i], error);
2310 static struct device_type sysc_device_type = {
2313 static struct sysc *sysc_child_to_parent(struct device *dev)
2315 struct device *parent = dev->parent;
2317 if (!parent || parent->type != &sysc_device_type)
2320 return dev_get_drvdata(parent);
2323 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
2328 ddata = sysc_child_to_parent(dev);
2330 error = pm_generic_runtime_suspend(dev);
2334 if (!ddata->enabled)
2337 return sysc_runtime_suspend(ddata->dev);
2340 static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
2345 ddata = sysc_child_to_parent(dev);
2347 if (!ddata->enabled) {
2348 error = sysc_runtime_resume(ddata->dev);
2351 "%s error: %i\n", __func__, error);
2354 return pm_generic_runtime_resume(dev);
2357 #ifdef CONFIG_PM_SLEEP
2358 static int sysc_child_suspend_noirq(struct device *dev)
2363 ddata = sysc_child_to_parent(dev);
2365 dev_dbg(ddata->dev, "%s %s\n", __func__,
2366 ddata->name ? ddata->name : "");
2368 error = pm_generic_suspend_noirq(dev);
2370 dev_err(dev, "%s error at %i: %i\n",
2371 __func__, __LINE__, error);
2376 if (!pm_runtime_status_suspended(dev)) {
2377 error = pm_generic_runtime_suspend(dev);
2379 dev_dbg(dev, "%s busy at %i: %i\n",
2380 __func__, __LINE__, error);
2385 error = sysc_runtime_suspend(ddata->dev);
2387 dev_err(dev, "%s error at %i: %i\n",
2388 __func__, __LINE__, error);
2393 ddata->child_needs_resume = true;
2399 static int sysc_child_resume_noirq(struct device *dev)
2404 ddata = sysc_child_to_parent(dev);
2406 dev_dbg(ddata->dev, "%s %s\n", __func__,
2407 ddata->name ? ddata->name : "");
2409 if (ddata->child_needs_resume) {
2410 ddata->child_needs_resume = false;
2412 error = sysc_runtime_resume(ddata->dev);
2415 "%s runtime resume error: %i\n",
2418 error = pm_generic_runtime_resume(dev);
2421 "%s generic runtime resume: %i\n",
2425 return pm_generic_resume_noirq(dev);
2429 static struct dev_pm_domain sysc_child_pm_domain = {
2431 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
2432 sysc_child_runtime_resume,
2434 USE_PLATFORM_PM_SLEEP_OPS
2435 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
2436 sysc_child_resume_noirq)
2440 /* Caller needs to take list_lock if ever used outside of cpu_pm */
2441 static void sysc_reinit_modules(struct sysc_soc_info *soc)
2443 struct sysc_module *module;
2444 struct list_head *pos;
2447 list_for_each(pos, &sysc_soc->restored_modules) {
2448 module = list_entry(pos, struct sysc_module, node);
2449 ddata = module->ddata;
2450 sysc_reinit_module(ddata, ddata->enabled);
2455 * sysc_context_notifier - optionally reset and restore module after idle
2456 * @nb: notifier block
2460 * Some interconnect target modules need to be restored, or reset and restored
2461 * on CPU_PM CPU_PM_CLUSTER_EXIT notifier. This is needed at least for am335x
2462 * OTG and GPMC target modules even if the modules are unused.
2464 static int sysc_context_notifier(struct notifier_block *nb, unsigned long cmd,
2467 struct sysc_soc_info *soc;
2469 soc = container_of(nb, struct sysc_soc_info, nb);
2472 case CPU_CLUSTER_PM_ENTER:
2474 case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */
2476 case CPU_CLUSTER_PM_EXIT:
2477 sysc_reinit_modules(soc);
2485 * sysc_add_restored - optionally add reset and restore quirk hanlling
2486 * @ddata: device data
2488 static void sysc_add_restored(struct sysc *ddata)
2490 struct sysc_module *restored_module;
2492 restored_module = kzalloc(sizeof(*restored_module), GFP_KERNEL);
2493 if (!restored_module)
2496 restored_module->ddata = ddata;
2498 mutex_lock(&sysc_soc->list_lock);
2500 list_add(&restored_module->node, &sysc_soc->restored_modules);
2502 if (sysc_soc->nb.notifier_call)
2505 sysc_soc->nb.notifier_call = sysc_context_notifier;
2506 cpu_pm_register_notifier(&sysc_soc->nb);
2509 mutex_unlock(&sysc_soc->list_lock);
2513 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
2514 * @ddata: device driver data
2515 * @child: child device driver
2517 * Allow idle for child devices as done with _od_runtime_suspend().
2518 * Otherwise many child devices will not idle because of the permanent
2519 * parent usecount set in pm_runtime_irq_safe().
2521 * Note that the long term solution is to just modify the child device
2522 * drivers to not set pm_runtime_irq_safe() and then this can be just
2525 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
2527 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
2528 dev_pm_domain_set(child, &sysc_child_pm_domain);
2531 static int sysc_notifier_call(struct notifier_block *nb,
2532 unsigned long event, void *device)
2534 struct device *dev = device;
2538 ddata = sysc_child_to_parent(dev);
2543 case BUS_NOTIFY_ADD_DEVICE:
2544 error = sysc_child_add_clocks(ddata, dev);
2547 sysc_legacy_idle_quirk(ddata, dev);
2556 static struct notifier_block sysc_nb = {
2557 .notifier_call = sysc_notifier_call,
2560 /* Device tree configured quirks */
2561 struct sysc_dts_quirk {
2566 static const struct sysc_dts_quirk sysc_dts_quirks[] = {
2567 { .name = "ti,no-idle-on-init",
2568 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
2569 { .name = "ti,no-reset-on-init",
2570 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
2571 { .name = "ti,no-idle",
2572 .mask = SYSC_QUIRK_NO_IDLE, },
2575 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
2578 const struct property *prop;
2581 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
2582 const char *name = sysc_dts_quirks[i].name;
2584 prop = of_get_property(np, name, &len);
2588 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
2590 dev_warn(ddata->dev,
2591 "dts flag should be at module level for %s\n",
2597 static int sysc_init_dts_quirks(struct sysc *ddata)
2599 struct device_node *np = ddata->dev->of_node;
2603 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
2605 sysc_parse_dts_quirks(ddata, np, false);
2606 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
2609 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
2613 ddata->cfg.srst_udelay = (u8)val;
2619 static void sysc_unprepare(struct sysc *ddata)
2626 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
2627 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
2628 clk_unprepare(ddata->clocks[i]);
2633 * Common sysc register bits found on omap2, also known as type1
2635 static const struct sysc_regbits sysc_regbits_omap2 = {
2636 .dmadisable_shift = -ENODEV,
2643 .autoidle_shift = 0,
2646 static const struct sysc_capabilities sysc_omap2 = {
2647 .type = TI_SYSC_OMAP2,
2648 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2649 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2650 SYSC_OMAP2_AUTOIDLE,
2651 .regbits = &sysc_regbits_omap2,
2654 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
2655 static const struct sysc_capabilities sysc_omap2_timer = {
2656 .type = TI_SYSC_OMAP2_TIMER,
2657 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2658 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2659 SYSC_OMAP2_AUTOIDLE,
2660 .regbits = &sysc_regbits_omap2,
2661 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
2665 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
2666 * with different sidle position
2668 static const struct sysc_regbits sysc_regbits_omap3_sham = {
2669 .dmadisable_shift = -ENODEV,
2670 .midle_shift = -ENODEV,
2672 .clkact_shift = -ENODEV,
2673 .enwkup_shift = -ENODEV,
2675 .autoidle_shift = 0,
2676 .emufree_shift = -ENODEV,
2679 static const struct sysc_capabilities sysc_omap3_sham = {
2680 .type = TI_SYSC_OMAP3_SHAM,
2681 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2682 .regbits = &sysc_regbits_omap3_sham,
2686 * AES register bits found on omap3 and later, a variant of
2687 * sysc_regbits_omap2 with different sidle position
2689 static const struct sysc_regbits sysc_regbits_omap3_aes = {
2690 .dmadisable_shift = -ENODEV,
2691 .midle_shift = -ENODEV,
2693 .clkact_shift = -ENODEV,
2694 .enwkup_shift = -ENODEV,
2696 .autoidle_shift = 0,
2697 .emufree_shift = -ENODEV,
2700 static const struct sysc_capabilities sysc_omap3_aes = {
2701 .type = TI_SYSC_OMAP3_AES,
2702 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2703 .regbits = &sysc_regbits_omap3_aes,
2707 * Common sysc register bits found on omap4, also known as type2
2709 static const struct sysc_regbits sysc_regbits_omap4 = {
2710 .dmadisable_shift = 16,
2713 .clkact_shift = -ENODEV,
2714 .enwkup_shift = -ENODEV,
2717 .autoidle_shift = -ENODEV,
2720 static const struct sysc_capabilities sysc_omap4 = {
2721 .type = TI_SYSC_OMAP4,
2722 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2723 SYSC_OMAP4_SOFTRESET,
2724 .regbits = &sysc_regbits_omap4,
2727 static const struct sysc_capabilities sysc_omap4_timer = {
2728 .type = TI_SYSC_OMAP4_TIMER,
2729 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2730 SYSC_OMAP4_SOFTRESET,
2731 .regbits = &sysc_regbits_omap4,
2735 * Common sysc register bits found on omap4, also known as type3
2737 static const struct sysc_regbits sysc_regbits_omap4_simple = {
2738 .dmadisable_shift = -ENODEV,
2741 .clkact_shift = -ENODEV,
2742 .enwkup_shift = -ENODEV,
2743 .srst_shift = -ENODEV,
2744 .emufree_shift = -ENODEV,
2745 .autoidle_shift = -ENODEV,
2748 static const struct sysc_capabilities sysc_omap4_simple = {
2749 .type = TI_SYSC_OMAP4_SIMPLE,
2750 .regbits = &sysc_regbits_omap4_simple,
2754 * SmartReflex sysc found on omap34xx
2756 static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2757 .dmadisable_shift = -ENODEV,
2758 .midle_shift = -ENODEV,
2759 .sidle_shift = -ENODEV,
2761 .enwkup_shift = -ENODEV,
2762 .srst_shift = -ENODEV,
2763 .emufree_shift = -ENODEV,
2764 .autoidle_shift = -ENODEV,
2767 static const struct sysc_capabilities sysc_34xx_sr = {
2768 .type = TI_SYSC_OMAP34XX_SR,
2769 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2770 .regbits = &sysc_regbits_omap34xx_sr,
2771 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
2772 SYSC_QUIRK_LEGACY_IDLE,
2776 * SmartReflex sysc found on omap36xx and later
2778 static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2779 .dmadisable_shift = -ENODEV,
2780 .midle_shift = -ENODEV,
2782 .clkact_shift = -ENODEV,
2784 .srst_shift = -ENODEV,
2785 .emufree_shift = -ENODEV,
2786 .autoidle_shift = -ENODEV,
2789 static const struct sysc_capabilities sysc_36xx_sr = {
2790 .type = TI_SYSC_OMAP36XX_SR,
2791 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
2792 .regbits = &sysc_regbits_omap36xx_sr,
2793 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
2796 static const struct sysc_capabilities sysc_omap4_sr = {
2797 .type = TI_SYSC_OMAP4_SR,
2798 .regbits = &sysc_regbits_omap36xx_sr,
2799 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
2803 * McASP register bits found on omap4 and later
2805 static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2806 .dmadisable_shift = -ENODEV,
2807 .midle_shift = -ENODEV,
2809 .clkact_shift = -ENODEV,
2810 .enwkup_shift = -ENODEV,
2811 .srst_shift = -ENODEV,
2812 .emufree_shift = -ENODEV,
2813 .autoidle_shift = -ENODEV,
2816 static const struct sysc_capabilities sysc_omap4_mcasp = {
2817 .type = TI_SYSC_OMAP4_MCASP,
2818 .regbits = &sysc_regbits_omap4_mcasp,
2819 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2823 * McASP found on dra7 and later
2825 static const struct sysc_capabilities sysc_dra7_mcasp = {
2826 .type = TI_SYSC_OMAP4_SIMPLE,
2827 .regbits = &sysc_regbits_omap4_simple,
2828 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2832 * FS USB host found on omap4 and later
2834 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2835 .dmadisable_shift = -ENODEV,
2836 .midle_shift = -ENODEV,
2838 .clkact_shift = -ENODEV,
2840 .srst_shift = -ENODEV,
2841 .emufree_shift = -ENODEV,
2842 .autoidle_shift = -ENODEV,
2845 static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2846 .type = TI_SYSC_OMAP4_USB_HOST_FS,
2847 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2848 .regbits = &sysc_regbits_omap4_usb_host_fs,
2851 static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2852 .dmadisable_shift = -ENODEV,
2853 .midle_shift = -ENODEV,
2854 .sidle_shift = -ENODEV,
2855 .clkact_shift = -ENODEV,
2858 .emufree_shift = -ENODEV,
2859 .autoidle_shift = -ENODEV,
2862 static const struct sysc_capabilities sysc_dra7_mcan = {
2863 .type = TI_SYSC_DRA7_MCAN,
2864 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2865 .regbits = &sysc_regbits_dra7_mcan,
2866 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
2870 * PRUSS found on some AM33xx, AM437x and AM57xx SoCs
2872 static const struct sysc_capabilities sysc_pruss = {
2873 .type = TI_SYSC_PRUSS,
2874 .sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT,
2875 .regbits = &sysc_regbits_omap4_simple,
2876 .mod_quirks = SYSC_MODULE_QUIRK_PRUSS,
2879 static int sysc_init_pdata(struct sysc *ddata)
2881 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2882 struct ti_sysc_module_data *mdata;
2887 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2891 if (ddata->legacy_mode) {
2892 mdata->name = ddata->legacy_mode;
2893 mdata->module_pa = ddata->module_pa;
2894 mdata->module_size = ddata->module_size;
2895 mdata->offsets = ddata->offsets;
2896 mdata->nr_offsets = SYSC_MAX_REGS;
2897 mdata->cap = ddata->cap;
2898 mdata->cfg = &ddata->cfg;
2901 ddata->mdata = mdata;
2906 static int sysc_init_match(struct sysc *ddata)
2908 const struct sysc_capabilities *cap;
2910 cap = of_device_get_match_data(ddata->dev);
2916 ddata->cfg.quirks |= ddata->cap->mod_quirks;
2921 static void ti_sysc_idle(struct work_struct *work)
2925 ddata = container_of(work, struct sysc, idle_work.work);
2928 * One time decrement of clock usage counts if left on from init.
2929 * Note that we disable opt clocks unconditionally in this case
2930 * as they are enabled unconditionally during init without
2931 * considering sysc_opt_clks_needed() at that point.
2933 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2934 SYSC_QUIRK_NO_IDLE_ON_INIT)) {
2935 sysc_disable_main_clocks(ddata);
2936 sysc_disable_opt_clocks(ddata);
2937 sysc_clkdm_allow_idle(ddata);
2940 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */
2941 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
2945 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT
2946 * and SYSC_QUIRK_NO_RESET_ON_INIT
2948 if (pm_runtime_active(ddata->dev))
2949 pm_runtime_put_sync(ddata->dev);
2953 * SoC model and features detection. Only needed for SoCs that need
2954 * special handling for quirks, no need to list others.
2956 static const struct soc_device_attribute sysc_soc_match[] = {
2957 SOC_FLAG("OMAP242*", SOC_2420),
2958 SOC_FLAG("OMAP243*", SOC_2430),
2959 SOC_FLAG("OMAP3[45]*", SOC_3430),
2960 SOC_FLAG("OMAP3[67]*", SOC_3630),
2961 SOC_FLAG("OMAP443*", SOC_4430),
2962 SOC_FLAG("OMAP446*", SOC_4460),
2963 SOC_FLAG("OMAP447*", SOC_4470),
2964 SOC_FLAG("OMAP54*", SOC_5430),
2965 SOC_FLAG("AM433", SOC_AM3),
2966 SOC_FLAG("AM43*", SOC_AM4),
2967 SOC_FLAG("DRA7*", SOC_DRA7),
2973 * List of SoCs variants with disabled features. By default we assume all
2974 * devices in the device tree are available so no need to list those SoCs.
2976 static const struct soc_device_attribute sysc_soc_feat_match[] = {
2977 /* OMAP3430/3530 and AM3517 variants with some accelerators disabled */
2978 SOC_FLAG("AM3505", DIS_SGX),
2979 SOC_FLAG("OMAP3525", DIS_SGX),
2980 SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX),
2981 SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX),
2983 /* OMAP3630/DM3730 variants with some accelerators disabled */
2984 SOC_FLAG("AM3703", DIS_IVA | DIS_SGX),
2985 SOC_FLAG("DM3725", DIS_SGX),
2986 SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX),
2987 SOC_FLAG("OMAP3615/AM3715", DIS_IVA),
2988 SOC_FLAG("OMAP3621", DIS_ISP),
2993 static int sysc_add_disabled(unsigned long base)
2995 struct sysc_address *disabled_module;
2997 disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL);
2998 if (!disabled_module)
3001 disabled_module->base = base;
3003 mutex_lock(&sysc_soc->list_lock);
3004 list_add(&disabled_module->node, &sysc_soc->disabled_modules);
3005 mutex_unlock(&sysc_soc->list_lock);
3011 * One time init to detect the booted SoC, disable unavailable features
3012 * and initialize list for optional cpu_pm notifier.
3014 * Note that we initialize static data shared across all ti-sysc instances
3015 * so ddata is only used for SoC type. This can be called from module_init
3016 * once we no longer need to rely on platform data.
3018 static int sysc_init_static_data(struct sysc *ddata)
3020 const struct soc_device_attribute *match;
3021 struct ti_sysc_platform_data *pdata;
3022 unsigned long features = 0;
3027 sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL);
3031 mutex_init(&sysc_soc->list_lock);
3032 INIT_LIST_HEAD(&sysc_soc->disabled_modules);
3033 INIT_LIST_HEAD(&sysc_soc->restored_modules);
3034 sysc_soc->general_purpose = true;
3036 pdata = dev_get_platdata(ddata->dev);
3037 if (pdata && pdata->soc_type_gp)
3038 sysc_soc->general_purpose = pdata->soc_type_gp();
3040 match = soc_device_match(sysc_soc_match);
3041 if (match && match->data)
3042 sysc_soc->soc = (int)match->data;
3044 /* Ignore devices that are not available on HS and EMU SoCs */
3045 if (!sysc_soc->general_purpose) {
3046 switch (sysc_soc->soc) {
3047 case SOC_3430 ... SOC_3630:
3048 sysc_add_disabled(0x48304000); /* timer12 */
3051 sysc_add_disabled(0x48310000); /* rng */
3058 match = soc_device_match(sysc_soc_feat_match);
3063 features = (unsigned long)match->data;
3066 * Add disabled devices to the list based on the module base.
3067 * Note that this must be done before we attempt to access the
3068 * device and have module revision checks working.
3070 if (features & DIS_ISP)
3071 sysc_add_disabled(0x480bd400);
3072 if (features & DIS_IVA)
3073 sysc_add_disabled(0x5d000000);
3074 if (features & DIS_SGX)
3075 sysc_add_disabled(0x50000000);
3080 static void sysc_cleanup_static_data(void)
3082 struct sysc_module *restored_module;
3083 struct sysc_address *disabled_module;
3084 struct list_head *pos, *tmp;
3089 if (sysc_soc->nb.notifier_call)
3090 cpu_pm_unregister_notifier(&sysc_soc->nb);
3092 mutex_lock(&sysc_soc->list_lock);
3093 list_for_each_safe(pos, tmp, &sysc_soc->restored_modules) {
3094 restored_module = list_entry(pos, struct sysc_module, node);
3096 kfree(restored_module);
3098 list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) {
3099 disabled_module = list_entry(pos, struct sysc_address, node);
3101 kfree(disabled_module);
3103 mutex_unlock(&sysc_soc->list_lock);
3106 static int sysc_check_disabled_devices(struct sysc *ddata)
3108 struct sysc_address *disabled_module;
3109 struct list_head *pos;
3112 mutex_lock(&sysc_soc->list_lock);
3113 list_for_each(pos, &sysc_soc->disabled_modules) {
3114 disabled_module = list_entry(pos, struct sysc_address, node);
3115 if (ddata->module_pa == disabled_module->base) {
3116 dev_dbg(ddata->dev, "module disabled for this SoC\n");
3121 mutex_unlock(&sysc_soc->list_lock);
3127 * Ignore timers tagged with no-reset and no-idle. These are likely in use,
3128 * for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks
3129 * are needed, we could also look at the timer register configuration.
3131 static int sysc_check_active_timer(struct sysc *ddata)
3135 if (ddata->cap->type != TI_SYSC_OMAP2_TIMER &&
3136 ddata->cap->type != TI_SYSC_OMAP4_TIMER)
3140 * Quirk for omap3 beagleboard revision A to B4 to use gpt12.
3141 * Revision C and later are fixed with commit 23885389dbbb ("ARM:
3142 * dts: Fix timer regression for beagleboard revision c"). This all
3143 * can be dropped if we stop supporting old beagleboard revisions
3144 * A to B4 at some point.
3146 if (sysc_soc->soc == SOC_3430)
3151 if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) &&
3152 (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE))
3158 static const struct of_device_id sysc_match_table[] = {
3159 { .compatible = "simple-bus", },
3163 static int sysc_probe(struct platform_device *pdev)
3165 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
3169 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
3173 ddata->dev = &pdev->dev;
3174 platform_set_drvdata(pdev, ddata);
3176 error = sysc_init_static_data(ddata);
3180 error = sysc_init_match(ddata);
3184 error = sysc_init_dts_quirks(ddata);
3188 error = sysc_map_and_check_registers(ddata);
3192 error = sysc_init_sysc_mask(ddata);
3196 error = sysc_init_idlemodes(ddata);
3200 error = sysc_init_syss_mask(ddata);
3204 error = sysc_init_pdata(ddata);
3208 sysc_init_early_quirks(ddata);
3210 error = sysc_check_disabled_devices(ddata);
3214 error = sysc_check_active_timer(ddata);
3215 if (error == -ENXIO)
3216 ddata->reserved = true;
3220 error = sysc_get_clocks(ddata);
3224 error = sysc_init_resets(ddata);
3228 error = sysc_init_module(ddata);
3232 pm_runtime_enable(ddata->dev);
3233 error = pm_runtime_get_sync(ddata->dev);
3235 pm_runtime_put_noidle(ddata->dev);
3236 pm_runtime_disable(ddata->dev);
3240 /* Balance use counts as PM runtime should have enabled these all */
3241 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
3242 reset_control_assert(ddata->rsts);
3244 if (!(ddata->cfg.quirks &
3245 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) {
3246 sysc_disable_main_clocks(ddata);
3247 sysc_disable_opt_clocks(ddata);
3248 sysc_clkdm_allow_idle(ddata);
3251 sysc_show_registers(ddata);
3253 ddata->dev->type = &sysc_device_type;
3255 if (!ddata->reserved) {
3256 error = of_platform_populate(ddata->dev->of_node,
3258 pdata ? pdata->auxdata : NULL,
3264 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
3266 /* At least earlycon won't survive without deferred idle */
3267 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
3268 SYSC_QUIRK_NO_IDLE_ON_INIT |
3269 SYSC_QUIRK_NO_RESET_ON_INIT)) {
3270 schedule_delayed_work(&ddata->idle_work, 3000);
3272 pm_runtime_put(&pdev->dev);
3275 if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_CTX_LOST)
3276 sysc_add_restored(ddata);
3281 pm_runtime_put_sync(&pdev->dev);
3282 pm_runtime_disable(&pdev->dev);
3284 sysc_unprepare(ddata);
3289 static int sysc_remove(struct platform_device *pdev)
3291 struct sysc *ddata = platform_get_drvdata(pdev);
3294 /* Device can still be enabled, see deferred idle quirk in probe */
3295 if (cancel_delayed_work_sync(&ddata->idle_work))
3296 ti_sysc_idle(&ddata->idle_work.work);
3298 error = pm_runtime_get_sync(ddata->dev);
3300 pm_runtime_put_noidle(ddata->dev);
3301 pm_runtime_disable(ddata->dev);
3305 of_platform_depopulate(&pdev->dev);
3307 pm_runtime_put_sync(&pdev->dev);
3308 pm_runtime_disable(&pdev->dev);
3310 if (!reset_control_status(ddata->rsts))
3311 reset_control_assert(ddata->rsts);
3314 sysc_unprepare(ddata);
3319 static const struct of_device_id sysc_match[] = {
3320 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
3321 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
3322 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
3323 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
3324 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
3325 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
3326 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
3327 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
3328 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
3329 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
3330 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
3331 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
3332 { .compatible = "ti,sysc-usb-host-fs",
3333 .data = &sysc_omap4_usb_host_fs, },
3334 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
3335 { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, },
3338 MODULE_DEVICE_TABLE(of, sysc_match);
3340 static struct platform_driver sysc_driver = {
3341 .probe = sysc_probe,
3342 .remove = sysc_remove,
3345 .of_match_table = sysc_match,
3350 static int __init sysc_init(void)
3352 bus_register_notifier(&platform_bus_type, &sysc_nb);
3354 return platform_driver_register(&sysc_driver);
3356 module_init(sysc_init);
3358 static void __exit sysc_exit(void)
3360 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
3361 platform_driver_unregister(&sysc_driver);
3362 sysc_cleanup_static_data();
3364 module_exit(sysc_exit);
3366 MODULE_DESCRIPTION("TI sysc interconnect target driver");
3367 MODULE_LICENSE("GPL v2");