ti/pm33xx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * AM33XX Power Management Routines
   4  *
   5  * Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
   6  *      Vaibhav Bedia, Dave Gerlach
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/cpu.h>
  11 #include <linux/err.h>
  12 #include <linux/genalloc.h>
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/io.h>
  16 #include <linux/module.h>
  17 #include <linux/nvmem-consumer.h>
  18 #include <linux/of.h>
  19 #include <linux/of_address.h>
  20 #include <linux/platform_data/pm33xx.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/rtc.h>
  24 #include <linux/rtc/rtc-omap.h>
  25 #include <linux/sizes.h>
  26 #include <linux/sram.h>
  27 #include <linux/suspend.h>
  28 #include <linux/ti-emif-sram.h>
  29 #include <linux/wkup_m3_ipc.h>
  30
  31 #include <asm/proc-fns.h>
  32 #include <asm/suspend.h>
  33 #include <asm/system_misc.h>
  34
  35 #define AMX3_PM_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \
  36                                          (unsigned long)pm_sram->do_wfi)
  37
  38 #define RTC_SCRATCH_RESUME_REG  0
  39 #define RTC_SCRATCH_MAGIC_REG   1
  40 #define RTC_REG_BOOT_MAGIC      0x8cd0 /* RTC */
  41 #define GIC_INT_SET_PENDING_BASE 0x200
  42 #define AM43XX_GIC_DIST_BASE    0x48241000
  43
  44 static void __iomem *rtc_base_virt;
  45 static struct clk *rtc_fck;
  46 static u32 rtc_magic_val;
  47
  48 static int (*am33xx_do_wfi_sram)(unsigned long unused);
  49 static phys_addr_t am33xx_do_wfi_sram_phys;
  50
  51 static struct gen_pool *sram_pool, *sram_pool_data;
  52 static unsigned long ocmcram_location, ocmcram_location_data;
  53
  54 static struct rtc_device *omap_rtc;
  55 static void __iomem *gic_dist_base;
  56
  57 static struct am33xx_pm_platform_data *pm_ops;
  58 static struct am33xx_pm_sram_addr *pm_sram;
  59
  60 static struct device *pm33xx_dev;
  61 static struct wkup_m3_ipc *m3_ipc;
  62
  63 #ifdef CONFIG_SUSPEND
  64 static int rtc_only_idle;
  65 static int retrigger_irq;
  66 static unsigned long suspend_wfi_flags;
  67
  68 static struct wkup_m3_wakeup_src wakeup_src = {.irq_nr = 0,
  69         .src = "Unknown",
  70 };
  71
  72 static struct wkup_m3_wakeup_src rtc_alarm_wakeup = {
  73         .irq_nr = 108, .src = "RTC Alarm",
  74 };
  75
  76 static struct wkup_m3_wakeup_src rtc_ext_wakeup = {
  77         .irq_nr = 0, .src = "Ext wakeup",
  78 };
  79 #endif
  80
  81 static u32 sram_suspend_address(unsigned long addr)
  82 {
  83         return ((unsigned long)am33xx_do_wfi_sram +
  84                 AMX3_PM_SRAM_SYMBOL_OFFSET(addr));
  85 }
  86
  87 static int am33xx_push_sram_idle(void)
  88 {
  89         struct am33xx_pm_ro_sram_data ro_sram_data;
  90         int ret;
  91         u32 table_addr, ro_data_addr;
  92         void *copy_addr;
  93
  94         ro_sram_data.amx3_pm_sram_data_virt = ocmcram_location_data;
  95         ro_sram_data.amx3_pm_sram_data_phys =
  96                 gen_pool_virt_to_phys(sram_pool_data, ocmcram_location_data);
  97         ro_sram_data.rtc_base_virt = rtc_base_virt;
  98
  99         /* Save physical address to calculate resume offset during pm init */
 100         am33xx_do_wfi_sram_phys = gen_pool_virt_to_phys(sram_pool,
 101                                                         ocmcram_location);
 102
 103         am33xx_do_wfi_sram = sram_exec_copy(sram_pool, (void *)ocmcram_location,
 104                                             pm_sram->do_wfi,
 105                                             *pm_sram->do_wfi_sz);
 106         if (!am33xx_do_wfi_sram) {
 107                 dev_err(pm33xx_dev,
 108                         "PM: %s: am33xx_do_wfi copy to sram failed\n",
 109                         __func__);
 110                 return -ENODEV;
 111         }
 112
 113         table_addr =
 114                 sram_suspend_address((unsigned long)pm_sram->emif_sram_table);
 115         ret = ti_emif_copy_pm_function_table(sram_pool, (void *)table_addr);
 116         if (ret) {
 117                 dev_dbg(pm33xx_dev,
 118                         "PM: %s: EMIF function copy failed\n", __func__);
 119                 return -EPROBE_DEFER;
 120         }
 121
 122         ro_data_addr =
 123                 sram_suspend_address((unsigned long)pm_sram->ro_sram_data);
 124         copy_addr = sram_exec_copy(sram_pool, (void *)ro_data_addr,
 125                                    &ro_sram_data,
 126                                    sizeof(ro_sram_data));
 127         if (!copy_addr) {
 128                 dev_err(pm33xx_dev,
 129                         "PM: %s: ro_sram_data copy to sram failed\n",
 130                         __func__);
 131                 return -ENODEV;
 132         }
 133
 134         return 0;
 135 }
 136
 137 static int am33xx_do_sram_idle(u32 wfi_flags)
 138 {
 139         int ret = 0;
 140
 141         if (!m3_ipc || !pm_ops)
 142                 return 0;
 143
 144         if (wfi_flags & WFI_FLAG_WAKE_M3)
 145                 ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_IDLE);
 146
 147         return pm_ops->cpu_suspend(am33xx_do_wfi_sram, wfi_flags);
 148 }
 149
 150 static int __init am43xx_map_gic(void)
 151 {
 152         gic_dist_base = ioremap(AM43XX_GIC_DIST_BASE, SZ_4K);
 153
 154         if (!gic_dist_base)
 155                 return -ENOMEM;
 156
 157         return 0;
 158 }
 159
 160 #ifdef CONFIG_SUSPEND
 161 static struct wkup_m3_wakeup_src rtc_wake_src(void)
 162 {
 163         u32 i;
 164
 165         i = __raw_readl(rtc_base_virt + 0x44) & 0x40;
 166
 167         if (i) {
 168                 retrigger_irq = rtc_alarm_wakeup.irq_nr;
 169                 return rtc_alarm_wakeup;
 170         }
 171
 172         retrigger_irq = rtc_ext_wakeup.irq_nr;
 173
 174         return rtc_ext_wakeup;
 175 }
 176
 177 static int am33xx_rtc_only_idle(unsigned long wfi_flags)
 178 {
 179         omap_rtc_power_off_program(&omap_rtc->dev);
 180         am33xx_do_wfi_sram(wfi_flags);
 181         return 0;
 182 }
 183
 184 /*
 185  * Note that the RTC module clock must be re-enabled only for rtc+ddr suspend.
 186  * And looks like the module can stay in SYSC_IDLE_SMART_WKUP mode configured
 187  * by the interconnect code just fine for both rtc+ddr suspend and retention
 188  * suspend.
 189  */
 190 static int am33xx_pm_suspend(suspend_state_t suspend_state)
 191 {
 192         int i, ret = 0;
 193
 194         if (suspend_state == PM_SUSPEND_MEM &&
 195             pm_ops->check_off_mode_enable()) {
 196                 ret = clk_prepare_enable(rtc_fck);
 197                 if (ret) {
 198                         dev_err(pm33xx_dev, "Failed to enable clock: %i\n", ret);
 199                         return ret;
 200                 }
 201
 202                 pm_ops->save_context();
 203                 suspend_wfi_flags |= WFI_FLAG_RTC_ONLY;
 204                 clk_save_context();
 205                 ret = pm_ops->soc_suspend(suspend_state, am33xx_rtc_only_idle,
 206                                           suspend_wfi_flags);
 207
 208                 suspend_wfi_flags &= ~WFI_FLAG_RTC_ONLY;
 209                 dev_info(pm33xx_dev, "Entering RTC Only mode with DDR in self-refresh\n");
 210
 211                 if (!ret) {
 212                         clk_restore_context();
 213                         pm_ops->restore_context();
 214                         m3_ipc->ops->set_rtc_only(m3_ipc);
 215                         am33xx_push_sram_idle();
 216                 }
 217         } else {
 218                 ret = pm_ops->soc_suspend(suspend_state, am33xx_do_wfi_sram,
 219                                           suspend_wfi_flags);
 220         }
 221
 222         if (ret) {
 223                 dev_err(pm33xx_dev, "PM: Kernel suspend failure\n");
 224         } else {
 225                 i = m3_ipc->ops->request_pm_status(m3_ipc);
 226
 227                 switch (i) {
 228                 case 0:
 229                         dev_info(pm33xx_dev,
 230                                  "PM: Successfully put all powerdomains to target state\n");
 231                         break;
 232                 case 1:
 233                         dev_err(pm33xx_dev,
 234                                 "PM: Could not transition all powerdomains to target state\n");
 235                         ret = -1;
 236                         break;
 237                 default:
 238                         dev_err(pm33xx_dev,
 239                                 "PM: CM3 returned unknown result = %d\n", i);
 240                         ret = -1;
 241                 }
 242
 243                 /* print the wakeup reason */
 244                 if (rtc_only_idle) {
 245                         wakeup_src = rtc_wake_src();
 246                         pr_info("PM: Wakeup source %s\n", wakeup_src.src);
 247                 } else {
 248                         pr_info("PM: Wakeup source %s\n",
 249                                 m3_ipc->ops->request_wake_src(m3_ipc));
 250                 }
 251         }
 252
 253         if (suspend_state == PM_SUSPEND_MEM && pm_ops->check_off_mode_enable())
 254                 clk_disable_unprepare(rtc_fck);
 255
 256         return ret;
 257 }
 258
 259 static int am33xx_pm_enter(suspend_state_t suspend_state)
 260 {
 261         int ret = 0;
 262
 263         switch (suspend_state) {
 264         case PM_SUSPEND_MEM:
 265         case PM_SUSPEND_STANDBY:
 266                 ret = am33xx_pm_suspend(suspend_state);
 267                 break;
 268         default:
 269                 ret = -EINVAL;
 270         }
 271
 272         return ret;
 273 }
 274
 275 static int am33xx_pm_begin(suspend_state_t state)
 276 {
 277         int ret = -EINVAL;
 278         struct nvmem_device *nvmem;
 279
 280         if (state == PM_SUSPEND_MEM && pm_ops->check_off_mode_enable()) {
 281                 nvmem = devm_nvmem_device_get(&omap_rtc->dev,
 282                                               "omap_rtc_scratch0");
 283                 if (!IS_ERR(nvmem))
 284                         nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 4,
 285                                            (void *)&rtc_magic_val);
 286                 rtc_only_idle = 1;
 287         } else {
 288                 rtc_only_idle = 0;
 289         }
 290
 291         pm_ops->begin_suspend();
 292
 293         switch (state) {
 294         case PM_SUSPEND_MEM:
 295                 ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_DEEPSLEEP);
 296                 break;
 297         case PM_SUSPEND_STANDBY:
 298                 ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_STANDBY);
 299                 break;
 300         }
 301
 302         return ret;
 303 }
 304
 305 static void am33xx_pm_end(void)
 306 {
 307         u32 val = 0;
 308         struct nvmem_device *nvmem;
 309
 310         nvmem = devm_nvmem_device_get(&omap_rtc->dev, "omap_rtc_scratch0");
 311         if (IS_ERR(nvmem))
 312                 return;
 313
 314         m3_ipc->ops->finish_low_power(m3_ipc);
 315         if (rtc_only_idle) {
 316                 if (retrigger_irq) {
 317                         /*
 318                          * 32 bits of Interrupt Set-Pending correspond to 32
 319                          * 32 interrupts. Compute the bit offset of the
 320                          * Interrupt and set that particular bit
 321                          * Compute the register offset by dividing interrupt
 322                          * number by 32 and mutiplying by 4
 323                          */
 324                         writel_relaxed(1 << (retrigger_irq & 31),
 325                                        gic_dist_base + GIC_INT_SET_PENDING_BASE
 326                                        + retrigger_irq / 32 * 4);
 327                 }
 328
 329                 nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 4,
 330                                    (void *)&val);
 331         }
 332
 333         rtc_only_idle = 0;
 334
 335         pm_ops->finish_suspend();
 336 }
 337
 338 static int am33xx_pm_valid(suspend_state_t state)
 339 {
 340         switch (state) {
 341         case PM_SUSPEND_STANDBY:
 342         case PM_SUSPEND_MEM:
 343                 return 1;
 344         default:
 345                 return 0;
 346         }
 347 }
 348
 349 static const struct platform_suspend_ops am33xx_pm_ops = {
 350         .begin          = am33xx_pm_begin,
 351         .end            = am33xx_pm_end,
 352         .enter          = am33xx_pm_enter,
 353         .valid          = am33xx_pm_valid,
 354 };
 355 #endif /* CONFIG_SUSPEND */
 356
 357 static void am33xx_pm_set_ipc_ops(void)
 358 {
 359         u32 resume_address;
 360         int temp;
 361
 362         temp = ti_emif_get_mem_type();
 363         if (temp < 0) {
 364                 dev_err(pm33xx_dev, "PM: Cannot determine memory type, no PM available\n");
 365                 return;
 366         }
 367         m3_ipc->ops->set_mem_type(m3_ipc, temp);
 368
 369         /* Physical resume address to be used by ROM code */
 370         resume_address = am33xx_do_wfi_sram_phys +
 371                          *pm_sram->resume_offset + 0x4;
 372
 373         m3_ipc->ops->set_resume_address(m3_ipc, (void *)resume_address);
 374 }
 375
 376 static void am33xx_pm_free_sram(void)
 377 {
 378         gen_pool_free(sram_pool, ocmcram_location, *pm_sram->do_wfi_sz);
 379         gen_pool_free(sram_pool_data, ocmcram_location_data,
 380                       sizeof(struct am33xx_pm_ro_sram_data));
 381 }
 382
 383 /*
 384  * Push the minimal suspend-resume code to SRAM
 385  */
 386 static int am33xx_pm_alloc_sram(void)
 387 {
 388         struct device_node *np;
 389         int ret = 0;
 390
 391         np = of_find_compatible_node(NULL, NULL, "ti,omap3-mpu");
 392         if (!np) {
 393                 np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
 394                 if (!np) {
 395                         dev_err(pm33xx_dev, "PM: %s: Unable to find device node for mpu\n",
 396                                 __func__);
 397                         return -ENODEV;
 398                 }
 399         }
 400
 401         sram_pool = of_gen_pool_get(np, "pm-sram", 0);
 402         if (!sram_pool) {
 403                 dev_err(pm33xx_dev, "PM: %s: Unable to get sram pool for ocmcram\n",
 404                         __func__);
 405                 ret = -ENODEV;
 406                 goto mpu_put_node;
 407         }
 408
 409         sram_pool_data = of_gen_pool_get(np, "pm-sram", 1);
 410         if (!sram_pool_data) {
 411                 dev_err(pm33xx_dev, "PM: %s: Unable to get sram data pool for ocmcram\n",
 412                         __func__);
 413                 ret = -ENODEV;
 414                 goto mpu_put_node;
 415         }
 416
 417         ocmcram_location = gen_pool_alloc(sram_pool, *pm_sram->do_wfi_sz);
 418         if (!ocmcram_location) {
 419                 dev_err(pm33xx_dev, "PM: %s: Unable to allocate memory from ocmcram\n",
 420                         __func__);
 421                 ret = -ENOMEM;
 422                 goto mpu_put_node;
 423         }
 424
 425         ocmcram_location_data = gen_pool_alloc(sram_pool_data,
 426                                                sizeof(struct emif_regs_amx3));
 427         if (!ocmcram_location_data) {
 428                 dev_err(pm33xx_dev, "PM: Unable to allocate memory from ocmcram\n");
 429                 gen_pool_free(sram_pool, ocmcram_location, *pm_sram->do_wfi_sz);
 430                 ret = -ENOMEM;
 431         }
 432
 433 mpu_put_node:
 434         of_node_put(np);
 435         return ret;
 436 }
 437
 438 static int am33xx_pm_rtc_setup(void)
 439 {
 440         struct device_node *np;
 441         unsigned long val = 0;
 442         struct nvmem_device *nvmem;
 443         int error;
 444
 445         np = of_find_node_by_name(NULL, "rtc");
 446
 447         if (of_device_is_available(np)) {
 448                 /* RTC interconnect target module clock */
 449                 rtc_fck = of_clk_get_by_name(np->parent, "fck");
 450                 if (IS_ERR(rtc_fck))
 451                         return PTR_ERR(rtc_fck);
 452
 453                 rtc_base_virt = of_iomap(np, 0);
 454                 if (!rtc_base_virt) {
 455                         pr_warn("PM: could not iomap rtc");
 456                         error = -ENODEV;
 457                         goto err_clk_put;
 458                 }
 459
 460                 omap_rtc = rtc_class_open("rtc0");
 461                 if (!omap_rtc) {
 462                         pr_warn("PM: rtc0 not available");
 463                         error = -EPROBE_DEFER;
 464                         goto err_iounmap;
 465                 }
 466
 467                 nvmem = devm_nvmem_device_get(&omap_rtc->dev,
 468                                               "omap_rtc_scratch0");
 469                 if (!IS_ERR(nvmem)) {
 470                         nvmem_device_read(nvmem, RTC_SCRATCH_MAGIC_REG * 4,
 471                                           4, (void *)&rtc_magic_val);
 472                         if ((rtc_magic_val & 0xffff) != RTC_REG_BOOT_MAGIC)
 473                                 pr_warn("PM: bootloader does not support rtc-only!\n");
 474
 475                         nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4,
 476                                            4, (void *)&val);
 477                         val = pm_sram->resume_address;
 478                         nvmem_device_write(nvmem, RTC_SCRATCH_RESUME_REG * 4,
 479                                            4, (void *)&val);
 480                 }
 481         } else {
 482                 pr_warn("PM: no-rtc available, rtc-only mode disabled.\n");
 483         }
 484
 485         return 0;
 486
 487 err_iounmap:
 488         iounmap(rtc_base_virt);
 489 err_clk_put:
 490         clk_put(rtc_fck);
 491
 492         return error;
 493 }
 494
 495 static int am33xx_pm_probe(struct platform_device *pdev)
 496 {
 497         struct device *dev = &pdev->dev;
 498         int ret;
 499
 500         if (!of_machine_is_compatible("ti,am33xx") &&
 501             !of_machine_is_compatible("ti,am43"))
 502                 return -ENODEV;
 503
 504         pm_ops = dev->platform_data;
 505         if (!pm_ops) {
 506                 dev_err(dev, "PM: Cannot get core PM ops!\n");
 507                 return -ENODEV;
 508         }
 509
 510         ret = am43xx_map_gic();
 511         if (ret) {
 512                 pr_err("PM: Could not ioremap GIC base\n");
 513                 return ret;
 514         }
 515
 516         pm_sram = pm_ops->get_sram_addrs();
 517         if (!pm_sram) {
 518                 dev_err(dev, "PM: Cannot get PM asm function addresses!!\n");
 519                 return -ENODEV;
 520         }
 521
 522         m3_ipc = wkup_m3_ipc_get();
 523         if (!m3_ipc) {
 524                 pr_err("PM: Cannot get wkup_m3_ipc handle\n");
 525                 return -EPROBE_DEFER;
 526         }
 527
 528         pm33xx_dev = dev;
 529
 530         ret = am33xx_pm_alloc_sram();
 531         if (ret)
 532                 goto err_wkup_m3_ipc_put;
 533
 534         ret = am33xx_pm_rtc_setup();
 535         if (ret)
 536                 goto err_free_sram;
 537
 538         ret = am33xx_push_sram_idle();
 539         if (ret)
 540                 goto err_unsetup_rtc;
 541
 542         am33xx_pm_set_ipc_ops();
 543
 544 #ifdef CONFIG_SUSPEND
 545         suspend_set_ops(&am33xx_pm_ops);
 546
 547         /*
 548          * For a system suspend we must flush the caches, we want
 549          * the DDR in self-refresh, we want to save the context
 550          * of the EMIF, and we want the wkup_m3 to handle low-power
 551          * transition.
 552          */
 553         suspend_wfi_flags |= WFI_FLAG_FLUSH_CACHE;
 554         suspend_wfi_flags |= WFI_FLAG_SELF_REFRESH;
 555         suspend_wfi_flags |= WFI_FLAG_SAVE_EMIF;
 556         suspend_wfi_flags |= WFI_FLAG_WAKE_M3;
 557 #endif /* CONFIG_SUSPEND */
 558
 559         pm_runtime_enable(dev);
 560         ret = pm_runtime_get_sync(dev);
 561         if (ret < 0) {
 562                 pm_runtime_put_noidle(dev);
 563                 goto err_pm_runtime_disable;
 564         }
 565
 566         ret = pm_ops->init(am33xx_do_sram_idle);
 567         if (ret) {
 568                 dev_err(dev, "Unable to call core pm init!\n");
 569                 ret = -ENODEV;
 570                 goto err_pm_runtime_put;
 571         }
 572
 573         return 0;
 574
 575 err_pm_runtime_put:
 576         pm_runtime_put_sync(dev);
 577 err_pm_runtime_disable:
 578         pm_runtime_disable(dev);
 579 err_unsetup_rtc:
 580         iounmap(rtc_base_virt);
 581         clk_put(rtc_fck);
 582 err_free_sram:
 583         am33xx_pm_free_sram();
 584         pm33xx_dev = NULL;
 585 err_wkup_m3_ipc_put:
 586         wkup_m3_ipc_put(m3_ipc);
 587         return ret;
 588 }
 589
 590 static int am33xx_pm_remove(struct platform_device *pdev)
 591 {
 592         pm_runtime_put_sync(&pdev->dev);
 593         pm_runtime_disable(&pdev->dev);
 594         if (pm_ops->deinit)
 595                 pm_ops->deinit();
 596         suspend_set_ops(NULL);
 597         wkup_m3_ipc_put(m3_ipc);
 598         am33xx_pm_free_sram();
 599         iounmap(rtc_base_virt);
 600         clk_put(rtc_fck);
 601         return 0;
 602 }
 603
 604 static struct platform_driver am33xx_pm_driver = {
 605         .driver = {
 606                 .name   = "pm33xx",
 607         },
 608         .probe = am33xx_pm_probe,
 609         .remove = am33xx_pm_remove,
 610 };
 611 module_platform_driver(am33xx_pm_driver);
 612
 613 MODULE_ALIAS("platform:pm33xx");
 614 MODULE_LICENSE("GPL v2");
 615 MODULE_DESCRIPTION("am33xx power management driver");