1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller
5 * Copyright (C) 2004-2007 Texas Instruments
6 * Copyright (C) 2008 Nokia Corporation
7 * Contact: Felipe Balbi <felipe.balbi@nokia.com>
10 * - HS USB ULPI mode works.
11 * - 3-pin mode support may be added in future.
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/platform_device.h>
18 #include <linux/workqueue.h>
20 #include <linux/delay.h>
21 #include <linux/usb/otg.h>
22 #include <linux/phy/phy.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/usb/musb.h>
25 #include <linux/usb/ulpi.h>
26 #include <linux/mfd/twl.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/err.h>
29 #include <linux/slab.h>
31 /* Register defines */
33 #define MCPC_CTRL 0x30
34 #define MCPC_CTRL_RTSOL (1 << 7)
35 #define MCPC_CTRL_EXTSWR (1 << 6)
36 #define MCPC_CTRL_EXTSWC (1 << 5)
37 #define MCPC_CTRL_VOICESW (1 << 4)
38 #define MCPC_CTRL_OUT64K (1 << 3)
39 #define MCPC_CTRL_RTSCTSSW (1 << 2)
40 #define MCPC_CTRL_HS_UART (1 << 0)
42 #define MCPC_IO_CTRL 0x33
43 #define MCPC_IO_CTRL_MICBIASEN (1 << 5)
44 #define MCPC_IO_CTRL_CTS_NPU (1 << 4)
45 #define MCPC_IO_CTRL_RXD_PU (1 << 3)
46 #define MCPC_IO_CTRL_TXDTYP (1 << 2)
47 #define MCPC_IO_CTRL_CTSTYP (1 << 1)
48 #define MCPC_IO_CTRL_RTSTYP (1 << 0)
50 #define MCPC_CTRL2 0x36
51 #define MCPC_CTRL2_MCPC_CK_EN (1 << 0)
53 #define OTHER_FUNC_CTRL 0x80
54 #define OTHER_FUNC_CTRL_BDIS_ACON_EN (1 << 4)
55 #define OTHER_FUNC_CTRL_FIVEWIRE_MODE (1 << 2)
57 #define OTHER_IFC_CTRL 0x83
58 #define OTHER_IFC_CTRL_OE_INT_EN (1 << 6)
59 #define OTHER_IFC_CTRL_CEA2011_MODE (1 << 5)
60 #define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN (1 << 4)
61 #define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT (1 << 3)
62 #define OTHER_IFC_CTRL_HIZ_ULPI (1 << 2)
63 #define OTHER_IFC_CTRL_ALT_INT_REROUTE (1 << 0)
65 #define OTHER_INT_EN_RISE 0x86
66 #define OTHER_INT_EN_FALL 0x89
67 #define OTHER_INT_STS 0x8C
68 #define OTHER_INT_LATCH 0x8D
69 #define OTHER_INT_VB_SESS_VLD (1 << 7)
70 #define OTHER_INT_DM_HI (1 << 6) /* not valid for "latch" reg */
71 #define OTHER_INT_DP_HI (1 << 5) /* not valid for "latch" reg */
72 #define OTHER_INT_BDIS_ACON (1 << 3) /* not valid for "fall" regs */
73 #define OTHER_INT_MANU (1 << 1)
74 #define OTHER_INT_ABNORMAL_STRESS (1 << 0)
76 #define ID_STATUS 0x96
77 #define ID_RES_FLOAT (1 << 4)
78 #define ID_RES_440K (1 << 3)
79 #define ID_RES_200K (1 << 2)
80 #define ID_RES_102K (1 << 1)
81 #define ID_RES_GND (1 << 0)
83 #define POWER_CTRL 0xAC
84 #define POWER_CTRL_OTG_ENAB (1 << 5)
86 #define OTHER_IFC_CTRL2 0xAF
87 #define OTHER_IFC_CTRL2_ULPI_STP_LOW (1 << 4)
88 #define OTHER_IFC_CTRL2_ULPI_TXEN_POL (1 << 3)
89 #define OTHER_IFC_CTRL2_ULPI_4PIN_2430 (1 << 2)
90 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK (3 << 0) /* bits 0 and 1 */
91 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N (0 << 0)
92 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N (1 << 0)
94 #define REG_CTRL_EN 0xB2
95 #define REG_CTRL_ERROR 0xB5
96 #define ULPI_I2C_CONFLICT_INTEN (1 << 0)
98 #define OTHER_FUNC_CTRL2 0xB8
99 #define OTHER_FUNC_CTRL2_VBAT_TIMER_EN (1 << 0)
101 /* following registers do not have separate _clr and _set registers */
102 #define VBUS_DEBOUNCE 0xC0
103 #define ID_DEBOUNCE 0xC1
104 #define VBAT_TIMER 0xD3
105 #define PHY_PWR_CTRL 0xFD
106 #define PHY_PWR_PHYPWD (1 << 0)
107 #define PHY_CLK_CTRL 0xFE
108 #define PHY_CLK_CTRL_CLOCKGATING_EN (1 << 2)
109 #define PHY_CLK_CTRL_CLK32K_EN (1 << 1)
110 #define REQ_PHY_DPLL_CLK (1 << 0)
111 #define PHY_CLK_CTRL_STS 0xFF
112 #define PHY_DPLL_CLK (1 << 0)
114 /* In module TWL_MODULE_PM_MASTER */
115 #define STS_HW_CONDITIONS 0x0F
117 /* In module TWL_MODULE_PM_RECEIVER */
118 #define VUSB_DEDICATED1 0x7D
119 #define VUSB_DEDICATED2 0x7E
120 #define VUSB1V5_DEV_GRP 0x71
121 #define VUSB1V5_TYPE 0x72
122 #define VUSB1V5_REMAP 0x73
123 #define VUSB1V8_DEV_GRP 0x74
124 #define VUSB1V8_TYPE 0x75
125 #define VUSB1V8_REMAP 0x76
126 #define VUSB3V1_DEV_GRP 0x77
127 #define VUSB3V1_TYPE 0x78
128 #define VUSB3V1_REMAP 0x79
130 /* In module TWL4030_MODULE_INTBR */
132 #define GPIO_USB_4PIN_ULPI_2430C (3 << 0)
134 static irqreturn_t twl4030_usb_irq(int irq, void *_twl);
136 * If VBUS is valid or ID is ground, then we know a
137 * cable is present and we need to be runtime-enabled
139 static inline bool cable_present(enum musb_vbus_id_status stat)
141 return stat == MUSB_VBUS_VALID ||
142 stat == MUSB_ID_GROUND;
149 /* TWL4030 internal USB regulator supplies */
150 struct regulator *usb1v5;
151 struct regulator *usb1v8;
152 struct regulator *usb3v1;
154 /* for vbus reporting with irqs disabled */
157 /* pin configuration */
158 enum twl4030_usb_mode usb_mode;
161 enum musb_vbus_id_status linkstat;
164 bool musb_mailbox_pending;
165 unsigned long runtime_suspended:1;
166 unsigned long needs_resume:1;
168 struct delayed_work id_workaround_work;
171 /* internal define on top of container_of */
172 #define phy_to_twl(x) container_of((x), struct twl4030_usb, phy)
174 /*-------------------------------------------------------------------------*/
176 static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl,
177 u8 module, u8 data, u8 address)
181 if ((twl_i2c_write_u8(module, data, address) >= 0) &&
182 (twl_i2c_read_u8(module, &check, address) >= 0) &&
185 dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
186 1, module, address, check, data);
188 /* Failed once: Try again */
189 if ((twl_i2c_write_u8(module, data, address) >= 0) &&
190 (twl_i2c_read_u8(module, &check, address) >= 0) &&
193 dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
194 2, module, address, check, data);
196 /* Failed again: Return error */
200 #define twl4030_usb_write_verify(twl, address, data) \
201 twl4030_i2c_write_u8_verify(twl, TWL_MODULE_USB, (data), (address))
203 static inline int twl4030_usb_write(struct twl4030_usb *twl,
208 ret = twl_i2c_write_u8(TWL_MODULE_USB, data, address);
211 "TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
215 static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address)
220 ret = twl_i2c_read_u8(module, &data, address);
225 "TWL4030:readb[0x%x,0x%x] Error %d\n",
226 module, address, ret);
231 static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address)
233 return twl4030_readb(twl, TWL_MODULE_USB, address);
236 /*-------------------------------------------------------------------------*/
239 twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
241 return twl4030_usb_write(twl, ULPI_SET(reg), bits);
245 twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
247 return twl4030_usb_write(twl, ULPI_CLR(reg), bits);
250 /*-------------------------------------------------------------------------*/
252 static bool twl4030_is_driving_vbus(struct twl4030_usb *twl)
256 ret = twl4030_usb_read(twl, PHY_CLK_CTRL_STS);
257 if (ret < 0 || !(ret & PHY_DPLL_CLK))
259 * if clocks are off, registers are not updated,
260 * but we can assume we don't drive VBUS in this case
264 ret = twl4030_usb_read(twl, ULPI_OTG_CTRL);
268 return (ret & (ULPI_OTG_DRVVBUS | ULPI_OTG_CHRGVBUS)) ? true : false;
271 static enum musb_vbus_id_status
272 twl4030_usb_linkstat(struct twl4030_usb *twl)
275 enum musb_vbus_id_status linkstat = MUSB_UNKNOWN;
277 twl->vbus_supplied = false;
280 * For ID/VBUS sensing, see manual section 15.4.8 ...
281 * except when using only battery backup power, two
282 * comparators produce VBUS_PRES and ID_PRES signals,
283 * which don't match docs elsewhere. But ... BIT(7)
284 * and BIT(2) of STS_HW_CONDITIONS, respectively, do
285 * seem to match up. If either is true the USB_PRES
286 * signal is active, the OTG module is activated, and
287 * its interrupt may be raised (may wake the system).
289 status = twl4030_readb(twl, TWL_MODULE_PM_MASTER, STS_HW_CONDITIONS);
291 dev_err(twl->dev, "USB link status err %d\n", status);
292 else if (status & (BIT(7) | BIT(2))) {
293 if (status & BIT(7)) {
294 if (twl4030_is_driving_vbus(twl))
297 twl->vbus_supplied = true;
301 linkstat = MUSB_ID_GROUND;
302 else if (status & BIT(7))
303 linkstat = MUSB_VBUS_VALID;
305 linkstat = MUSB_VBUS_OFF;
307 if (twl->linkstat != MUSB_UNKNOWN)
308 linkstat = MUSB_VBUS_OFF;
311 kobject_uevent(&twl->dev->kobj, linkstat == MUSB_VBUS_VALID
312 ? KOBJ_ONLINE : KOBJ_OFFLINE);
314 dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n",
315 status, status, linkstat);
317 /* REVISIT this assumes host and peripheral controllers
318 * are registered, and that both are active...
324 static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode)
326 twl->usb_mode = mode;
329 case T2_USB_MODE_ULPI:
330 twl4030_usb_clear_bits(twl, ULPI_IFC_CTRL,
331 ULPI_IFC_CTRL_CARKITMODE);
332 twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
333 twl4030_usb_clear_bits(twl, ULPI_FUNC_CTRL,
334 ULPI_FUNC_CTRL_XCVRSEL_MASK |
335 ULPI_FUNC_CTRL_OPMODE_MASK);
338 /* FIXME: power on defaults */
341 dev_err(twl->dev, "unsupported T2 transceiver mode %d\n",
347 static void twl4030_i2c_access(struct twl4030_usb *twl, int on)
349 unsigned long timeout;
350 int val = twl4030_usb_read(twl, PHY_CLK_CTRL);
354 /* enable DPLL to access PHY registers over I2C */
355 val |= REQ_PHY_DPLL_CLK;
356 WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
359 timeout = jiffies + HZ;
360 while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
362 && time_before(jiffies, timeout))
364 if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
366 dev_err(twl->dev, "Timeout setting T2 HSUSB "
369 /* let ULPI control the DPLL clock */
370 val &= ~REQ_PHY_DPLL_CLK;
371 WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
377 static void __twl4030_phy_power(struct twl4030_usb *twl, int on)
379 u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL);
382 pwr &= ~PHY_PWR_PHYPWD;
384 pwr |= PHY_PWR_PHYPWD;
386 WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
389 static int twl4030_usb_runtime_suspend(struct device *dev);
390 static int twl4030_usb_runtime_resume(struct device *dev);
392 static int __maybe_unused twl4030_usb_suspend(struct device *dev)
394 struct twl4030_usb *twl = dev_get_drvdata(dev);
397 * we need enabled runtime on resume,
398 * so turn irq off here, so we do not get it early
399 * note: wakeup on usb plug works independently of this
401 dev_dbg(twl->dev, "%s\n", __func__);
402 disable_irq(twl->irq);
403 if (!twl->runtime_suspended && !atomic_read(&twl->connected)) {
404 twl4030_usb_runtime_suspend(dev);
405 twl->needs_resume = 1;
411 static int __maybe_unused twl4030_usb_resume(struct device *dev)
413 struct twl4030_usb *twl = dev_get_drvdata(dev);
415 dev_dbg(twl->dev, "%s\n", __func__);
416 enable_irq(twl->irq);
417 if (twl->needs_resume)
418 twl4030_usb_runtime_resume(dev);
419 /* check whether cable status changed */
420 twl4030_usb_irq(0, twl);
422 twl->runtime_suspended = 0;
427 static int __maybe_unused twl4030_usb_runtime_suspend(struct device *dev)
429 struct twl4030_usb *twl = dev_get_drvdata(dev);
431 dev_dbg(twl->dev, "%s\n", __func__);
433 __twl4030_phy_power(twl, 0);
434 regulator_disable(twl->usb1v5);
435 regulator_disable(twl->usb1v8);
436 regulator_disable(twl->usb3v1);
438 twl->runtime_suspended = 1;
443 static int __maybe_unused twl4030_usb_runtime_resume(struct device *dev)
445 struct twl4030_usb *twl = dev_get_drvdata(dev);
448 dev_dbg(twl->dev, "%s\n", __func__);
450 res = regulator_enable(twl->usb3v1);
452 dev_err(twl->dev, "Failed to enable usb3v1\n");
454 res = regulator_enable(twl->usb1v8);
456 dev_err(twl->dev, "Failed to enable usb1v8\n");
459 * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP
460 * in twl4030) resets the VUSB_DEDICATED2 register. This reset
461 * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to
462 * SLEEP. We work around this by clearing the bit after usv3v1
463 * is re-activated. This ensures that VUSB3V1 is really active.
465 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);
467 res = regulator_enable(twl->usb1v5);
469 dev_err(twl->dev, "Failed to enable usb1v5\n");
471 __twl4030_phy_power(twl, 1);
472 twl4030_usb_write(twl, PHY_CLK_CTRL,
473 twl4030_usb_read(twl, PHY_CLK_CTRL) |
474 (PHY_CLK_CTRL_CLOCKGATING_EN |
475 PHY_CLK_CTRL_CLK32K_EN));
477 twl4030_i2c_access(twl, 1);
478 twl4030_usb_set_mode(twl, twl->usb_mode);
479 if (twl->usb_mode == T2_USB_MODE_ULPI)
480 twl4030_i2c_access(twl, 0);
482 * According to the TPS65950 TRM, there has to be at least 50ms
483 * delay between setting POWER_CTRL_OTG_ENAB and enabling charging
484 * so wait here so that a fully enabled phy can be expected after
491 static int twl4030_phy_power_off(struct phy *phy)
493 struct twl4030_usb *twl = phy_get_drvdata(phy);
495 dev_dbg(twl->dev, "%s\n", __func__);
500 static int twl4030_phy_power_on(struct phy *phy)
502 struct twl4030_usb *twl = phy_get_drvdata(phy);
504 dev_dbg(twl->dev, "%s\n", __func__);
505 pm_runtime_get_sync(twl->dev);
506 schedule_delayed_work(&twl->id_workaround_work, HZ);
507 pm_runtime_mark_last_busy(twl->dev);
508 pm_runtime_put_autosuspend(twl->dev);
513 static int twl4030_usb_ldo_init(struct twl4030_usb *twl)
515 /* Enable writing to power configuration registers */
516 twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
517 TWL4030_PM_MASTER_PROTECT_KEY);
519 twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
520 TWL4030_PM_MASTER_PROTECT_KEY);
522 /* Keep VUSB3V1 LDO in sleep state until VBUS/ID change detected*/
523 /*twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);*/
525 /* input to VUSB3V1 LDO is from VBAT, not VBUS */
526 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1);
528 /* Initialize 3.1V regulator */
529 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP);
531 twl->usb3v1 = devm_regulator_get(twl->dev, "usb3v1");
532 if (IS_ERR(twl->usb3v1))
535 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE);
537 /* Initialize 1.5V regulator */
538 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP);
540 twl->usb1v5 = devm_regulator_get(twl->dev, "usb1v5");
541 if (IS_ERR(twl->usb1v5))
544 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE);
546 /* Initialize 1.8V regulator */
547 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP);
549 twl->usb1v8 = devm_regulator_get(twl->dev, "usb1v8");
550 if (IS_ERR(twl->usb1v8))
553 twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE);
555 /* disable access to power configuration registers */
556 twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
557 TWL4030_PM_MASTER_PROTECT_KEY);
562 static ssize_t vbus_show(struct device *dev,
563 struct device_attribute *attr, char *buf)
565 struct twl4030_usb *twl = dev_get_drvdata(dev);
568 mutex_lock(&twl->lock);
569 ret = sprintf(buf, "%s\n",
570 twl->vbus_supplied ? "on" : "off");
571 mutex_unlock(&twl->lock);
575 static DEVICE_ATTR_RO(vbus);
577 static irqreturn_t twl4030_usb_irq(int irq, void *_twl)
579 struct twl4030_usb *twl = _twl;
580 enum musb_vbus_id_status status;
583 status = twl4030_usb_linkstat(twl);
585 mutex_lock(&twl->lock);
586 twl->linkstat = status;
587 mutex_unlock(&twl->lock);
589 if (cable_present(status)) {
590 if (atomic_add_unless(&twl->connected, 1, 1)) {
591 dev_dbg(twl->dev, "%s: cable connected %i\n",
593 pm_runtime_get_sync(twl->dev);
594 twl->musb_mailbox_pending = true;
597 if (atomic_add_unless(&twl->connected, -1, 0)) {
598 dev_dbg(twl->dev, "%s: cable disconnected %i\n",
600 pm_runtime_mark_last_busy(twl->dev);
601 pm_runtime_put_autosuspend(twl->dev);
602 twl->musb_mailbox_pending = true;
605 if (twl->musb_mailbox_pending) {
606 err = musb_mailbox(status);
608 twl->musb_mailbox_pending = false;
611 /* don't schedule during sleep - irq works right then */
612 if (status == MUSB_ID_GROUND && pm_runtime_active(twl->dev)) {
613 cancel_delayed_work(&twl->id_workaround_work);
614 schedule_delayed_work(&twl->id_workaround_work, HZ);
618 sysfs_notify(&twl->dev->kobj, NULL, "vbus");
623 static void twl4030_id_workaround_work(struct work_struct *work)
625 struct twl4030_usb *twl = container_of(work, struct twl4030_usb,
626 id_workaround_work.work);
628 twl4030_usb_irq(0, twl);
631 static int twl4030_phy_init(struct phy *phy)
633 struct twl4030_usb *twl = phy_get_drvdata(phy);
635 pm_runtime_get_sync(twl->dev);
636 twl->linkstat = MUSB_UNKNOWN;
637 schedule_delayed_work(&twl->id_workaround_work, HZ);
638 pm_runtime_mark_last_busy(twl->dev);
639 pm_runtime_put_autosuspend(twl->dev);
644 static int twl4030_set_peripheral(struct usb_otg *otg,
645 struct usb_gadget *gadget)
650 otg->gadget = gadget;
652 otg->state = OTG_STATE_UNDEFINED;
657 static int twl4030_set_host(struct usb_otg *otg, struct usb_bus *host)
664 otg->state = OTG_STATE_UNDEFINED;
669 static const struct phy_ops ops = {
670 .init = twl4030_phy_init,
671 .power_on = twl4030_phy_power_on,
672 .power_off = twl4030_phy_power_off,
673 .owner = THIS_MODULE,
676 static const struct dev_pm_ops twl4030_usb_pm_ops = {
677 SET_RUNTIME_PM_OPS(twl4030_usb_runtime_suspend,
678 twl4030_usb_runtime_resume, NULL)
679 SET_SYSTEM_SLEEP_PM_OPS(twl4030_usb_suspend, twl4030_usb_resume)
682 static int twl4030_usb_probe(struct platform_device *pdev)
684 struct twl4030_usb_data *pdata = dev_get_platdata(&pdev->dev);
685 struct twl4030_usb *twl;
689 struct device_node *np = pdev->dev.of_node;
690 struct phy_provider *phy_provider;
692 twl = devm_kzalloc(&pdev->dev, sizeof(*twl), GFP_KERNEL);
697 of_property_read_u32(np, "usb_mode",
698 (enum twl4030_usb_mode *)&twl->usb_mode);
700 twl->usb_mode = pdata->usb_mode;
702 dev_err(&pdev->dev, "twl4030 initialized without pdata\n");
706 otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL);
710 twl->dev = &pdev->dev;
711 twl->irq = platform_get_irq(pdev, 0);
712 twl->vbus_supplied = false;
713 twl->linkstat = MUSB_UNKNOWN;
714 twl->musb_mailbox_pending = false;
716 twl->phy.dev = twl->dev;
717 twl->phy.label = "twl4030";
719 twl->phy.type = USB_PHY_TYPE_USB2;
721 otg->usb_phy = &twl->phy;
722 otg->set_host = twl4030_set_host;
723 otg->set_peripheral = twl4030_set_peripheral;
725 phy = devm_phy_create(twl->dev, NULL, &ops);
727 dev_dbg(&pdev->dev, "Failed to create PHY\n");
731 phy_set_drvdata(phy, twl);
733 phy_provider = devm_of_phy_provider_register(twl->dev,
734 of_phy_simple_xlate);
735 if (IS_ERR(phy_provider))
736 return PTR_ERR(phy_provider);
738 /* init mutex for workqueue */
739 mutex_init(&twl->lock);
741 INIT_DELAYED_WORK(&twl->id_workaround_work, twl4030_id_workaround_work);
743 err = twl4030_usb_ldo_init(twl);
745 dev_err(&pdev->dev, "ldo init failed\n");
748 usb_add_phy_dev(&twl->phy);
750 platform_set_drvdata(pdev, twl);
751 if (device_create_file(&pdev->dev, &dev_attr_vbus))
752 dev_warn(&pdev->dev, "could not create sysfs file\n");
754 ATOMIC_INIT_NOTIFIER_HEAD(&twl->phy.notifier);
756 pm_runtime_use_autosuspend(&pdev->dev);
757 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
758 pm_runtime_enable(&pdev->dev);
759 pm_runtime_get_sync(&pdev->dev);
761 /* Our job is to use irqs and status from the power module
762 * to keep the transceiver disabled when nothing's connected.
764 * FIXME we actually shouldn't start enabling it until the
765 * USB controller drivers have said they're ready, by calling
766 * set_host() and/or set_peripheral() ... OTG_capable boards
767 * need both handles, otherwise just one suffices.
769 status = devm_request_threaded_irq(twl->dev, twl->irq, NULL,
770 twl4030_usb_irq, IRQF_TRIGGER_FALLING |
771 IRQF_TRIGGER_RISING | IRQF_ONESHOT, "twl4030_usb", twl);
773 dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n",
779 err = phy_create_lookup(phy, "usb", "musb-hdrc.0");
783 pm_runtime_mark_last_busy(&pdev->dev);
784 pm_runtime_put_autosuspend(twl->dev);
786 dev_info(&pdev->dev, "Initialized TWL4030 USB module\n");
790 static int twl4030_usb_remove(struct platform_device *pdev)
792 struct twl4030_usb *twl = platform_get_drvdata(pdev);
795 usb_remove_phy(&twl->phy);
796 pm_runtime_get_sync(twl->dev);
797 cancel_delayed_work_sync(&twl->id_workaround_work);
798 device_remove_file(twl->dev, &dev_attr_vbus);
800 /* set transceiver mode to power on defaults */
801 twl4030_usb_set_mode(twl, -1);
803 /* idle ulpi before powering off */
804 if (cable_present(twl->linkstat))
805 pm_runtime_put_noidle(twl->dev);
806 pm_runtime_mark_last_busy(twl->dev);
807 pm_runtime_dont_use_autosuspend(&pdev->dev);
808 pm_runtime_put_sync(twl->dev);
809 pm_runtime_disable(twl->dev);
811 /* autogate 60MHz ULPI clock,
812 * clear dpll clock request for i2c access,
815 val = twl4030_usb_read(twl, PHY_CLK_CTRL);
817 val |= PHY_CLK_CTRL_CLOCKGATING_EN;
818 val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK);
819 twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val);
822 /* disable complete OTG block */
823 twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
829 static const struct of_device_id twl4030_usb_id_table[] = {
830 { .compatible = "ti,twl4030-usb" },
833 MODULE_DEVICE_TABLE(of, twl4030_usb_id_table);
836 static struct platform_driver twl4030_usb_driver = {
837 .probe = twl4030_usb_probe,
838 .remove = twl4030_usb_remove,
840 .name = "twl4030_usb",
841 .pm = &twl4030_usb_pm_ops,
842 .of_match_table = of_match_ptr(twl4030_usb_id_table),
846 static int __init twl4030_usb_init(void)
848 return platform_driver_register(&twl4030_usb_driver);
850 subsys_initcall(twl4030_usb_init);
852 static void __exit twl4030_usb_exit(void)
854 platform_driver_unregister(&twl4030_usb_driver);
856 module_exit(twl4030_usb_exit);
858 MODULE_ALIAS("platform:twl4030_usb");
859 MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation");
860 MODULE_DESCRIPTION("TWL4030 USB transceiver driver");
861 MODULE_LICENSE("GPL");