1 /* This is a bcm43xx microcode assembly example.
3 * In this example file, r0 and r1 are always input
4 * registers and r2 is output.
5 * For input we can always have constant values or (one) memory
6 * operand instead of the input registers shown here.
10 * Offset Registers: off0 - off5
13 * To access memory, two methods can be used. Examples follow.
16 * Indirect through Offset Register (pointer):
21 /* The target architecture. Supported versions are 5 and 15 */
24 /* Program entry point */
27 #define PSM_BRC spr848
29 #define ECOND_MAC_ON (0x20 | 4)
31 %assert ((((1))) == ((((2 - 1) & 0xFF))))
32 %assert ((1 == 2) || (1 == (0xFF & 1)))
34 %assert ((1 == (2 - 1)) && (2 == 2))
39 /* ADD instructions */
40 add r0,r1,r2 /* add */
41 add. r0,r1,r2 /* add, set carry */
42 addc r0,r1,r2 /* add with carry */
43 addc. r0,r1,r2 /* add with carry, set carry */
46 /* SUB instructions */
47 sub r0,r1,r2 /* sub */
48 sub. r0,r1,r2 /* sub, set carry */
49 subc r0,r1,r2 /* sub with carry */
50 subc. r0,r1,r2 /* sub with carry, set carry */
52 sra r0,r1,r2 /* arithmetic rightshift */
54 /* Logical instructions */
55 or r0,r1,r2 /* bitwise OR */
56 and r0,r1,r2 /* bitwise AND */
57 xor r0,r1,r2 /* bitwise XOR */
58 sr r0,r1,r2 /* rightshift */
59 sl r0,r1,r2 /* leftshift */
61 srx 7,8,r0,r1,r2 /* eXtended right shift (two input regs) */
63 rl r0,r1,r2 /* rotate left */
64 rr r0,r1,r2 /* rotate right */
65 nand r0,r1,r2 /* clear bits (notmask + and) */
67 orx 7,8,r0,r1,r2 /* eXtended OR */
69 /* Copy instruction. This is a virtual instruction
70 * translated to more lowlevel stuff like OR. */
71 mov r0,r2 /* copy data */
74 jmp label /* unconditional jump */
75 jand r0,r1,label /* jump if binary AND */
76 jnand r0,r1,label /* jump if not binary AND */
77 js r0,r1,label /* jump if all bits set */
78 jns r0,r1,label /* jump if not all bits set */
79 je r0,r1,label /* jump if equal */
80 jne r0,r1,label /* jump if not equal */
81 jls r0,r1,label /* jump if less (signed) */
82 jges r0,r1,label /* jump if greater or equal (signed) */
83 jgs r0,r1,label /* jump if greater (signed) */
84 jles r0,r1,label /* jump if less or equal (signed) */
85 jl r0,r1,label /* jump if less */
86 jge r0,r1,label /* jump if greater or equal */
87 jg r0,r1,label /* jump if greater */
88 jle r0,r1,label /* jump if less or equal */
90 jzx 7,8,r0,r1,label /* Jump if zero after shift and mask */
91 jnzx 7,8,r0,r1,label /* Jump if nonzero after shift and mask */
93 /* jump on external conditions */
94 jext ECOND_MAC_ON,label /* jump if external condition is TRUE */
95 jnext ECOND_MAC_ON,label /* jump if external condition is FALSE */
98 call lr0,label /* store PC in lr0, call func at label */
99 ret lr0,lr1 /* store PC in lr0, return to lr1
100 * Both link registers can be the same
101 * and don't interfere. */
103 /* TKIP sbox lookup */
104 tkiph r0,r2 /* Lookup high */
105 tkiphs r0,r2 /* Lookup high, byteswap */
106 tkipl r0,r2 /* Lookup low */
107 tkipls r0,r2 /* Lookup low, byteswap */
109 nap /* sleep until event */
111 /* raw instruction */
112 @160 r0,r1,r2 /* equivalent to or r0,r1,r2 */
113 @1C0 @C11, @C22, @BC3
116 /* Support for directional jumps.
117 * Directional jumps can be used to conveniently jump inside of
118 * functions without using function specific label prefixes. Note
119 * that this does not establish a sub-namespace, though. "loop"
120 * and "out" are still in the global namespace and can't be used
121 * anymore for absolute jumps (Assembler will warn about duplication).
142 /* The assembler has support for fancy assemble-time
143 * immediate constant expansion. This is called "complex immediates".
144 * Complex immediates are _always_ clamped by parentheses. There is no
145 * operator precedence. You must use parentheses to tell precedence.
157 mov (1 << (0x3 + 2)),r0
158 mov (1 + (2 + (3 + 4))),r0
159 mov (4 >> (((((~5 | 0x21)))) | (~((10) & 2)))),r0
162 /* Some regression testing for the assembler follows */
163 mov 2,off0 /* test memory stuff */
164 xor 0x124,r1,[0x0,off0] /* test memory stuff */
165 xor 0x124,r0,[0x0] /* test memory stuff */
166 mov -34,r0 /* negative dec numbers are supported */
167 or r0,r1,@BC2 /* We also support single raw operands */
168 mov 0xEEEE,r0 /* MOV supports up to 16bit */
169 jand 0x3800,r0,label /* This is emulated by jnzx */
170 jnand 0x3800,r0,label /* This is emulated by jzx */
171 or spr06c,0,spr06c /* Can have one spr input and one spr output */
172 or [0],0,[0] /* Can have one mem input and one mem output */
173 mov testlabel, r0 /* Can use label as immediate value */
174 mov r0,r1;mov r2, r3 /* ; does split instructions */
175 mov [(1+1)],[(2+2),off0] /* Can use complex immediates as memory offsets */
176 orx (0 + 1), (1 * 2), 0, 0, r0 /* Allow complex immediates as M or S */
179 /* The .initvals section generates an "Initial Values" file
180 * with the name "foobar" in this example, which is uploaded
181 * by the kernel driver on load. This is useful for writing ucode
182 * specific values to the chip without bloating the small ucode
183 * memory space with this initialization stuff.
184 * Values are written in order they appear here.
187 mmio16 0x1234, 0xABC /* Write 0x1234 to MMIO register 0xABC */
188 mmio32 0x12345678, 0xABC /* Write 0x12345678 to MMIO register 0xABC */
189 phy 0x1234, 0xABC /* Write 0x1234 to PHY register 0xABC */
190 radio 0x1234, 0xABC /* Write 0x1234 to RADIO register 0xABC */
191 shm16 0x1234, 0x0001, 0x0002 /* Write 0x1234 to SHM routing 0x0001, register 0x0002 */
192 shm32 0x12345678, 0x0001, 0x0002 /* Write 0x12345678 to SHM routing 0x0001, register 0x0002 */
195 // vim: syntax=b43 ts=8