1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved
6 #include <linux/cpufreq.h>
7 #include <linux/dma-mapping.h>
8 #include <linux/module.h>
10 #include <linux/platform_device.h>
12 #include <soc/tegra/bpmp.h>
13 #include <soc/tegra/bpmp-abi.h>
15 #define EDVD_CORE_VOLT_FREQ(core) (0x20 + (core) * 0x4)
16 #define EDVD_CORE_VOLT_FREQ_F_SHIFT 0
17 #define EDVD_CORE_VOLT_FREQ_F_MASK 0xffff
18 #define EDVD_CORE_VOLT_FREQ_V_SHIFT 16
20 struct tegra186_cpufreq_cluster_info {
23 unsigned int bpmp_cluster_id;
27 static const struct tegra186_cpufreq_cluster_info tegra186_clusters[] = {
31 .cpus = { 1, 2, NO_CPU, NO_CPU },
37 .cpus = { 0, 3, 4, 5 },
42 struct tegra186_cpufreq_cluster {
43 const struct tegra186_cpufreq_cluster_info *info;
44 struct cpufreq_frequency_table *table;
49 struct tegra186_cpufreq_data {
53 struct tegra186_cpufreq_cluster *clusters;
56 static int tegra186_cpufreq_init(struct cpufreq_policy *policy)
58 struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
61 for (i = 0; i < data->num_clusters; i++) {
62 struct tegra186_cpufreq_cluster *cluster = &data->clusters[i];
63 const struct tegra186_cpufreq_cluster_info *info =
67 for (core = 0; core < ARRAY_SIZE(info->cpus); core++) {
68 if (info->cpus[core] == policy->cpu)
71 if (core == ARRAY_SIZE(info->cpus))
75 data->regs + info->offset + EDVD_CORE_VOLT_FREQ(core);
76 policy->freq_table = cluster->table;
80 policy->cpuinfo.transition_latency = 300 * 1000;
85 static int tegra186_cpufreq_set_target(struct cpufreq_policy *policy,
88 struct cpufreq_frequency_table *tbl = policy->freq_table + index;
89 void __iomem *edvd_reg = policy->driver_data;
90 u32 edvd_val = tbl->driver_data;
92 writel(edvd_val, edvd_reg);
97 static unsigned int tegra186_cpufreq_get(unsigned int cpu)
99 struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
100 struct cpufreq_policy *policy;
101 void __iomem *edvd_reg;
102 unsigned int i, freq = 0;
105 policy = cpufreq_cpu_get(cpu);
109 edvd_reg = policy->driver_data;
110 ndiv = readl(edvd_reg) & EDVD_CORE_VOLT_FREQ_F_MASK;
112 for (i = 0; i < data->num_clusters; i++) {
113 struct tegra186_cpufreq_cluster *cluster = &data->clusters[i];
116 for (core = 0; core < ARRAY_SIZE(cluster->info->cpus); core++) {
117 if (cluster->info->cpus[core] != policy->cpu)
120 freq = (cluster->ref_clk_khz * ndiv) / cluster->div;
126 cpufreq_cpu_put(policy);
131 static struct cpufreq_driver tegra186_cpufreq_driver = {
133 .flags = CPUFREQ_STICKY | CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
134 CPUFREQ_NEED_INITIAL_FREQ_CHECK,
135 .get = tegra186_cpufreq_get,
136 .verify = cpufreq_generic_frequency_table_verify,
137 .target_index = tegra186_cpufreq_set_target,
138 .init = tegra186_cpufreq_init,
139 .attr = cpufreq_generic_attr,
142 static struct cpufreq_frequency_table *init_vhint_table(
143 struct platform_device *pdev, struct tegra_bpmp *bpmp,
144 struct tegra186_cpufreq_cluster *cluster)
146 struct cpufreq_frequency_table *table;
147 struct mrq_cpu_vhint_request req;
148 struct tegra_bpmp_message msg;
149 struct cpu_vhint_data *data;
150 int err, i, j, num_rates = 0;
154 virt = dma_alloc_coherent(bpmp->dev, sizeof(*data), &phys,
157 return ERR_PTR(-ENOMEM);
159 data = (struct cpu_vhint_data *)virt;
161 memset(&req, 0, sizeof(req));
163 req.cluster_id = cluster->info->bpmp_cluster_id;
165 memset(&msg, 0, sizeof(msg));
166 msg.mrq = MRQ_CPU_VHINT;
168 msg.tx.size = sizeof(req);
170 err = tegra_bpmp_transfer(bpmp, &msg);
172 table = ERR_PTR(err);
176 for (i = data->vfloor; i <= data->vceil; i++) {
177 u16 ndiv = data->ndiv[i];
179 if (ndiv < data->ndiv_min || ndiv > data->ndiv_max)
182 /* Only store lowest voltage index for each rate */
183 if (i > 0 && ndiv == data->ndiv[i - 1])
189 table = devm_kcalloc(&pdev->dev, num_rates + 1, sizeof(*table),
192 table = ERR_PTR(-ENOMEM);
196 cluster->ref_clk_khz = data->ref_clk_hz / 1000;
197 cluster->div = data->pdiv * data->mdiv;
199 for (i = data->vfloor, j = 0; i <= data->vceil; i++) {
200 struct cpufreq_frequency_table *point;
201 u16 ndiv = data->ndiv[i];
204 if (ndiv < data->ndiv_min || ndiv > data->ndiv_max)
207 /* Only store lowest voltage index for each rate */
208 if (i > 0 && ndiv == data->ndiv[i - 1])
211 edvd_val |= i << EDVD_CORE_VOLT_FREQ_V_SHIFT;
212 edvd_val |= ndiv << EDVD_CORE_VOLT_FREQ_F_SHIFT;
215 point->driver_data = edvd_val;
216 point->frequency = (cluster->ref_clk_khz * ndiv) / cluster->div;
219 table[j].frequency = CPUFREQ_TABLE_END;
222 dma_free_coherent(bpmp->dev, sizeof(*data), virt, phys);
227 static int tegra186_cpufreq_probe(struct platform_device *pdev)
229 struct tegra186_cpufreq_data *data;
230 struct tegra_bpmp *bpmp;
231 unsigned int i = 0, err;
233 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
237 data->clusters = devm_kcalloc(&pdev->dev, ARRAY_SIZE(tegra186_clusters),
238 sizeof(*data->clusters), GFP_KERNEL);
242 data->num_clusters = ARRAY_SIZE(tegra186_clusters);
244 bpmp = tegra_bpmp_get(&pdev->dev);
246 return PTR_ERR(bpmp);
248 data->regs = devm_platform_ioremap_resource(pdev, 0);
249 if (IS_ERR(data->regs)) {
250 err = PTR_ERR(data->regs);
254 for (i = 0; i < data->num_clusters; i++) {
255 struct tegra186_cpufreq_cluster *cluster = &data->clusters[i];
257 cluster->info = &tegra186_clusters[i];
258 cluster->table = init_vhint_table(pdev, bpmp, cluster);
259 if (IS_ERR(cluster->table)) {
260 err = PTR_ERR(cluster->table);
265 tegra186_cpufreq_driver.driver_data = data;
267 err = cpufreq_register_driver(&tegra186_cpufreq_driver);
270 tegra_bpmp_put(bpmp);
275 static int tegra186_cpufreq_remove(struct platform_device *pdev)
277 cpufreq_unregister_driver(&tegra186_cpufreq_driver);
282 static const struct of_device_id tegra186_cpufreq_of_match[] = {
283 { .compatible = "nvidia,tegra186-ccplex-cluster", },
286 MODULE_DEVICE_TABLE(of, tegra186_cpufreq_of_match);
288 static struct platform_driver tegra186_cpufreq_platform_driver = {
290 .name = "tegra186-cpufreq",
291 .of_match_table = tegra186_cpufreq_of_match,
293 .probe = tegra186_cpufreq_probe,
294 .remove = tegra186_cpufreq_remove,
296 module_platform_driver(tegra186_cpufreq_platform_driver);
298 MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
299 MODULE_DESCRIPTION("NVIDIA Tegra186 cpufreq driver");
300 MODULE_LICENSE("GPL v2");