1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
6 #include <linux/delay.h>
7 #include <linux/interrupt.h>
9 #include <linux/mailbox_controller.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
14 #include <linux/slab.h>
16 #include <soc/tegra/fuse.h>
18 #include <dt-bindings/mailbox/tegra186-hsp.h>
22 #define HSP_INT_IE(x) (0x100 + ((x) * 4))
23 #define HSP_INT_IV 0x300
24 #define HSP_INT_IR 0x304
26 #define HSP_INT_EMPTY_SHIFT 0
27 #define HSP_INT_EMPTY_MASK 0xff
28 #define HSP_INT_FULL_SHIFT 8
29 #define HSP_INT_FULL_MASK 0xff
31 #define HSP_INT_DIMENSIONING 0x380
32 #define HSP_nSM_SHIFT 0
33 #define HSP_nSS_SHIFT 4
34 #define HSP_nAS_SHIFT 8
35 #define HSP_nDB_SHIFT 12
36 #define HSP_nSI_SHIFT 16
37 #define HSP_nINT_MASK 0xf
39 #define HSP_DB_TRIGGER 0x0
40 #define HSP_DB_ENABLE 0x4
41 #define HSP_DB_RAW 0x8
42 #define HSP_DB_PENDING 0xc
44 #define HSP_SM_SHRD_MBOX 0x0
45 #define HSP_SM_SHRD_MBOX_FULL BIT(31)
46 #define HSP_SM_SHRD_MBOX_FULL_INT_IE 0x04
47 #define HSP_SM_SHRD_MBOX_EMPTY_INT_IE 0x08
49 #define HSP_DB_CCPLEX 1
53 struct tegra_hsp_channel;
56 struct tegra_hsp_channel {
57 struct tegra_hsp *hsp;
58 struct mbox_chan *chan;
62 struct tegra_hsp_doorbell {
63 struct tegra_hsp_channel channel;
64 struct list_head list;
70 struct tegra_hsp_mailbox {
71 struct tegra_hsp_channel channel;
76 struct tegra_hsp_db_map {
82 struct tegra_hsp_soc {
83 const struct tegra_hsp_db_map *map;
89 const struct tegra_hsp_soc *soc;
90 struct mbox_controller mbox_db;
91 struct mbox_controller mbox_sm;
93 unsigned int doorbell_irq;
94 unsigned int *shared_irqs;
95 unsigned int shared_irq;
103 struct list_head doorbells;
104 struct tegra_hsp_mailbox *mailboxes;
109 static inline u32 tegra_hsp_readl(struct tegra_hsp *hsp, unsigned int offset)
111 return readl(hsp->regs + offset);
114 static inline void tegra_hsp_writel(struct tegra_hsp *hsp, u32 value,
117 writel(value, hsp->regs + offset);
120 static inline u32 tegra_hsp_channel_readl(struct tegra_hsp_channel *channel,
123 return readl(channel->regs + offset);
126 static inline void tegra_hsp_channel_writel(struct tegra_hsp_channel *channel,
127 u32 value, unsigned int offset)
129 writel(value, channel->regs + offset);
132 static bool tegra_hsp_doorbell_can_ring(struct tegra_hsp_doorbell *db)
136 value = tegra_hsp_channel_readl(&db->channel, HSP_DB_ENABLE);
138 return (value & BIT(TEGRA_HSP_DB_MASTER_CCPLEX)) != 0;
141 static struct tegra_hsp_doorbell *
142 __tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
144 struct tegra_hsp_doorbell *entry;
146 list_for_each_entry(entry, &hsp->doorbells, list)
147 if (entry->master == master)
153 static struct tegra_hsp_doorbell *
154 tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
156 struct tegra_hsp_doorbell *db;
159 spin_lock_irqsave(&hsp->lock, flags);
160 db = __tegra_hsp_doorbell_get(hsp, master);
161 spin_unlock_irqrestore(&hsp->lock, flags);
166 static irqreturn_t tegra_hsp_doorbell_irq(int irq, void *data)
168 struct tegra_hsp *hsp = data;
169 struct tegra_hsp_doorbell *db;
170 unsigned long master, value;
172 db = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
176 value = tegra_hsp_channel_readl(&db->channel, HSP_DB_PENDING);
177 tegra_hsp_channel_writel(&db->channel, value, HSP_DB_PENDING);
179 spin_lock(&hsp->lock);
181 for_each_set_bit(master, &value, hsp->mbox_db.num_chans) {
182 struct tegra_hsp_doorbell *db;
184 db = __tegra_hsp_doorbell_get(hsp, master);
186 * Depending on the bootloader chain, the CCPLEX doorbell will
187 * have some doorbells enabled, which means that requesting an
188 * interrupt will immediately fire.
190 * In that case, db->channel.chan will still be NULL here and
191 * cause a crash if not properly guarded.
193 * It remains to be seen if ignoring the doorbell in that case
194 * is the correct solution.
196 if (db && db->channel.chan)
197 mbox_chan_received_data(db->channel.chan, NULL);
200 spin_unlock(&hsp->lock);
205 static irqreturn_t tegra_hsp_shared_irq(int irq, void *data)
207 struct tegra_hsp *hsp = data;
208 unsigned long bit, mask;
212 status = tegra_hsp_readl(hsp, HSP_INT_IR) & hsp->mask;
214 /* process EMPTY interrupts first */
215 mask = (status >> HSP_INT_EMPTY_SHIFT) & HSP_INT_EMPTY_MASK;
217 for_each_set_bit(bit, &mask, hsp->num_sm) {
218 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
222 * Disable EMPTY interrupts until data is sent with
223 * the next message. These interrupts are level-
224 * triggered, so if we kept them enabled they would
225 * constantly trigger until we next write data into
228 spin_lock(&hsp->lock);
230 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
231 tegra_hsp_writel(hsp, hsp->mask,
232 HSP_INT_IE(hsp->shared_irq));
234 spin_unlock(&hsp->lock);
236 mbox_chan_txdone(mb->channel.chan, 0);
240 /* process FULL interrupts */
241 mask = (status >> HSP_INT_FULL_SHIFT) & HSP_INT_FULL_MASK;
243 for_each_set_bit(bit, &mask, hsp->num_sm) {
244 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
247 value = tegra_hsp_channel_readl(&mb->channel,
249 value &= ~HSP_SM_SHRD_MBOX_FULL;
250 msg = (void *)(unsigned long)value;
251 mbox_chan_received_data(mb->channel.chan, msg);
254 * Need to clear all bits here since some producers,
255 * such as TCU, depend on fields in the register
256 * getting cleared by the consumer.
258 * The mailbox API doesn't give the consumers a way
259 * of doing that explicitly, so we have to make sure
260 * we cover all possible cases.
262 tegra_hsp_channel_writel(&mb->channel, 0x0,
270 static struct tegra_hsp_channel *
271 tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name,
272 unsigned int master, unsigned int index)
274 struct tegra_hsp_doorbell *db;
278 db = devm_kzalloc(hsp->dev, sizeof(*db), GFP_KERNEL);
280 return ERR_PTR(-ENOMEM);
282 offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K;
283 offset += index * 0x100;
285 db->channel.regs = hsp->regs + offset;
286 db->channel.hsp = hsp;
288 db->name = devm_kstrdup_const(hsp->dev, name, GFP_KERNEL);
292 spin_lock_irqsave(&hsp->lock, flags);
293 list_add_tail(&db->list, &hsp->doorbells);
294 spin_unlock_irqrestore(&hsp->lock, flags);
299 static int tegra_hsp_doorbell_send_data(struct mbox_chan *chan, void *data)
301 struct tegra_hsp_doorbell *db = chan->con_priv;
303 tegra_hsp_channel_writel(&db->channel, 1, HSP_DB_TRIGGER);
308 static int tegra_hsp_doorbell_startup(struct mbox_chan *chan)
310 struct tegra_hsp_doorbell *db = chan->con_priv;
311 struct tegra_hsp *hsp = db->channel.hsp;
312 struct tegra_hsp_doorbell *ccplex;
316 if (db->master >= chan->mbox->num_chans) {
317 dev_err(chan->mbox->dev,
318 "invalid master ID %u for HSP channel\n",
323 ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
328 * On simulation platforms the BPMP hasn't had a chance yet to mark
329 * the doorbell as ringable by the CCPLEX, so we want to skip extra
332 if (tegra_is_silicon() && !tegra_hsp_doorbell_can_ring(db))
335 spin_lock_irqsave(&hsp->lock, flags);
337 value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
338 value |= BIT(db->master);
339 tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
341 spin_unlock_irqrestore(&hsp->lock, flags);
346 static void tegra_hsp_doorbell_shutdown(struct mbox_chan *chan)
348 struct tegra_hsp_doorbell *db = chan->con_priv;
349 struct tegra_hsp *hsp = db->channel.hsp;
350 struct tegra_hsp_doorbell *ccplex;
354 ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
358 spin_lock_irqsave(&hsp->lock, flags);
360 value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
361 value &= ~BIT(db->master);
362 tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
364 spin_unlock_irqrestore(&hsp->lock, flags);
367 static const struct mbox_chan_ops tegra_hsp_db_ops = {
368 .send_data = tegra_hsp_doorbell_send_data,
369 .startup = tegra_hsp_doorbell_startup,
370 .shutdown = tegra_hsp_doorbell_shutdown,
373 static int tegra_hsp_mailbox_send_data(struct mbox_chan *chan, void *data)
375 struct tegra_hsp_mailbox *mb = chan->con_priv;
376 struct tegra_hsp *hsp = mb->channel.hsp;
380 if (WARN_ON(!mb->producer))
383 /* copy data and mark mailbox full */
384 value = (u32)(unsigned long)data;
385 value |= HSP_SM_SHRD_MBOX_FULL;
387 tegra_hsp_channel_writel(&mb->channel, value, HSP_SM_SHRD_MBOX);
389 /* enable EMPTY interrupt for the shared mailbox */
390 spin_lock_irqsave(&hsp->lock, flags);
392 hsp->mask |= BIT(HSP_INT_EMPTY_SHIFT + mb->index);
393 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
395 spin_unlock_irqrestore(&hsp->lock, flags);
400 static int tegra_hsp_mailbox_flush(struct mbox_chan *chan,
401 unsigned long timeout)
403 struct tegra_hsp_mailbox *mb = chan->con_priv;
404 struct tegra_hsp_channel *ch = &mb->channel;
407 timeout = jiffies + msecs_to_jiffies(timeout);
409 while (time_before(jiffies, timeout)) {
410 value = tegra_hsp_channel_readl(ch, HSP_SM_SHRD_MBOX);
411 if ((value & HSP_SM_SHRD_MBOX_FULL) == 0) {
412 mbox_chan_txdone(chan, 0);
414 /* Wait until channel is empty */
415 if (chan->active_req != NULL)
427 static int tegra_hsp_mailbox_startup(struct mbox_chan *chan)
429 struct tegra_hsp_mailbox *mb = chan->con_priv;
430 struct tegra_hsp_channel *ch = &mb->channel;
431 struct tegra_hsp *hsp = mb->channel.hsp;
434 chan->txdone_method = TXDONE_BY_IRQ;
437 * Shared mailboxes start out as consumers by default. FULL and EMPTY
438 * interrupts are coalesced at the same shared interrupt.
440 * Keep EMPTY interrupts disabled at startup and only enable them when
441 * the mailbox is actually full. This is required because the FULL and
442 * EMPTY interrupts are level-triggered, so keeping EMPTY interrupts
443 * enabled all the time would cause an interrupt storm while mailboxes
447 spin_lock_irqsave(&hsp->lock, flags);
450 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
452 hsp->mask |= BIT(HSP_INT_FULL_SHIFT + mb->index);
454 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
456 spin_unlock_irqrestore(&hsp->lock, flags);
458 if (hsp->soc->has_per_mb_ie) {
460 tegra_hsp_channel_writel(ch, 0x0,
461 HSP_SM_SHRD_MBOX_EMPTY_INT_IE);
463 tegra_hsp_channel_writel(ch, 0x1,
464 HSP_SM_SHRD_MBOX_FULL_INT_IE);
470 static void tegra_hsp_mailbox_shutdown(struct mbox_chan *chan)
472 struct tegra_hsp_mailbox *mb = chan->con_priv;
473 struct tegra_hsp_channel *ch = &mb->channel;
474 struct tegra_hsp *hsp = mb->channel.hsp;
477 if (hsp->soc->has_per_mb_ie) {
479 tegra_hsp_channel_writel(ch, 0x0,
480 HSP_SM_SHRD_MBOX_EMPTY_INT_IE);
482 tegra_hsp_channel_writel(ch, 0x0,
483 HSP_SM_SHRD_MBOX_FULL_INT_IE);
486 spin_lock_irqsave(&hsp->lock, flags);
489 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
491 hsp->mask &= ~BIT(HSP_INT_FULL_SHIFT + mb->index);
493 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
495 spin_unlock_irqrestore(&hsp->lock, flags);
498 static const struct mbox_chan_ops tegra_hsp_sm_ops = {
499 .send_data = tegra_hsp_mailbox_send_data,
500 .flush = tegra_hsp_mailbox_flush,
501 .startup = tegra_hsp_mailbox_startup,
502 .shutdown = tegra_hsp_mailbox_shutdown,
505 static struct mbox_chan *tegra_hsp_db_xlate(struct mbox_controller *mbox,
506 const struct of_phandle_args *args)
508 struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_db);
509 unsigned int type = args->args[0], master = args->args[1];
510 struct tegra_hsp_channel *channel = ERR_PTR(-ENODEV);
511 struct tegra_hsp_doorbell *db;
512 struct mbox_chan *chan;
516 if (type != TEGRA_HSP_MBOX_TYPE_DB || !hsp->doorbell_irq)
517 return ERR_PTR(-ENODEV);
519 db = tegra_hsp_doorbell_get(hsp, master);
521 channel = &db->channel;
524 return ERR_CAST(channel);
526 spin_lock_irqsave(&hsp->lock, flags);
528 for (i = 0; i < mbox->num_chans; i++) {
529 chan = &mbox->chans[i];
530 if (!chan->con_priv) {
531 channel->chan = chan;
539 spin_unlock_irqrestore(&hsp->lock, flags);
541 return chan ?: ERR_PTR(-EBUSY);
544 static struct mbox_chan *tegra_hsp_sm_xlate(struct mbox_controller *mbox,
545 const struct of_phandle_args *args)
547 struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_sm);
548 unsigned int type = args->args[0], index;
549 struct tegra_hsp_mailbox *mb;
551 index = args->args[1] & TEGRA_HSP_SM_MASK;
553 if (type != TEGRA_HSP_MBOX_TYPE_SM || !hsp->shared_irqs ||
554 index >= hsp->num_sm)
555 return ERR_PTR(-ENODEV);
557 mb = &hsp->mailboxes[index];
559 if ((args->args[1] & TEGRA_HSP_SM_FLAG_TX) == 0)
560 mb->producer = false;
564 return mb->channel.chan;
567 static int tegra_hsp_add_doorbells(struct tegra_hsp *hsp)
569 const struct tegra_hsp_db_map *map = hsp->soc->map;
570 struct tegra_hsp_channel *channel;
573 channel = tegra_hsp_doorbell_create(hsp, map->name,
574 map->master, map->index);
576 return PTR_ERR(channel);
584 static int tegra_hsp_add_mailboxes(struct tegra_hsp *hsp, struct device *dev)
588 hsp->mailboxes = devm_kcalloc(dev, hsp->num_sm, sizeof(*hsp->mailboxes),
593 for (i = 0; i < hsp->num_sm; i++) {
594 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
598 mb->channel.hsp = hsp;
599 mb->channel.regs = hsp->regs + SZ_64K + i * SZ_32K;
600 mb->channel.chan = &hsp->mbox_sm.chans[i];
601 mb->channel.chan->con_priv = mb;
607 static int tegra_hsp_request_shared_irq(struct tegra_hsp *hsp)
609 unsigned int i, irq = 0;
612 for (i = 0; i < hsp->num_si; i++) {
613 irq = hsp->shared_irqs[i];
617 err = devm_request_irq(hsp->dev, irq, tegra_hsp_shared_irq, 0,
618 dev_name(hsp->dev), hsp);
620 dev_err(hsp->dev, "failed to request interrupt: %d\n",
627 /* disable all interrupts */
628 tegra_hsp_writel(hsp, 0, HSP_INT_IE(hsp->shared_irq));
630 dev_dbg(hsp->dev, "interrupt requested: %u\n", irq);
635 if (i == hsp->num_si) {
636 dev_err(hsp->dev, "failed to find available interrupt\n");
643 static int tegra_hsp_probe(struct platform_device *pdev)
645 struct tegra_hsp *hsp;
646 struct resource *res;
651 hsp = devm_kzalloc(&pdev->dev, sizeof(*hsp), GFP_KERNEL);
655 hsp->dev = &pdev->dev;
656 hsp->soc = of_device_get_match_data(&pdev->dev);
657 INIT_LIST_HEAD(&hsp->doorbells);
658 spin_lock_init(&hsp->lock);
660 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
661 hsp->regs = devm_ioremap_resource(&pdev->dev, res);
662 if (IS_ERR(hsp->regs))
663 return PTR_ERR(hsp->regs);
665 value = tegra_hsp_readl(hsp, HSP_INT_DIMENSIONING);
666 hsp->num_sm = (value >> HSP_nSM_SHIFT) & HSP_nINT_MASK;
667 hsp->num_ss = (value >> HSP_nSS_SHIFT) & HSP_nINT_MASK;
668 hsp->num_as = (value >> HSP_nAS_SHIFT) & HSP_nINT_MASK;
669 hsp->num_db = (value >> HSP_nDB_SHIFT) & HSP_nINT_MASK;
670 hsp->num_si = (value >> HSP_nSI_SHIFT) & HSP_nINT_MASK;
672 err = platform_get_irq_byname_optional(pdev, "doorbell");
674 hsp->doorbell_irq = err;
676 if (hsp->num_si > 0) {
677 unsigned int count = 0;
679 hsp->shared_irqs = devm_kcalloc(&pdev->dev, hsp->num_si,
680 sizeof(*hsp->shared_irqs),
682 if (!hsp->shared_irqs)
685 for (i = 0; i < hsp->num_si; i++) {
688 name = kasprintf(GFP_KERNEL, "shared%u", i);
692 err = platform_get_irq_byname_optional(pdev, name);
694 hsp->shared_irqs[i] = err;
702 devm_kfree(&pdev->dev, hsp->shared_irqs);
703 hsp->shared_irqs = NULL;
707 /* setup the doorbell controller */
708 hsp->mbox_db.of_xlate = tegra_hsp_db_xlate;
709 hsp->mbox_db.num_chans = 32;
710 hsp->mbox_db.dev = &pdev->dev;
711 hsp->mbox_db.ops = &tegra_hsp_db_ops;
713 hsp->mbox_db.chans = devm_kcalloc(&pdev->dev, hsp->mbox_db.num_chans,
714 sizeof(*hsp->mbox_db.chans),
716 if (!hsp->mbox_db.chans)
719 if (hsp->doorbell_irq) {
720 err = tegra_hsp_add_doorbells(hsp);
722 dev_err(&pdev->dev, "failed to add doorbells: %d\n",
728 err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_db);
730 dev_err(&pdev->dev, "failed to register doorbell mailbox: %d\n",
735 /* setup the shared mailbox controller */
736 hsp->mbox_sm.of_xlate = tegra_hsp_sm_xlate;
737 hsp->mbox_sm.num_chans = hsp->num_sm;
738 hsp->mbox_sm.dev = &pdev->dev;
739 hsp->mbox_sm.ops = &tegra_hsp_sm_ops;
741 hsp->mbox_sm.chans = devm_kcalloc(&pdev->dev, hsp->mbox_sm.num_chans,
742 sizeof(*hsp->mbox_sm.chans),
744 if (!hsp->mbox_sm.chans)
747 if (hsp->shared_irqs) {
748 err = tegra_hsp_add_mailboxes(hsp, &pdev->dev);
750 dev_err(&pdev->dev, "failed to add mailboxes: %d\n",
756 err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_sm);
758 dev_err(&pdev->dev, "failed to register shared mailbox: %d\n",
763 platform_set_drvdata(pdev, hsp);
765 if (hsp->doorbell_irq) {
766 err = devm_request_irq(&pdev->dev, hsp->doorbell_irq,
767 tegra_hsp_doorbell_irq, IRQF_NO_SUSPEND,
768 dev_name(&pdev->dev), hsp);
771 "failed to request doorbell IRQ#%u: %d\n",
772 hsp->doorbell_irq, err);
777 if (hsp->shared_irqs) {
778 err = tegra_hsp_request_shared_irq(hsp);
786 static int __maybe_unused tegra_hsp_resume(struct device *dev)
788 struct tegra_hsp *hsp = dev_get_drvdata(dev);
790 struct tegra_hsp_doorbell *db;
792 list_for_each_entry(db, &hsp->doorbells, list) {
793 if (db && db->channel.chan)
794 tegra_hsp_doorbell_startup(db->channel.chan);
797 if (hsp->mailboxes) {
798 for (i = 0; i < hsp->num_sm; i++) {
799 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
801 if (mb->channel.chan->cl)
802 tegra_hsp_mailbox_startup(mb->channel.chan);
809 static const struct dev_pm_ops tegra_hsp_pm_ops = {
810 .resume_noirq = tegra_hsp_resume,
813 static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = {
814 { "ccplex", TEGRA_HSP_DB_MASTER_CCPLEX, HSP_DB_CCPLEX, },
815 { "bpmp", TEGRA_HSP_DB_MASTER_BPMP, HSP_DB_BPMP, },
819 static const struct tegra_hsp_soc tegra186_hsp_soc = {
820 .map = tegra186_hsp_db_map,
821 .has_per_mb_ie = false,
824 static const struct tegra_hsp_soc tegra194_hsp_soc = {
825 .map = tegra186_hsp_db_map,
826 .has_per_mb_ie = true,
829 static const struct of_device_id tegra_hsp_match[] = {
830 { .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc },
831 { .compatible = "nvidia,tegra194-hsp", .data = &tegra194_hsp_soc },
835 static struct platform_driver tegra_hsp_driver = {
838 .of_match_table = tegra_hsp_match,
839 .pm = &tegra_hsp_pm_ops,
841 .probe = tegra_hsp_probe,
844 static int __init tegra_hsp_init(void)
846 return platform_driver_register(&tegra_hsp_driver);
848 core_initcall(tegra_hsp_init);