2 * drivers/soc/tegra/pmc.c
4 * Copyright (c) 2010 Google, Inc
7 * Colin Cross <ccross@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #define pr_fmt(fmt) "tegra-pmc: " fmt
22 #include <linux/kernel.h>
23 #include <linux/clk.h>
24 #include <linux/clk/tegra.h>
25 #include <linux/debugfs.h>
26 #include <linux/delay.h>
27 #include <linux/err.h>
28 #include <linux/export.h>
29 #include <linux/init.h>
31 #include <linux/iopoll.h>
33 #include <linux/of_address.h>
34 #include <linux/of_platform.h>
35 #include <linux/platform_device.h>
36 #include <linux/pm_domain.h>
37 #include <linux/reboot.h>
38 #include <linux/reset.h>
39 #include <linux/seq_file.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
43 #include <soc/tegra/common.h>
44 #include <soc/tegra/fuse.h>
45 #include <soc/tegra/pmc.h>
48 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
49 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
50 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
51 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
52 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
53 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
54 #define PMC_CNTRL_MAIN_RST BIT(4)
56 #define DPD_SAMPLE 0x020
57 #define DPD_SAMPLE_ENABLE BIT(0)
58 #define DPD_SAMPLE_DISABLE (0 << 0)
60 #define PWRGATE_TOGGLE 0x30
61 #define PWRGATE_TOGGLE_START BIT(8)
63 #define REMOVE_CLAMPING 0x34
65 #define PWRGATE_STATUS 0x38
67 #define PMC_PWR_DET 0x48
69 #define PMC_SCRATCH0 0x50
70 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
71 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
72 #define PMC_SCRATCH0_MODE_RCM BIT(1)
73 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
74 PMC_SCRATCH0_MODE_BOOTLOADER | \
75 PMC_SCRATCH0_MODE_RCM)
77 #define PMC_CPUPWRGOOD_TIMER 0xc8
78 #define PMC_CPUPWROFF_TIMER 0xcc
80 #define PMC_PWR_DET_VALUE 0xe4
82 #define PMC_SCRATCH41 0x140
84 #define PMC_SENSOR_CTRL 0x1b0
85 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
86 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
88 #define PMC_RST_STATUS 0x1b4
89 #define PMC_RST_STATUS_POR 0
90 #define PMC_RST_STATUS_WATCHDOG 1
91 #define PMC_RST_STATUS_SENSOR 2
92 #define PMC_RST_STATUS_SW_MAIN 3
93 #define PMC_RST_STATUS_LP0 4
94 #define PMC_RST_STATUS_AOTAG 5
96 #define IO_DPD_REQ 0x1b8
97 #define IO_DPD_REQ_CODE_IDLE (0U << 30)
98 #define IO_DPD_REQ_CODE_OFF (1U << 30)
99 #define IO_DPD_REQ_CODE_ON (2U << 30)
100 #define IO_DPD_REQ_CODE_MASK (3U << 30)
102 #define IO_DPD_STATUS 0x1bc
103 #define IO_DPD2_REQ 0x1c0
104 #define IO_DPD2_STATUS 0x1c4
105 #define SEL_DPD_TIM 0x1c8
107 #define PMC_SCRATCH54 0x258
108 #define PMC_SCRATCH54_DATA_SHIFT 8
109 #define PMC_SCRATCH54_ADDR_SHIFT 0
111 #define PMC_SCRATCH55 0x25c
112 #define PMC_SCRATCH55_RESET_TEGRA BIT(31)
113 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
114 #define PMC_SCRATCH55_PINMUX_SHIFT 24
115 #define PMC_SCRATCH55_16BITOP BIT(15)
116 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
117 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
119 #define GPU_RG_CNTRL 0x2d4
121 struct tegra_powergate {
122 struct generic_pm_domain genpd;
123 struct tegra_pmc *pmc;
126 unsigned int num_clks;
127 struct reset_control **resets;
128 unsigned int num_resets;
131 struct tegra_io_pad_soc {
132 enum tegra_io_pad id;
134 unsigned int voltage;
137 struct tegra_pmc_soc {
138 unsigned int num_powergates;
139 const char *const *powergates;
140 unsigned int num_cpu_powergates;
141 const u8 *cpu_powergates;
143 bool has_tsense_reset;
146 const struct tegra_io_pad_soc *io_pads;
147 unsigned int num_io_pads;
151 * struct tegra_pmc - NVIDIA Tegra PMC
152 * @dev: pointer to PMC device structure
153 * @base: pointer to I/O remapped register region
154 * @clk: pointer to pclk clock
155 * @soc: pointer to SoC data structure
156 * @debugfs: pointer to debugfs entry
157 * @rate: currently configured rate of pclk
158 * @suspend_mode: lowest suspend mode available
159 * @cpu_good_time: CPU power good time (in microseconds)
160 * @cpu_off_time: CPU power off time (in microsecends)
161 * @core_osc_time: core power good OSC time (in microseconds)
162 * @core_pmu_time: core power good PMU time (in microseconds)
163 * @core_off_time: core power off time (in microseconds)
164 * @corereq_high: core power request is active-high
165 * @sysclkreq_high: system clock request is active-high
166 * @combined_req: combined power request for CPU & core
167 * @cpu_pwr_good_en: CPU power good signal is enabled
168 * @lp0_vec_phys: physical base address of the LP0 warm boot code
169 * @lp0_vec_size: size of the LP0 warm boot code
170 * @powergates_available: Bitmap of available power gates
171 * @powergates_lock: mutex for power gate register access
177 struct dentry *debugfs;
179 const struct tegra_pmc_soc *soc;
183 enum tegra_suspend_mode suspend_mode;
192 bool cpu_pwr_good_en;
195 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
197 struct mutex powergates_lock;
200 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
202 .suspend_mode = TEGRA_SUSPEND_NONE,
205 static inline struct tegra_powergate *
206 to_powergate(struct generic_pm_domain *domain)
208 return container_of(domain, struct tegra_powergate, genpd);
211 static u32 tegra_pmc_readl(unsigned long offset)
213 return readl(pmc->base + offset);
216 static void tegra_pmc_writel(u32 value, unsigned long offset)
218 writel(value, pmc->base + offset);
221 static inline bool tegra_powergate_state(int id)
223 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
224 return (tegra_pmc_readl(GPU_RG_CNTRL) & 0x1) == 0;
226 return (tegra_pmc_readl(PWRGATE_STATUS) & BIT(id)) != 0;
229 static inline bool tegra_powergate_is_valid(int id)
231 return (pmc->soc && pmc->soc->powergates[id]);
234 static inline bool tegra_powergate_is_available(int id)
236 return test_bit(id, pmc->powergates_available);
239 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
243 if (!pmc || !pmc->soc || !name)
246 for (i = 0; i < pmc->soc->num_powergates; i++) {
247 if (!tegra_powergate_is_valid(i))
250 if (!strcmp(name, pmc->soc->powergates[i]))
258 * tegra_powergate_set() - set the state of a partition
260 * @new_state: new state of the partition
262 static int tegra_powergate_set(unsigned int id, bool new_state)
267 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
270 mutex_lock(&pmc->powergates_lock);
272 if (tegra_powergate_state(id) == new_state) {
273 mutex_unlock(&pmc->powergates_lock);
277 tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
279 err = readx_poll_timeout(tegra_powergate_state, id, status,
280 status == new_state, 10, 100000);
282 mutex_unlock(&pmc->powergates_lock);
287 static int __tegra_powergate_remove_clamping(unsigned int id)
291 mutex_lock(&pmc->powergates_lock);
294 * On Tegra124 and later, the clamps for the GPU are controlled by a
295 * separate register (with different semantics).
297 if (id == TEGRA_POWERGATE_3D) {
298 if (pmc->soc->has_gpu_clamps) {
299 tegra_pmc_writel(0, GPU_RG_CNTRL);
305 * Tegra 2 has a bug where PCIE and VDE clamping masks are
306 * swapped relatively to the partition ids
308 if (id == TEGRA_POWERGATE_VDEC)
309 mask = (1 << TEGRA_POWERGATE_PCIE);
310 else if (id == TEGRA_POWERGATE_PCIE)
311 mask = (1 << TEGRA_POWERGATE_VDEC);
315 tegra_pmc_writel(mask, REMOVE_CLAMPING);
318 mutex_unlock(&pmc->powergates_lock);
323 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
327 for (i = 0; i < pg->num_clks; i++)
328 clk_disable_unprepare(pg->clks[i]);
331 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
336 for (i = 0; i < pg->num_clks; i++) {
337 err = clk_prepare_enable(pg->clks[i]);
346 clk_disable_unprepare(pg->clks[i]);
351 static int tegra_powergate_reset_assert(struct tegra_powergate *pg)
356 for (i = 0; i < pg->num_resets; i++) {
357 err = reset_control_assert(pg->resets[i]);
365 static int tegra_powergate_reset_deassert(struct tegra_powergate *pg)
370 for (i = 0; i < pg->num_resets; i++) {
371 err = reset_control_deassert(pg->resets[i]);
379 static int tegra_powergate_power_up(struct tegra_powergate *pg,
384 err = tegra_powergate_reset_assert(pg);
388 usleep_range(10, 20);
390 err = tegra_powergate_set(pg->id, true);
394 usleep_range(10, 20);
396 err = tegra_powergate_enable_clocks(pg);
400 usleep_range(10, 20);
402 err = __tegra_powergate_remove_clamping(pg->id);
406 usleep_range(10, 20);
408 err = tegra_powergate_reset_deassert(pg);
412 usleep_range(10, 20);
415 tegra_powergate_disable_clocks(pg);
420 tegra_powergate_disable_clocks(pg);
421 usleep_range(10, 20);
424 tegra_powergate_set(pg->id, false);
429 static int tegra_powergate_power_down(struct tegra_powergate *pg)
433 err = tegra_powergate_enable_clocks(pg);
437 usleep_range(10, 20);
439 err = tegra_powergate_reset_assert(pg);
443 usleep_range(10, 20);
445 tegra_powergate_disable_clocks(pg);
447 usleep_range(10, 20);
449 err = tegra_powergate_set(pg->id, false);
456 tegra_powergate_enable_clocks(pg);
457 usleep_range(10, 20);
458 tegra_powergate_reset_deassert(pg);
459 usleep_range(10, 20);
462 tegra_powergate_disable_clocks(pg);
467 static int tegra_genpd_power_on(struct generic_pm_domain *domain)
469 struct tegra_powergate *pg = to_powergate(domain);
472 err = tegra_powergate_power_up(pg, true);
474 pr_err("failed to turn on PM domain %s: %d\n", pg->genpd.name,
480 static int tegra_genpd_power_off(struct generic_pm_domain *domain)
482 struct tegra_powergate *pg = to_powergate(domain);
485 err = tegra_powergate_power_down(pg);
487 pr_err("failed to turn off PM domain %s: %d\n",
488 pg->genpd.name, err);
494 * tegra_powergate_power_on() - power on partition
497 int tegra_powergate_power_on(unsigned int id)
499 if (!tegra_powergate_is_available(id))
502 return tegra_powergate_set(id, true);
506 * tegra_powergate_power_off() - power off partition
509 int tegra_powergate_power_off(unsigned int id)
511 if (!tegra_powergate_is_available(id))
514 return tegra_powergate_set(id, false);
516 EXPORT_SYMBOL(tegra_powergate_power_off);
519 * tegra_powergate_is_powered() - check if partition is powered
522 int tegra_powergate_is_powered(unsigned int id)
524 if (!tegra_powergate_is_valid(id))
527 return tegra_powergate_state(id);
531 * tegra_powergate_remove_clamping() - remove power clamps for partition
534 int tegra_powergate_remove_clamping(unsigned int id)
536 if (!tegra_powergate_is_available(id))
539 return __tegra_powergate_remove_clamping(id);
541 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
544 * tegra_powergate_sequence_power_up() - power up partition
546 * @clk: clock for partition
547 * @rst: reset for partition
549 * Must be called with clk disabled, and returns with clk enabled.
551 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
552 struct reset_control *rst)
554 struct tegra_powergate pg;
557 if (!tegra_powergate_is_available(id))
566 err = tegra_powergate_power_up(&pg, false);
568 pr_err("failed to turn on partition %d: %d\n", id, err);
572 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
576 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
577 * @cpuid: CPU partition ID
579 * Returns the partition ID corresponding to the CPU partition ID or a
580 * negative error code on failure.
582 static int tegra_get_cpu_powergate_id(unsigned int cpuid)
584 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
585 return pmc->soc->cpu_powergates[cpuid];
591 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
592 * @cpuid: CPU partition ID
594 bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
598 id = tegra_get_cpu_powergate_id(cpuid);
602 return tegra_powergate_is_powered(id);
606 * tegra_pmc_cpu_power_on() - power on CPU partition
607 * @cpuid: CPU partition ID
609 int tegra_pmc_cpu_power_on(unsigned int cpuid)
613 id = tegra_get_cpu_powergate_id(cpuid);
617 return tegra_powergate_set(id, true);
621 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
622 * @cpuid: CPU partition ID
624 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
628 id = tegra_get_cpu_powergate_id(cpuid);
632 return tegra_powergate_remove_clamping(id);
634 #endif /* CONFIG_SMP */
636 static int tegra_pmc_restart_notify(struct notifier_block *this,
637 unsigned long action, void *data)
639 const char *cmd = data;
642 value = tegra_pmc_readl(PMC_SCRATCH0);
643 value &= ~PMC_SCRATCH0_MODE_MASK;
646 if (strcmp(cmd, "recovery") == 0)
647 value |= PMC_SCRATCH0_MODE_RECOVERY;
649 if (strcmp(cmd, "bootloader") == 0)
650 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
652 if (strcmp(cmd, "forced-recovery") == 0)
653 value |= PMC_SCRATCH0_MODE_RCM;
656 tegra_pmc_writel(value, PMC_SCRATCH0);
658 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
659 value = tegra_pmc_readl(PMC_CNTRL);
660 value |= PMC_CNTRL_MAIN_RST;
661 tegra_pmc_writel(value, PMC_CNTRL);
666 static struct notifier_block tegra_pmc_restart_handler = {
667 .notifier_call = tegra_pmc_restart_notify,
671 static int powergate_show(struct seq_file *s, void *data)
676 seq_printf(s, " powergate powered\n");
677 seq_printf(s, "------------------\n");
679 for (i = 0; i < pmc->soc->num_powergates; i++) {
680 status = tegra_powergate_is_powered(i);
684 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
685 status ? "yes" : "no");
691 static int powergate_open(struct inode *inode, struct file *file)
693 return single_open(file, powergate_show, inode->i_private);
696 static const struct file_operations powergate_fops = {
697 .open = powergate_open,
700 .release = single_release,
703 static int tegra_powergate_debugfs_init(void)
705 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
713 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
714 struct device_node *np)
717 unsigned int i, count;
720 count = of_count_phandle_with_args(np, "clocks", "#clock-cells");
724 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
728 for (i = 0; i < count; i++) {
729 pg->clks[i] = of_clk_get(np, i);
730 if (IS_ERR(pg->clks[i])) {
731 err = PTR_ERR(pg->clks[i]);
736 pg->num_clks = count;
742 clk_put(pg->clks[i]);
749 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
750 struct device_node *np, bool off)
752 struct reset_control *rst;
753 unsigned int i, count;
756 count = of_count_phandle_with_args(np, "resets", "#reset-cells");
760 pg->resets = kcalloc(count, sizeof(rst), GFP_KERNEL);
764 for (i = 0; i < count; i++) {
765 pg->resets[i] = of_reset_control_get_by_index(np, i);
766 if (IS_ERR(pg->resets[i])) {
767 err = PTR_ERR(pg->resets[i]);
772 err = reset_control_assert(pg->resets[i]);
774 err = reset_control_deassert(pg->resets[i]);
777 reset_control_put(pg->resets[i]);
782 pg->num_resets = count;
788 reset_control_put(pg->resets[i]);
795 static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
797 struct tegra_powergate *pg;
801 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
805 id = tegra_powergate_lookup(pmc, np->name);
807 pr_err("powergate lookup failed for %s: %d\n", np->name, id);
812 * Clear the bit for this powergate so it cannot be managed
813 * directly via the legacy APIs for controlling powergates.
815 clear_bit(id, pmc->powergates_available);
818 pg->genpd.name = np->name;
819 pg->genpd.power_off = tegra_genpd_power_off;
820 pg->genpd.power_on = tegra_genpd_power_on;
823 off = !tegra_powergate_is_powered(pg->id);
825 err = tegra_powergate_of_get_clks(pg, np);
827 pr_err("failed to get clocks for %s: %d\n", np->name, err);
831 err = tegra_powergate_of_get_resets(pg, np, off);
833 pr_err("failed to get resets for %s: %d\n", np->name, err);
837 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
839 WARN_ON(tegra_powergate_power_up(pg, true));
845 * FIXME: If XHCI is enabled for Tegra, then power-up the XUSB
846 * host and super-speed partitions. Once the XHCI driver
847 * manages the partitions itself this code can be removed. Note
848 * that we don't register these partitions with the genpd core
849 * to avoid it from powering down the partitions as they appear
852 if (IS_ENABLED(CONFIG_USB_XHCI_TEGRA) &&
853 (id == TEGRA_POWERGATE_XUSBA || id == TEGRA_POWERGATE_XUSBC)) {
855 WARN_ON(tegra_powergate_power_up(pg, true));
860 err = pm_genpd_init(&pg->genpd, NULL, off);
862 pr_err("failed to initialise PM domain %s: %d\n", np->name,
867 err = of_genpd_add_provider_simple(np, &pg->genpd);
869 pr_err("failed to add PM domain provider for %s: %d\n",
874 pr_debug("added PM domain %s\n", pg->genpd.name);
879 pm_genpd_remove(&pg->genpd);
882 while (pg->num_resets--)
883 reset_control_put(pg->resets[pg->num_resets]);
888 while (pg->num_clks--)
889 clk_put(pg->clks[pg->num_clks]);
894 set_bit(id, pmc->powergates_available);
900 static void tegra_powergate_init(struct tegra_pmc *pmc,
901 struct device_node *parent)
903 struct device_node *np, *child;
906 /* Create a bitmap of the available and valid partitions */
907 for (i = 0; i < pmc->soc->num_powergates; i++)
908 if (pmc->soc->powergates[i])
909 set_bit(i, pmc->powergates_available);
911 np = of_get_child_by_name(parent, "powergates");
915 for_each_child_of_node(np, child)
916 tegra_powergate_add(pmc, child);
921 static const struct tegra_io_pad_soc *
922 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
926 for (i = 0; i < pmc->soc->num_io_pads; i++)
927 if (pmc->soc->io_pads[i].id == id)
928 return &pmc->soc->io_pads[i];
933 static int tegra_io_pad_prepare(enum tegra_io_pad id, unsigned long *request,
934 unsigned long *status, u32 *mask)
936 const struct tegra_io_pad_soc *pad;
937 unsigned long rate, value;
939 pad = tegra_io_pad_find(pmc, id);
941 pr_err("invalid I/O pad ID %u\n", id);
945 if (pad->dpd == UINT_MAX)
948 *mask = BIT(pad->dpd % 32);
951 *status = IO_DPD_STATUS;
952 *request = IO_DPD_REQ;
954 *status = IO_DPD2_STATUS;
955 *request = IO_DPD2_REQ;
958 rate = clk_get_rate(pmc->clk);
960 pr_err("failed to get clock rate\n");
964 tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE);
966 /* must be at least 200 ns, in APB (PCLK) clock cycles */
967 value = DIV_ROUND_UP(1000000000, rate);
968 value = DIV_ROUND_UP(200, value);
969 tegra_pmc_writel(value, SEL_DPD_TIM);
974 static int tegra_io_pad_poll(unsigned long offset, u32 mask,
975 u32 val, unsigned long timeout)
979 timeout = jiffies + msecs_to_jiffies(timeout);
981 while (time_after(timeout, jiffies)) {
982 value = tegra_pmc_readl(offset);
983 if ((value & mask) == val)
986 usleep_range(250, 1000);
992 static void tegra_io_pad_unprepare(void)
994 tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE);
998 * tegra_io_pad_power_enable() - enable power to I/O pad
999 * @id: Tegra I/O pad ID for which to enable power
1001 * Returns: 0 on success or a negative error code on failure.
1003 int tegra_io_pad_power_enable(enum tegra_io_pad id)
1005 unsigned long request, status;
1009 mutex_lock(&pmc->powergates_lock);
1011 err = tegra_io_pad_prepare(id, &request, &status, &mask);
1013 pr_err("failed to prepare I/O pad: %d\n", err);
1017 tegra_pmc_writel(IO_DPD_REQ_CODE_OFF | mask, request);
1019 err = tegra_io_pad_poll(status, mask, 0, 250);
1021 pr_err("failed to enable I/O pad: %d\n", err);
1025 tegra_io_pad_unprepare();
1028 mutex_unlock(&pmc->powergates_lock);
1031 EXPORT_SYMBOL(tegra_io_pad_power_enable);
1034 * tegra_io_pad_power_disable() - disable power to I/O pad
1035 * @id: Tegra I/O pad ID for which to disable power
1037 * Returns: 0 on success or a negative error code on failure.
1039 int tegra_io_pad_power_disable(enum tegra_io_pad id)
1041 unsigned long request, status;
1045 mutex_lock(&pmc->powergates_lock);
1047 err = tegra_io_pad_prepare(id, &request, &status, &mask);
1049 pr_err("failed to prepare I/O pad: %d\n", err);
1053 tegra_pmc_writel(IO_DPD_REQ_CODE_ON | mask, request);
1055 err = tegra_io_pad_poll(status, mask, mask, 250);
1057 pr_err("failed to disable I/O pad: %d\n", err);
1061 tegra_io_pad_unprepare();
1064 mutex_unlock(&pmc->powergates_lock);
1067 EXPORT_SYMBOL(tegra_io_pad_power_disable);
1069 int tegra_io_pad_set_voltage(enum tegra_io_pad id,
1070 enum tegra_io_pad_voltage voltage)
1072 const struct tegra_io_pad_soc *pad;
1075 pad = tegra_io_pad_find(pmc, id);
1079 if (pad->voltage == UINT_MAX)
1082 mutex_lock(&pmc->powergates_lock);
1084 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
1085 value = tegra_pmc_readl(PMC_PWR_DET);
1086 value |= BIT(pad->voltage);
1087 tegra_pmc_writel(value, PMC_PWR_DET);
1089 /* update I/O voltage */
1090 value = tegra_pmc_readl(PMC_PWR_DET_VALUE);
1092 if (voltage == TEGRA_IO_PAD_1800000UV)
1093 value &= ~BIT(pad->voltage);
1095 value |= BIT(pad->voltage);
1097 tegra_pmc_writel(value, PMC_PWR_DET_VALUE);
1099 mutex_unlock(&pmc->powergates_lock);
1101 usleep_range(100, 250);
1105 EXPORT_SYMBOL(tegra_io_pad_set_voltage);
1107 int tegra_io_pad_get_voltage(enum tegra_io_pad id)
1109 const struct tegra_io_pad_soc *pad;
1112 pad = tegra_io_pad_find(pmc, id);
1116 if (pad->voltage == UINT_MAX)
1119 value = tegra_pmc_readl(PMC_PWR_DET_VALUE);
1121 if ((value & BIT(pad->voltage)) == 0)
1122 return TEGRA_IO_PAD_1800000UV;
1124 return TEGRA_IO_PAD_3300000UV;
1126 EXPORT_SYMBOL(tegra_io_pad_get_voltage);
1129 * tegra_io_rail_power_on() - enable power to I/O rail
1130 * @id: Tegra I/O pad ID for which to enable power
1132 * See also: tegra_io_pad_power_enable()
1134 int tegra_io_rail_power_on(unsigned int id)
1136 return tegra_io_pad_power_enable(id);
1138 EXPORT_SYMBOL(tegra_io_rail_power_on);
1141 * tegra_io_rail_power_off() - disable power to I/O rail
1142 * @id: Tegra I/O pad ID for which to disable power
1144 * See also: tegra_io_pad_power_disable()
1146 int tegra_io_rail_power_off(unsigned int id)
1148 return tegra_io_pad_power_disable(id);
1150 EXPORT_SYMBOL(tegra_io_rail_power_off);
1152 #ifdef CONFIG_PM_SLEEP
1153 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1155 return pmc->suspend_mode;
1158 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1160 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1163 pmc->suspend_mode = mode;
1166 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1168 unsigned long long rate = 0;
1172 case TEGRA_SUSPEND_LP1:
1176 case TEGRA_SUSPEND_LP2:
1177 rate = clk_get_rate(pmc->clk);
1184 if (WARN_ON_ONCE(rate == 0))
1187 if (rate != pmc->rate) {
1190 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1191 do_div(ticks, USEC_PER_SEC);
1192 tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER);
1194 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1195 do_div(ticks, USEC_PER_SEC);
1196 tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER);
1203 value = tegra_pmc_readl(PMC_CNTRL);
1204 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1205 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1206 tegra_pmc_writel(value, PMC_CNTRL);
1210 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1212 u32 value, values[2];
1214 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1218 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1222 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1226 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1230 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1235 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1237 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1238 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1240 pmc->cpu_good_time = value;
1242 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1243 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1245 pmc->cpu_off_time = value;
1247 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1248 values, ARRAY_SIZE(values)))
1249 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1251 pmc->core_osc_time = values[0];
1252 pmc->core_pmu_time = values[1];
1254 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1255 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1257 pmc->core_off_time = value;
1259 pmc->corereq_high = of_property_read_bool(np,
1260 "nvidia,core-power-req-active-high");
1262 pmc->sysclkreq_high = of_property_read_bool(np,
1263 "nvidia,sys-clock-req-active-high");
1265 pmc->combined_req = of_property_read_bool(np,
1266 "nvidia,combined-power-req");
1268 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1269 "nvidia,cpu-pwr-good-en");
1271 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1272 ARRAY_SIZE(values)))
1273 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1274 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1276 pmc->lp0_vec_phys = values[0];
1277 pmc->lp0_vec_size = values[1];
1282 static void tegra_pmc_init(struct tegra_pmc *pmc)
1286 /* Always enable CPU power request */
1287 value = tegra_pmc_readl(PMC_CNTRL);
1288 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1289 tegra_pmc_writel(value, PMC_CNTRL);
1291 value = tegra_pmc_readl(PMC_CNTRL);
1293 if (pmc->sysclkreq_high)
1294 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
1296 value |= PMC_CNTRL_SYSCLK_POLARITY;
1298 /* configure the output polarity while the request is tristated */
1299 tegra_pmc_writel(value, PMC_CNTRL);
1301 /* now enable the request */
1302 value = tegra_pmc_readl(PMC_CNTRL);
1303 value |= PMC_CNTRL_SYSCLK_OE;
1304 tegra_pmc_writel(value, PMC_CNTRL);
1307 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1309 static const char disabled[] = "emergency thermal reset disabled";
1310 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1311 struct device *dev = pmc->dev;
1312 struct device_node *np;
1313 u32 value, checksum;
1315 if (!pmc->soc->has_tsense_reset)
1318 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip");
1320 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1324 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1325 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1329 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1330 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1334 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) {
1335 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1339 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) {
1340 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
1344 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
1347 value = tegra_pmc_readl(PMC_SENSOR_CTRL);
1348 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1349 tegra_pmc_writel(value, PMC_SENSOR_CTRL);
1351 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
1352 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
1353 tegra_pmc_writel(value, PMC_SCRATCH54);
1355 value = PMC_SCRATCH55_RESET_TEGRA;
1356 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
1357 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
1358 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
1361 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
1362 * contain the checksum and are currently zero, so they are not added.
1364 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
1365 + ((value >> 24) & 0xff);
1367 checksum = 0x100 - checksum;
1369 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
1371 tegra_pmc_writel(value, PMC_SCRATCH55);
1373 value = tegra_pmc_readl(PMC_SENSOR_CTRL);
1374 value |= PMC_SENSOR_CTRL_ENABLE_RST;
1375 tegra_pmc_writel(value, PMC_SENSOR_CTRL);
1377 dev_info(pmc->dev, "emergency thermal reset enabled\n");
1383 static int tegra_pmc_probe(struct platform_device *pdev)
1386 struct resource *res;
1390 * Early initialisation should have configured an initial
1391 * register mapping and setup the soc data pointer. If these
1392 * are not valid then something went badly wrong!
1394 if (WARN_ON(!pmc->base || !pmc->soc))
1397 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
1401 /* take over the memory region from the early initialization */
1402 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1403 base = devm_ioremap_resource(&pdev->dev, res);
1405 return PTR_ERR(base);
1407 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
1408 if (IS_ERR(pmc->clk)) {
1409 err = PTR_ERR(pmc->clk);
1410 dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
1414 pmc->dev = &pdev->dev;
1416 tegra_pmc_init(pmc);
1418 tegra_pmc_init_tsense_reset(pmc);
1420 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1421 err = tegra_powergate_debugfs_init();
1426 err = register_restart_handler(&tegra_pmc_restart_handler);
1428 debugfs_remove(pmc->debugfs);
1429 dev_err(&pdev->dev, "unable to register restart handler, %d\n",
1434 mutex_lock(&pmc->powergates_lock);
1437 mutex_unlock(&pmc->powergates_lock);
1442 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
1443 static int tegra_pmc_suspend(struct device *dev)
1445 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41);
1450 static int tegra_pmc_resume(struct device *dev)
1452 tegra_pmc_writel(0x0, PMC_SCRATCH41);
1457 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
1461 static const char * const tegra20_powergates[] = {
1462 [TEGRA_POWERGATE_CPU] = "cpu",
1463 [TEGRA_POWERGATE_3D] = "3d",
1464 [TEGRA_POWERGATE_VENC] = "venc",
1465 [TEGRA_POWERGATE_VDEC] = "vdec",
1466 [TEGRA_POWERGATE_PCIE] = "pcie",
1467 [TEGRA_POWERGATE_L2] = "l2",
1468 [TEGRA_POWERGATE_MPE] = "mpe",
1471 static const struct tegra_pmc_soc tegra20_pmc_soc = {
1472 .num_powergates = ARRAY_SIZE(tegra20_powergates),
1473 .powergates = tegra20_powergates,
1474 .num_cpu_powergates = 0,
1475 .cpu_powergates = NULL,
1476 .has_tsense_reset = false,
1477 .has_gpu_clamps = false,
1480 static const char * const tegra30_powergates[] = {
1481 [TEGRA_POWERGATE_CPU] = "cpu0",
1482 [TEGRA_POWERGATE_3D] = "3d0",
1483 [TEGRA_POWERGATE_VENC] = "venc",
1484 [TEGRA_POWERGATE_VDEC] = "vdec",
1485 [TEGRA_POWERGATE_PCIE] = "pcie",
1486 [TEGRA_POWERGATE_L2] = "l2",
1487 [TEGRA_POWERGATE_MPE] = "mpe",
1488 [TEGRA_POWERGATE_HEG] = "heg",
1489 [TEGRA_POWERGATE_SATA] = "sata",
1490 [TEGRA_POWERGATE_CPU1] = "cpu1",
1491 [TEGRA_POWERGATE_CPU2] = "cpu2",
1492 [TEGRA_POWERGATE_CPU3] = "cpu3",
1493 [TEGRA_POWERGATE_CELP] = "celp",
1494 [TEGRA_POWERGATE_3D1] = "3d1",
1497 static const u8 tegra30_cpu_powergates[] = {
1498 TEGRA_POWERGATE_CPU,
1499 TEGRA_POWERGATE_CPU1,
1500 TEGRA_POWERGATE_CPU2,
1501 TEGRA_POWERGATE_CPU3,
1504 static const struct tegra_pmc_soc tegra30_pmc_soc = {
1505 .num_powergates = ARRAY_SIZE(tegra30_powergates),
1506 .powergates = tegra30_powergates,
1507 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
1508 .cpu_powergates = tegra30_cpu_powergates,
1509 .has_tsense_reset = true,
1510 .has_gpu_clamps = false,
1513 static const char * const tegra114_powergates[] = {
1514 [TEGRA_POWERGATE_CPU] = "crail",
1515 [TEGRA_POWERGATE_3D] = "3d",
1516 [TEGRA_POWERGATE_VENC] = "venc",
1517 [TEGRA_POWERGATE_VDEC] = "vdec",
1518 [TEGRA_POWERGATE_MPE] = "mpe",
1519 [TEGRA_POWERGATE_HEG] = "heg",
1520 [TEGRA_POWERGATE_CPU1] = "cpu1",
1521 [TEGRA_POWERGATE_CPU2] = "cpu2",
1522 [TEGRA_POWERGATE_CPU3] = "cpu3",
1523 [TEGRA_POWERGATE_CELP] = "celp",
1524 [TEGRA_POWERGATE_CPU0] = "cpu0",
1525 [TEGRA_POWERGATE_C0NC] = "c0nc",
1526 [TEGRA_POWERGATE_C1NC] = "c1nc",
1527 [TEGRA_POWERGATE_DIS] = "dis",
1528 [TEGRA_POWERGATE_DISB] = "disb",
1529 [TEGRA_POWERGATE_XUSBA] = "xusba",
1530 [TEGRA_POWERGATE_XUSBB] = "xusbb",
1531 [TEGRA_POWERGATE_XUSBC] = "xusbc",
1534 static const u8 tegra114_cpu_powergates[] = {
1535 TEGRA_POWERGATE_CPU0,
1536 TEGRA_POWERGATE_CPU1,
1537 TEGRA_POWERGATE_CPU2,
1538 TEGRA_POWERGATE_CPU3,
1541 static const struct tegra_pmc_soc tegra114_pmc_soc = {
1542 .num_powergates = ARRAY_SIZE(tegra114_powergates),
1543 .powergates = tegra114_powergates,
1544 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
1545 .cpu_powergates = tegra114_cpu_powergates,
1546 .has_tsense_reset = true,
1547 .has_gpu_clamps = false,
1550 static const char * const tegra124_powergates[] = {
1551 [TEGRA_POWERGATE_CPU] = "crail",
1552 [TEGRA_POWERGATE_3D] = "3d",
1553 [TEGRA_POWERGATE_VENC] = "venc",
1554 [TEGRA_POWERGATE_PCIE] = "pcie",
1555 [TEGRA_POWERGATE_VDEC] = "vdec",
1556 [TEGRA_POWERGATE_MPE] = "mpe",
1557 [TEGRA_POWERGATE_HEG] = "heg",
1558 [TEGRA_POWERGATE_SATA] = "sata",
1559 [TEGRA_POWERGATE_CPU1] = "cpu1",
1560 [TEGRA_POWERGATE_CPU2] = "cpu2",
1561 [TEGRA_POWERGATE_CPU3] = "cpu3",
1562 [TEGRA_POWERGATE_CELP] = "celp",
1563 [TEGRA_POWERGATE_CPU0] = "cpu0",
1564 [TEGRA_POWERGATE_C0NC] = "c0nc",
1565 [TEGRA_POWERGATE_C1NC] = "c1nc",
1566 [TEGRA_POWERGATE_SOR] = "sor",
1567 [TEGRA_POWERGATE_DIS] = "dis",
1568 [TEGRA_POWERGATE_DISB] = "disb",
1569 [TEGRA_POWERGATE_XUSBA] = "xusba",
1570 [TEGRA_POWERGATE_XUSBB] = "xusbb",
1571 [TEGRA_POWERGATE_XUSBC] = "xusbc",
1572 [TEGRA_POWERGATE_VIC] = "vic",
1573 [TEGRA_POWERGATE_IRAM] = "iram",
1576 static const u8 tegra124_cpu_powergates[] = {
1577 TEGRA_POWERGATE_CPU0,
1578 TEGRA_POWERGATE_CPU1,
1579 TEGRA_POWERGATE_CPU2,
1580 TEGRA_POWERGATE_CPU3,
1583 static const struct tegra_io_pad_soc tegra124_io_pads[] = {
1584 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX },
1585 { .id = TEGRA_IO_PAD_BB, .dpd = 15, .voltage = UINT_MAX },
1586 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = UINT_MAX },
1587 { .id = TEGRA_IO_PAD_COMP, .dpd = 22, .voltage = UINT_MAX },
1588 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
1589 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
1590 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX },
1591 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
1592 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX },
1593 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX },
1594 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX },
1595 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX },
1596 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
1597 { .id = TEGRA_IO_PAD_HV, .dpd = 38, .voltage = UINT_MAX },
1598 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX },
1599 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
1600 { .id = TEGRA_IO_PAD_NAND, .dpd = 13, .voltage = UINT_MAX },
1601 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX },
1602 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX },
1603 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
1604 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX },
1605 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = UINT_MAX },
1606 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = UINT_MAX },
1607 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 35, .voltage = UINT_MAX },
1608 { .id = TEGRA_IO_PAD_SYS_DDC, .dpd = 58, .voltage = UINT_MAX },
1609 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX },
1610 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
1611 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
1612 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
1613 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
1616 static const struct tegra_pmc_soc tegra124_pmc_soc = {
1617 .num_powergates = ARRAY_SIZE(tegra124_powergates),
1618 .powergates = tegra124_powergates,
1619 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
1620 .cpu_powergates = tegra124_cpu_powergates,
1621 .has_tsense_reset = true,
1622 .has_gpu_clamps = true,
1623 .num_io_pads = ARRAY_SIZE(tegra124_io_pads),
1624 .io_pads = tegra124_io_pads,
1627 static const char * const tegra210_powergates[] = {
1628 [TEGRA_POWERGATE_CPU] = "crail",
1629 [TEGRA_POWERGATE_3D] = "3d",
1630 [TEGRA_POWERGATE_VENC] = "venc",
1631 [TEGRA_POWERGATE_PCIE] = "pcie",
1632 [TEGRA_POWERGATE_MPE] = "mpe",
1633 [TEGRA_POWERGATE_SATA] = "sata",
1634 [TEGRA_POWERGATE_CPU1] = "cpu1",
1635 [TEGRA_POWERGATE_CPU2] = "cpu2",
1636 [TEGRA_POWERGATE_CPU3] = "cpu3",
1637 [TEGRA_POWERGATE_CPU0] = "cpu0",
1638 [TEGRA_POWERGATE_C0NC] = "c0nc",
1639 [TEGRA_POWERGATE_SOR] = "sor",
1640 [TEGRA_POWERGATE_DIS] = "dis",
1641 [TEGRA_POWERGATE_DISB] = "disb",
1642 [TEGRA_POWERGATE_XUSBA] = "xusba",
1643 [TEGRA_POWERGATE_XUSBB] = "xusbb",
1644 [TEGRA_POWERGATE_XUSBC] = "xusbc",
1645 [TEGRA_POWERGATE_VIC] = "vic",
1646 [TEGRA_POWERGATE_IRAM] = "iram",
1647 [TEGRA_POWERGATE_NVDEC] = "nvdec",
1648 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
1649 [TEGRA_POWERGATE_AUD] = "aud",
1650 [TEGRA_POWERGATE_DFD] = "dfd",
1651 [TEGRA_POWERGATE_VE2] = "ve2",
1654 static const u8 tegra210_cpu_powergates[] = {
1655 TEGRA_POWERGATE_CPU0,
1656 TEGRA_POWERGATE_CPU1,
1657 TEGRA_POWERGATE_CPU2,
1658 TEGRA_POWERGATE_CPU3,
1661 static const struct tegra_io_pad_soc tegra210_io_pads[] = {
1662 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = 5 },
1663 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = 18 },
1664 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = 10 },
1665 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
1666 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
1667 { .id = TEGRA_IO_PAD_CSIC, .dpd = 42, .voltage = UINT_MAX },
1668 { .id = TEGRA_IO_PAD_CSID, .dpd = 43, .voltage = UINT_MAX },
1669 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX },
1670 { .id = TEGRA_IO_PAD_CSIF, .dpd = 45, .voltage = UINT_MAX },
1671 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = 19 },
1672 { .id = TEGRA_IO_PAD_DEBUG_NONAO, .dpd = 26, .voltage = UINT_MAX },
1673 { .id = TEGRA_IO_PAD_DMIC, .dpd = 50, .voltage = 20 },
1674 { .id = TEGRA_IO_PAD_DP, .dpd = 51, .voltage = UINT_MAX },
1675 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
1676 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX },
1677 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX },
1678 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX },
1679 { .id = TEGRA_IO_PAD_EMMC, .dpd = 35, .voltage = UINT_MAX },
1680 { .id = TEGRA_IO_PAD_EMMC2, .dpd = 37, .voltage = UINT_MAX },
1681 { .id = TEGRA_IO_PAD_GPIO, .dpd = 27, .voltage = 21 },
1682 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX },
1683 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
1684 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX },
1685 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
1686 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX },
1687 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX },
1688 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
1689 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = UINT_MAX, .voltage = 11 },
1690 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = 12 },
1691 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = 13 },
1692 { .id = TEGRA_IO_PAD_SPI, .dpd = 46, .voltage = 22 },
1693 { .id = TEGRA_IO_PAD_SPI_HV, .dpd = 47, .voltage = 23 },
1694 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = 2 },
1695 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
1696 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
1697 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
1698 { .id = TEGRA_IO_PAD_USB3, .dpd = 18, .voltage = UINT_MAX },
1699 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
1702 static const struct tegra_pmc_soc tegra210_pmc_soc = {
1703 .num_powergates = ARRAY_SIZE(tegra210_powergates),
1704 .powergates = tegra210_powergates,
1705 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
1706 .cpu_powergates = tegra210_cpu_powergates,
1707 .has_tsense_reset = true,
1708 .has_gpu_clamps = true,
1709 .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
1710 .io_pads = tegra210_io_pads,
1713 static const struct of_device_id tegra_pmc_match[] = {
1714 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
1715 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
1716 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
1717 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
1718 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
1719 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
1723 static struct platform_driver tegra_pmc_driver = {
1725 .name = "tegra-pmc",
1726 .suppress_bind_attrs = true,
1727 .of_match_table = tegra_pmc_match,
1728 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
1729 .pm = &tegra_pmc_pm_ops,
1732 .probe = tegra_pmc_probe,
1734 builtin_platform_driver(tegra_pmc_driver);
1737 * Early initialization to allow access to registers in the very early boot
1740 static int __init tegra_pmc_early_init(void)
1742 const struct of_device_id *match;
1743 struct device_node *np;
1744 struct resource regs;
1748 mutex_init(&pmc->powergates_lock);
1750 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
1753 * Fall back to legacy initialization for 32-bit ARM only. All
1754 * 64-bit ARM device tree files for Tegra are required to have
1757 * This is for backwards-compatibility with old device trees
1758 * that didn't contain a PMC node. Note that in this case the
1759 * SoC data can't be matched and therefore powergating is
1762 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
1763 pr_warn("DT node not found, powergating disabled\n");
1765 regs.start = 0x7000e400;
1766 regs.end = 0x7000e7ff;
1767 regs.flags = IORESOURCE_MEM;
1769 pr_warn("Using memory region %pR\n", ®s);
1772 * At this point we're not running on Tegra, so play
1773 * nice with multi-platform kernels.
1779 * Extract information from the device tree if we've found a
1782 if (of_address_to_resource(np, 0, ®s) < 0) {
1783 pr_err("failed to get PMC registers\n");
1789 pmc->base = ioremap_nocache(regs.start, resource_size(®s));
1791 pr_err("failed to map PMC registers\n");
1797 pmc->soc = match->data;
1799 tegra_powergate_init(pmc, np);
1802 * Invert the interrupt polarity if a PMC device tree node
1803 * exists and contains the nvidia,invert-interrupt property.
1805 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
1807 value = tegra_pmc_readl(PMC_CNTRL);
1810 value |= PMC_CNTRL_INTR_POLARITY;
1812 value &= ~PMC_CNTRL_INTR_POLARITY;
1814 tegra_pmc_writel(value, PMC_CNTRL);
1821 early_initcall(tegra_pmc_early_init);