2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
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6 * modification, are permitted (subject to the limitations in the
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13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
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28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 /* Please make sure the size of ALL headers is on word alignment */
40 #define M_FF 0x02 /* fast frame */
42 #define RX_STATS_SIZE 10
44 struct rx_frame_header {
45 a_uint32_t rx_stats[RX_STATS_SIZE];
48 #define ATH_DATA_TYPE_AGGR 0x1
49 #define ATH_DATA_TYPE_NON_AGGR 0x2
50 #define ATH_SHORT_PREAMBLE 0x1
52 typedef struct _mgt_header {
61 } POSTPACK ath_mgt_hdr_t;
63 typedef struct _beacon_header {
65 a_uint8_t len_changed;
69 #define M_LINK0 0x01 /* frame needs WEP encryption */
70 #define M_UAPSD 0x08 /* frame flagged for u-apsd handling */
72 /* Tx frame header flags definition */
73 //Reserved bit-0 for selfCTS
74 //Reserved bit-1 for RTS
75 #define TFH_FLAGS_USE_MIN_RATE 0x100
77 typedef struct __data_header {
87 } POSTPACK ath_data_hdr_t;
89 #define RX_HEADER_SPACE HTC_HDR_LENGTH + sizeof(struct rx_frame_header)
91 struct ieee80211com_target {
92 a_uint32_t ic_ampdu_limit;
93 a_uint8_t ic_ampdu_subframes;
94 a_uint8_t ic_enable_coex;
95 a_uint8_t ic_tx_chainmask;
99 #define ATH_NODE_MAX 8 /* max no. of nodes */
100 #define ATH_VAP_MAX 2 /* max no. of vaps */
102 #define VAP_TARGET_SIZE 12
104 struct ieee80211vap_target
106 a_uint8_t iv_vapindex;
107 a_uint8_t iv_opmode; /* enum ieee80211_opmode */
108 a_uint8_t iv_myaddr[IEEE80211_ADDR_LEN];
109 a_uint8_t iv_ath_cap;
110 a_uint16_t iv_rtsthreshold;
114 a_uint8_t iv_nodeindex;
115 struct ieee80211_node_target *iv_bss;
118 /* NB: this must have the same value as IEEE80211_FC1_PWR_MGT */
119 #define IEEE80211_NODE_PWR_MGT 0x0010 /* power save mode enabled */
120 #define IEEE80211_NODE_AREF 0x0020 /* authentication ref held */
121 #define IEEE80211_NODE_UAPSD 0x0040 /* U-APSD power save enabled */
122 #define IEEE80211_NODE_UAPSD_TRIG 0x0080 /* U-APSD triggerable state */
123 #define IEEE80211_NODE_UAPSD_SP 0x0100 /* U-APSD SP in progress */
124 #define IEEE80211_NODE_ATH 0x0200 /* Atheros Owl or follow-on device */
125 #define IEEE80211_NODE_OWL_WORKAROUND 0x0400 /* Owl WDS workaround needed*/
126 #define IEEE80211_NODE_WDS 0x0800 /* WDS link */
128 #define NODE_TARGET_SIZE 22
130 struct ieee80211_node_target
132 a_uint8_t ni_macaddr[IEEE80211_ADDR_LEN];
133 a_uint8_t ni_bssid[IEEE80211_ADDR_LEN];
134 a_uint8_t ni_nodeindex;
135 a_uint8_t ni_vapindex;
136 a_uint8_t ni_is_vapnode;
139 a_uint16_t ni_maxampdu;
144 * Should move to ath_node_target later on ...
146 a_uint16_t ni_txseqmgmt;
149 struct ieee80211vap_target *ni_vap;
152 struct ath_interrupt_stats {
154 a_uint32_t ast_rxorn;
155 a_uint32_t ast_rxeol;
156 a_uint32_t ast_txurn;
161 struct ath_tx_stats {
162 a_uint32_t ast_tx_xretries; /* tx failed 'cuz too many retries */
163 a_uint32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */
164 a_uint32_t ast_tx_filtered; /* tx failed 'cuz xmit filtered */
165 a_uint32_t ast_tx_timer_exp; /* tx timer expired */
166 a_uint32_t ast_tx_shortretry; /* tx on-chip retries (short) */
167 a_uint32_t ast_tx_longretry; /* tx on-chip retries (long) */
169 a_uint32_t ast_tx_rts; /* tx frames with rts enabled */
170 a_uint32_t ast_tx_altrate; /* tx frames with alternate rate */
171 a_uint32_t ast_tx_protect; /* tx frames with protection */
173 a_uint32_t tx_tgt; /* tx data pkts recieved on target */
174 a_uint32_t tx_qnull; /* txq empty occurences */
176 a_uint32_t txaggr_nframes; /* no. of frames aggregated */
177 a_uint32_t tx_compunaggr; /* tx unaggregated frame completions */
178 a_uint32_t tx_compaggr; /* tx aggregated completions */
179 a_uint32_t txaggr_retries; /* tx retries of sub frames */
180 a_uint32_t txaggr_single; /* tx frames not aggregated */
181 a_uint32_t txaggr_compgood; /* tx aggr good completions */
182 a_uint32_t txaggr_compretries; /* tx aggr unacked subframes */
183 a_uint32_t txaggr_prepends; /* tx aggr old frames requeued */
184 a_uint32_t txaggr_data_urun; /* data underrun for an aggregate */
185 a_uint32_t txaggr_delim_urun; /* delimiter underrun for an aggr */
186 a_uint32_t txaggr_errlast; /* tx aggr: last sub-frame failed */
187 a_uint32_t txaggr_longretries; /* tx aggr h/w long retries */
188 a_uint32_t txaggr_babug; /* tx aggr : BA bug */
189 a_uint32_t txaggr_compxretry; /* tx aggr excessive retries */
190 a_uint32_t txaggr_shortretries;/* tx aggr h/w short retries */
191 a_uint32_t txaggr_timer_exp; /* tx aggr : tx timer expired */
192 a_uint32_t txunaggr_compretries; /* tx non-aggr unacked subframes */
193 a_uint32_t txaggr_filtered; /* filtered aggr packet */
194 a_uint32_t txaggr_fifo; /* fifo underrun of aggregate */
195 a_uint32_t txaggr_xtxop; /* txop exceeded for an aggregate */
196 a_uint32_t txaggr_desc_cfgerr; /* aggr descriptor config error */
197 a_uint32_t txunaggr_errlast; /* tx non-aggr: last frame failed */
198 a_uint32_t txunaggr_xretry; /* tx unaggregated excessive retries */
199 a_uint32_t txaggr_xretries; /* tx excessive retries of aggr */
201 a_uint32_t tx_stopfiltered; /* tx pkts filtered for requeueing */
202 a_uint32_t tx_noskbs; /* tx no skbs for encapsulations */
203 a_uint32_t tx_nobufs; /* tx no descriptors */
205 a_uint32_t tx_bars; /* tx bars sent */
206 a_uint32_t txbar_xretry; /* tx bars excessively retried */
207 a_uint32_t txbar_compretries; /* tx bars retried */
208 a_uint32_t txbar_errlast; /* tx bars last frame failed */
211 struct ath_rx_stats {
212 a_uint32_t ast_rx_nobuf; /* rx setup failed 'cuz no skbuff */
213 a_uint32_t ast_rx_send;
214 a_uint32_t ast_rx_done;
217 struct ath_aggr_info {
220 a_uint8_t aggr_enable;
224 struct wmi_data_delba {
225 a_uint8_t ni_nodeindex;
228 a_uint8_t reasoncode;
231 struct wmi_fw_version {