2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <adf_os_types.h>
37 #include <adf_os_dma.h>
38 #include <adf_os_timer.h>
39 #include <adf_os_lock.h>
40 #include <adf_os_io.h>
41 #include <adf_os_mem.h>
42 #include <adf_os_util.h>
43 #include <adf_os_stdtypes.h>
44 #include <adf_os_defer.h>
45 #include <adf_os_atomic.h>
48 #include <adf_net_wcmd.h>
52 #ifdef USE_HEADERLEN_RESV
56 #include <ieee80211_var.h>
57 #include "if_athrate.h"
58 #include "if_athvar.h"
61 #define ath_tgt_free_skb adf_nbuf_free
63 #define OFDM_PLCP_BITS 22
64 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
65 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
71 #define HT_LTF(_ns) (4 * (_ns))
72 #define SYMBOL_TIME(_ns) ((_ns) << 2) // ns * 4 us
73 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) // ns * 3.6 us
75 static a_uint16_t bits_per_symbol[][2] = {
77 { 26, 54 }, // 0: BPSK
78 { 52, 108 }, // 1: QPSK 1/2
79 { 78, 162 }, // 2: QPSK 3/4
80 { 104, 216 }, // 3: 16-QAM 1/2
81 { 156, 324 }, // 4: 16-QAM 3/4
82 { 208, 432 }, // 5: 64-QAM 2/3
83 { 234, 486 }, // 6: 64-QAM 3/4
84 { 260, 540 }, // 7: 64-QAM 5/6
85 { 52, 108 }, // 8: BPSK
86 { 104, 216 }, // 9: QPSK 1/2
87 { 156, 324 }, // 10: QPSK 3/4
88 { 208, 432 }, // 11: 16-QAM 1/2
89 { 312, 648 }, // 12: 16-QAM 3/4
90 { 416, 864 }, // 13: 64-QAM 2/3
91 { 468, 972 }, // 14: 64-QAM 3/4
92 { 520, 1080 }, // 15: 64-QAM 5/6
95 void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,
96 owl_txq_state_t txqstate);
97 static void ath_tgt_txqaddbuf(struct ath_softc_tgt *sc, struct ath_txq *txq,
98 struct ath_tx_buf *bf, struct ath_tx_desc *lastds);
99 void ath_rate_findrate_11n_Hardcoded(struct ath_softc_tgt *sc,
100 struct ath_rc_series series[]);
101 void ath_buf_set_rate_Hardcoded(struct ath_softc_tgt *sc,
102 struct ath_tx_buf *bf) ;
103 static a_int32_t ath_tgt_txbuf_setup(struct ath_softc_tgt *sc,
104 struct ath_tx_buf *bf, ath_data_hdr_t *dh);
105 static void ath_tx_freebuf(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
106 static void ath_tx_uc_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
107 static void ath_update_stats(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
108 void adf_print_buf(adf_nbuf_t buf);
109 static void ath_tgt_tx_enqueue(struct ath_txq *txq, struct ath_atx_tid *tid);
111 void ath_tgt_tx_comp_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
112 struct ieee80211_frame *ATH_SKB_2_WH(adf_nbuf_t skb);
114 void ath_tgt_tx_send_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
116 static void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
117 static void ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
119 extern a_int32_t ath_chainmask_sel_logic(void *);
120 static a_int32_t ath_get_pktlen(struct ath_tx_buf *bf, a_int32_t hdrlen);
121 static void ath_tgt_txq_schedule(struct ath_softc_tgt *sc, struct ath_txq *txq);
123 typedef void (*ath_ft_set_atype_t)(struct ath_softc_tgt *sc, struct ath_buf *bf);
126 ath_tx_set_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
129 ath_bar_tx(struct ath_softc_tgt *sc, ath_atx_tid_t *tid, struct ath_tx_buf *bf);
131 ath_tx_update_baw(ath_atx_tid_t *tid, int seqno);
133 ath_tx_retry_subframe(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
134 ath_tx_bufhead *bf_q, struct ath_tx_buf **bar);
137 ath_tx_comp_aggr_error(struct ath_softc_tgt *sc, struct ath_tx_buf *bf, ath_atx_tid_t *tid);
139 void ath_tx_addto_baw(ath_atx_tid_t *tid, struct ath_tx_buf *bf);
140 static inline void ath_tx_retry_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
141 static void ath_tx_comp_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
142 static void ath_update_aggr_stats(struct ath_softc_tgt *sc, struct ath_tx_desc *ds,
143 int nframes, int nbad);
144 static inline void ath_aggr_resume_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
145 static void ath_tx_comp_cleanup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
147 int ath_tgt_tx_add_to_aggr(struct ath_softc_tgt *sc,
148 struct ath_buf *bf,int datatype,
149 ath_atx_tid_t *tid, int is_burst);
151 struct ieee80211_frame *ATH_SKB_2_WH(adf_nbuf_t skb)
156 adf_nbuf_peek_header(skb, &anbdata, &anblen);
158 return((struct ieee80211_frame *)anbdata);
161 #undef adf_os_cpu_to_le16
163 static a_uint16_t adf_os_cpu_to_le16(a_uint16_t x)
165 return ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8));
169 ath_aggr_resume_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
173 txq = TID_TO_ACTXQ(tid->tidno);
176 if (asf_tailq_empty(&tid->buf_q))
179 ath_tgt_tx_enqueue(txq, tid);
180 ath_tgt_txq_schedule(sc, txq);
184 ath_aggr_pause_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
189 static a_uint32_t ath_pkt_duration(struct ath_softc_tgt *sc,
190 a_uint8_t rix, struct ath_tx_buf *bf,
191 a_int32_t width, a_int32_t half_gi)
193 const HAL_RATE_TABLE *rt = sc->sc_currates;
194 a_uint32_t nbits, nsymbits, duration, nsymbols;
199 pktlen = bf->bf_isaggr ? bf->bf_al : bf->bf_pktlen;
200 rc = rt->info[rix].rateCode;
203 return ath_hal_computetxtime(sc->sc_ah, rt, pktlen, rix,
206 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
207 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
208 nsymbols = (nbits + nsymbits - 1) / nsymbits;
211 duration = SYMBOL_TIME(nsymbols);
213 duration = SYMBOL_TIME_HALFGI(nsymbols);
215 streams = HT_RC_2_STREAMS(rc);
216 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
221 static void ath_dma_map(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
223 adf_nbuf_t skb = bf->bf_skb;
225 skb = adf_nbuf_queue_first(&bf->bf_skbhead);
226 adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, skb, ADF_OS_DMA_TO_DEVICE);
229 static void ath_dma_unmap(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
231 adf_nbuf_t skb = bf->bf_skb;
233 skb = adf_nbuf_queue_first(&bf->bf_skbhead);
234 adf_nbuf_unmap( sc->sc_dev, bf->bf_dmamap, ADF_OS_DMA_TO_DEVICE);
237 static void ath_filltxdesc(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
239 struct ath_tx_desc *ds0, *ds = bf->bf_desc;
243 adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info);
245 for (i = 0; i < bf->bf_dmamap_info.nsegs; i++, ds++) {
247 ds->ds_data = bf->bf_dmamap_info.dma_segs[i].paddr;
249 if (i == (bf->bf_dmamap_info.nsegs - 1)) {
253 ds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, i+1);
255 ath_hal_filltxdesc(sc->sc_ah, ds
256 , bf->bf_dmamap_info.dma_segs[i].len
258 , i == (bf->bf_dmamap_info.nsegs - 1)
263 static void ath_tx_tgt_setds(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
265 struct ath_tx_desc *ds = bf->bf_desc;
267 switch (bf->bf_protmode) {
268 case IEEE80211_PROT_RTSCTS:
269 bf->bf_flags |= HAL_TXDESC_RTSENA;
271 case IEEE80211_PROT_CTSONLY:
272 bf->bf_flags |= HAL_TXDESC_CTSENA;
278 ath_hal_set11n_txdesc(sc->sc_ah, ds
284 , bf->bf_flags | HAL_TXDESC_INTREQ);
286 ath_filltxdesc(sc, bf);
289 static struct ath_tx_buf *ath_buf_toggle(struct ath_softc_tgt *sc,
290 struct ath_tx_buf *bf,
293 struct ath_tx_buf *tmp = NULL;
294 adf_nbuf_t buf = NULL;
296 adf_os_assert(sc->sc_txbuf_held != NULL);
298 tmp = sc->sc_txbuf_held;
301 ath_dma_unmap(sc, bf);
302 adf_nbuf_queue_init(&tmp->bf_skbhead);
303 buf = adf_nbuf_queue_remove(&bf->bf_skbhead);
305 adf_nbuf_queue_add(&tmp->bf_skbhead, buf);
307 adf_os_assert(adf_nbuf_queue_len(&bf->bf_skbhead) == 0);
309 tmp->bf_next = bf->bf_next;
310 tmp->bf_endpt = bf->bf_endpt;
311 tmp->bf_tidno = bf->bf_tidno;
312 tmp->bf_skb = bf->bf_skb;
313 tmp->bf_node = bf->bf_node;
314 tmp->bf_isaggr = bf->bf_isaggr;
315 tmp->bf_flags = bf->bf_flags;
316 tmp->bf_state = bf->bf_state;
317 tmp->bf_retries = bf->bf_retries;
318 tmp->bf_comp = bf->bf_comp;
319 tmp->bf_nframes = bf->bf_nframes;
320 tmp->bf_cookie = bf->bf_cookie;
332 ath_dma_map(sc, tmp);
333 ath_tx_tgt_setds(sc, tmp);
336 sc->sc_txbuf_held = bf;
341 static void ath_tgt_skb_free(struct ath_softc_tgt *sc,
342 adf_nbuf_queue_t *head,
343 HTC_ENDPOINT_ID endpt)
347 while (adf_nbuf_queue_len(head) != 0) {
348 tskb = adf_nbuf_queue_remove(head);
349 ath_free_tx_skb(sc->tgt_htc_handle,endpt,tskb);
353 static void ath_buf_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
355 ath_dma_unmap(sc, bf);
356 ath_tgt_skb_free(sc, &bf->bf_skbhead,bf->bf_endpt);
359 bf = ath_buf_toggle(sc, bf, 0);
361 asf_tailq_insert_tail(&sc->sc_txbuf, bf, bf_list);
365 static void ath_buf_set_rate(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
367 struct ath_hal *ah = sc->sc_ah;
368 const HAL_RATE_TABLE *rt;
369 struct ath_tx_desc *ds = bf->bf_desc;
370 HAL_11N_RATE_SERIES series[4];
372 a_uint8_t rix, cix, rtsctsrate;
373 a_uint32_t ctsduration = 0;
374 a_int32_t prot_mode = AH_FALSE;
376 rt = sc->sc_currates;
377 rix = bf->bf_rcs[0].rix;
378 flags = (bf->bf_flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA));
379 cix = rt->info[sc->sc_protrix].controlRate;
381 if (bf->bf_protmode != IEEE80211_PROT_NONE &&
382 (rt->info[rix].phy == IEEE80211_T_OFDM ||
383 rt->info[rix].phy == IEEE80211_T_HT) &&
384 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
385 cix = rt->info[sc->sc_protrix].controlRate;
388 if (ath_hal_htsupported(ah) && (!bf->bf_ismcast))
389 flags = HAL_TXDESC_RTSENA;
392 if (bf->bf_rcs[i].tries) {
393 cix = rt->info[bf->bf_rcs[i].rix].controlRate;
400 adf_os_mem_set(series, 0, sizeof(HAL_11N_RATE_SERIES) * 4);
402 for (i = 0; i < 4; i++) {
403 if (!bf->bf_rcs[i].tries)
406 rix = bf->bf_rcs[i].rix;
408 series[i].Rate = rt->info[rix].rateCode |
409 (bf->bf_shpream ? rt->info[rix].shortPreamble : 0);
411 series[i].Tries = bf->bf_rcs[i].tries;
413 series[i].RateFlags = ((bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
414 HAL_RATESERIES_RTS_CTS : 0 ) |
415 ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
416 HAL_RATESERIES_2040 : 0 ) |
417 ((bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG) ?
418 HAL_RATESERIES_HALFGI : 0 ) |
419 ((bf->bf_rcs[i].flags & ATH_RC_TX_STBC_FLAG) ?
420 HAL_RATESERIES_STBC: 0);
422 series[i].RateFlags = ((bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
423 HAL_RATESERIES_RTS_CTS : 0 ) |
424 ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
425 HAL_RATESERIES_2040 : 0 ) |
426 ((bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG) ?
427 HAL_RATESERIES_HALFGI : 0 );
429 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
430 (bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) != 0,
431 (bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG));
433 series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
436 series[i].RateFlags |= HAL_RATESERIES_RTS_CTS;
438 if (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG)
439 series[i].RateFlags |= HAL_RATESERIES_RTS_CTS;
442 rtsctsrate = rt->info[cix].rateCode |
443 (bf->bf_shpream ? rt->info[cix].shortPreamble : 0);
445 ath_hal_set11n_ratescenario(ah, ds, 1,
446 rtsctsrate, ctsduration,
451 static void ath_tgt_rate_findrate(struct ath_softc_tgt *sc,
452 struct ath_node_target *an,
453 a_int32_t shortPreamble,
459 struct ath_rc_series series[],
462 ath_rate_findrate(sc, an, 1, frameLen, 10, 4, 1,
463 ATH_RC_PROBE_ALLOWED, series, isProbe);
466 static void owl_tgt_tid_init(struct ath_atx_tid *tid)
470 tid->seq_start = tid->seq_next = 0;
471 tid->baw_size = WME_MAX_BA;
472 tid->baw_head = tid->baw_tail = 0;
475 tid->sched = AH_FALSE;
477 asf_tailq_init(&tid->buf_q);
479 for (i = 0; i < ATH_TID_MAX_BUFS; i++) {
480 TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, i);
484 static void owl_tgt_tid_cleanup(struct ath_softc_tgt *sc,
485 struct ath_atx_tid *tid)
492 tid->flag &= ~TID_CLEANUP_INPROGRES;
494 if (tid->flag & TID_REINITIALIZE) {
495 adf_os_print("TID REINIT DONE for tid %p\n", tid);
496 tid->flag &= ~TID_REINITIALIZE;
497 owl_tgt_tid_init(tid);
499 ath_aggr_resume_tid(sc, tid);
503 void owl_tgt_node_init(struct ath_node_target * an)
505 struct ath_atx_tid *tid;
508 for (tidno = 0, tid = &an->tid[tidno]; tidno < WME_NUM_TID;tidno++, tid++) {
512 if ( tid->flag & TID_CLEANUP_INPROGRES ) {
513 tid->flag |= TID_REINITIALIZE;
514 adf_os_print("tid[%p]->incomp is not 0: %d\n",
517 owl_tgt_tid_init(tid);
522 void ath_tx_status_clear(struct ath_softc_tgt *sc)
526 for (i = 0; i < 2; i++) {
527 sc->tx_status[i].cnt = 0;
531 static WMI_TXSTATUS_EVENT *ath_tx_status_get(struct ath_softc_tgt *sc)
533 WMI_TXSTATUS_EVENT *txs = NULL;
536 for (i = 0; i < 2; i++) {
537 if (sc->tx_status[i].cnt < HTC_MAX_TX_STATUS) {
538 txs = &sc->tx_status[i];
546 void ath_tx_status_update(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
548 struct ath_tx_desc *ds = bf->bf_lastds;
549 WMI_TXSTATUS_EVENT *txs;
551 if (sc->sc_tx_draining)
554 txs = ath_tx_status_get(sc);
558 txs->txstatus[txs->cnt].cookie = bf->bf_cookie;
559 txs->txstatus[txs->cnt].ts_rate = SM(bf->bf_endpt, ATH9K_HTC_TXSTAT_EPID);
561 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
562 txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_FILT;
564 if (!(ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) &&
565 !(ds->ds_txstat.ts_status & HAL_TXERR_FIFO) &&
566 !(ds->ds_txstat.ts_status & HAL_TXERR_TIMER_EXPIRED) &&
567 !(ds->ds_txstat.ts_status & HAL_TXERR_FILT))
568 txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_ACK;
570 ath_tx_status_update_rate(sc, bf->bf_rcs, ds->ds_txstat.ts_rate, txs);
575 void ath_tx_status_update_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
576 struct ath_tx_desc *ds, struct ath_rc_series rcs[],
579 WMI_TXSTATUS_EVENT *txs;
581 if (sc->sc_tx_draining)
584 txs = ath_tx_status_get(sc);
588 txs->txstatus[txs->cnt].cookie = bf->bf_cookie;
589 txs->txstatus[txs->cnt].ts_rate = SM(bf->bf_endpt, ATH9K_HTC_TXSTAT_EPID);
592 txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_ACK;
595 ath_tx_status_update_rate(sc, rcs, ds->ds_txstat.ts_rate, txs);
600 void ath_tx_status_send(struct ath_softc_tgt *sc)
604 if (sc->sc_tx_draining)
607 for (i = 0; i < 2; i++) {
608 if (sc->tx_status[i].cnt) {
609 wmi_event(sc->tgt_wmi_handle, WMI_TXSTATUS_EVENTID,
610 &sc->tx_status[i], sizeof(WMI_TXSTATUS_EVENT));
611 /* FIXME: Handle failures. */
612 sc->tx_status[i].cnt = 0;
617 static void owltgt_tx_process_cabq(struct ath_softc_tgt *sc, struct ath_txq *txq)
619 struct ath_hal *ah = sc->sc_ah;
620 ah->ah_setInterrupts(ah, sc->sc_imask & ~HAL_INT_SWBA);
621 owltgt_tx_processq(sc, txq, OWL_TXQ_ACTIVE);
622 ah->ah_setInterrupts(ah, sc->sc_imask);
625 void owl_tgt_tx_tasklet(TQUEUE_ARG data)
627 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
631 ath_tx_status_clear(sc);
633 for (i = 0; i < (HAL_NUM_TX_QUEUES - 6); i++) {
634 txq = ATH_TXQ(sc, i);
636 if (ATH_TXQ_SETUP(sc, i)) {
637 if (txq == sc->sc_cabq)
638 owltgt_tx_process_cabq(sc, txq);
640 owltgt_tx_processq(sc, txq, OWL_TXQ_ACTIVE);
644 ath_tx_status_send(sc);
647 void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,
648 owl_txq_state_t txqstate)
650 struct ath_tx_buf *bf;
651 struct ath_tx_desc *ds;
655 if (asf_tailq_empty(&txq->axq_q)) {
656 txq->axq_link = NULL;
657 txq->axq_linkbuf = NULL;
661 bf = asf_tailq_first(&txq->axq_q);
664 status = ath_hal_txprocdesc(sc->sc_ah, ds);
666 if (status == HAL_EINPROGRESS) {
667 if (txqstate == OWL_TXQ_ACTIVE)
669 else if (txqstate == OWL_TXQ_STOPPED) {
670 __stats(sc, tx_stopfiltered);
671 ds->ds_txstat.ts_flags = 0;
672 ds->ds_txstat.ts_status = HAL_OK;
674 ds->ds_txstat.ts_flags = HAL_TX_SW_FILTERED;
678 ATH_TXQ_REMOVE_HEAD(txq, bf, bf_list);
679 if ((asf_tailq_empty(&txq->axq_q))) {
680 __stats(sc, tx_qnull);
681 txq->axq_link = NULL;
682 txq->axq_linkbuf = NULL;
688 ath_tx_status_update(sc, bf);
689 ath_buf_comp(sc, bf);
692 if (txqstate == OWL_TXQ_ACTIVE) {
693 ath_tgt_txq_schedule(sc, txq);
698 static struct ieee80211_frame* ATH_SKB2_WH(adf_nbuf_t skb)
703 adf_nbuf_peek_header(skb, &anbdata, &anblen);
704 return((struct ieee80211_frame *)anbdata);
708 ath_tgt_tid_drain(struct ath_softc_tgt *sc, struct ath_atx_tid *tid)
710 struct ath_tx_buf *bf;
712 while (!asf_tailq_empty(&tid->buf_q)) {
713 TAILQ_DEQ(&tid->buf_q, bf, bf_list);
714 ath_tx_freebuf(sc, bf);
717 tid->seq_next = tid->seq_start;
718 tid->baw_tail = tid->baw_head;
721 static void ath_tgt_tx_comp_normal(struct ath_softc_tgt *sc,
722 struct ath_tx_buf *bf)
724 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
725 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
727 if (tid->flag & TID_CLEANUP_INPROGRES) {
728 owl_tgt_tid_cleanup(sc, tid);
732 ath_tx_uc_comp(sc, bf);
735 ath_tx_freebuf(sc, bf);
738 static struct ieee80211_node_target * ath_tgt_find_node(struct ath_softc_tgt *sc,
739 a_int32_t node_index)
741 struct ath_node_target *an;
742 struct ieee80211_node_target *ni;
744 if (node_index > TARGET_NODE_MAX)
747 an = &sc->sc_sta[node_index];
751 if (ni->ni_vap == NULL) {
760 static struct ath_tx_buf* ath_tx_buf_alloc(struct ath_softc_tgt *sc)
762 struct ath_tx_buf *bf = NULL;
764 bf = asf_tailq_first(&sc->sc_txbuf);
766 adf_os_mem_set(&bf->bf_state, 0, sizeof(struct ath_buf_state));
767 asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
775 struct ath_tx_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc,
776 adf_nbuf_t skb, ath_data_hdr_t *dh)
778 struct ath_tx_buf *bf;
779 struct ieee80211_node_target *ni;
780 struct ath_atx_tid *tid;
782 ni = ath_tgt_find_node(sc, dh->ni_index);
786 tid = ATH_AN_2_TID(ATH_NODE_TARGET(ni), dh->tidno);
787 if (tid->flag & TID_REINITIALIZE) {
788 adf_os_print("drop frame due to TID reinit\n");
792 bf = ath_tx_buf_alloc(sc);
794 __stats(sc, tx_nobufs);
798 bf->bf_tidno = dh->tidno;
799 bf->bf_txq = TID_TO_ACTXQ(bf->bf_tidno);
800 bf->bf_keytype = dh->keytype;
801 bf->bf_keyix = dh->keyix;
802 bf->bf_protmode = dh->flags & (IEEE80211_PROT_RTSCTS | IEEE80211_PROT_CTSONLY);
805 adf_nbuf_queue_add(&bf->bf_skbhead, skb);
806 skb = adf_nbuf_queue_first(&(bf->bf_skbhead));
808 if (adf_nbuf_queue_len(&(bf->bf_skbhead)) == 0) {
809 __stats(sc, tx_noskbs);
817 ath_tgt_txbuf_setup(sc, bf, dh);
819 ath_tx_tgt_setds(sc, bf);
824 static void ath_tgt_tx_seqno_normal(struct ath_tx_buf *bf)
826 struct ieee80211_node_target *ni = bf->bf_node;
827 struct ath_node_target *an = ATH_NODE_TARGET(ni);
828 struct ieee80211_frame *wh = ATH_SKB_2_WH(bf->bf_skb);
829 struct ath_atx_tid *tid = ATH_AN_2_TID(an, bf->bf_tidno);
831 u_int8_t fragno = (wh->i_seq[0] & 0xf);
833 INCR(ni->ni_txseqmgmt, IEEE80211_SEQ_MAX);
835 bf->bf_seqno = (tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
837 *(u_int16_t *)wh->i_seq = adf_os_cpu_to_le16(bf->bf_seqno);
838 wh->i_seq[0] |= fragno;
840 if (!(wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG))
841 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
844 static a_int32_t ath_key_setup(struct ieee80211_node_target *ni,
845 struct ath_tx_buf *bf)
847 struct ieee80211_frame *wh = ATH_SKB_2_WH(bf->bf_skb);
849 if (!(wh->i_fc[1] & IEEE80211_FC1_WEP)) {
850 bf->bf_keytype = HAL_KEY_TYPE_CLEAR;
851 bf->bf_keyix = HAL_TXKEYIX_INVALID;
855 switch (bf->bf_keytype) {
856 case HAL_KEY_TYPE_WEP:
857 bf->bf_pktlen += IEEE80211_WEP_ICVLEN;
859 case HAL_KEY_TYPE_AES:
860 bf->bf_pktlen += IEEE80211_WEP_MICLEN;
862 case HAL_KEY_TYPE_TKIP:
863 bf->bf_pktlen += IEEE80211_WEP_ICVLEN;
869 if (bf->bf_keytype == HAL_KEY_TYPE_AES ||
870 bf->bf_keytype == HAL_KEY_TYPE_TKIP)
871 ieee80211_tgt_crypto_encap(wh, ni, bf->bf_keytype);
876 static void ath_tgt_txq_add_ucast(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
878 struct ath_hal *ah = sc->sc_ah;
881 volatile a_int32_t txe_val;
887 status = ath_hal_txprocdesc(sc->sc_ah, bf->bf_lastds);
889 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
891 if (txq->axq_link == NULL) {
892 ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
894 *txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
896 txe_val = OS_REG_READ(ah, 0x840);
897 if (!(txe_val & (1<< txq->axq_qnum)))
898 ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
901 txq->axq_link = &bf->bf_lastds->ds_link;
902 ah->ah_startTxDma(ah, txq->axq_qnum);
905 static a_int32_t ath_tgt_txbuf_setup(struct ath_softc_tgt *sc,
906 struct ath_tx_buf *bf,
910 struct ieee80211_frame *wh = ATH_SKB2_WH(bf->bf_skb);
912 a_uint32_t flags = adf_os_ntohl(dh->flags);
914 ath_tgt_tx_seqno_normal(bf);
916 bf->bf_txq_add = ath_tgt_txq_add_ucast;
917 bf->bf_hdrlen = ieee80211_anyhdrsize(wh);
918 bf->bf_pktlen = ath_get_pktlen(bf, bf->bf_hdrlen);
919 bf->bf_ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
921 if ((retval = ath_key_setup(bf->bf_node, bf)) < 0)
924 if (flags & ATH_SHORT_PREAMBLE)
925 bf->bf_shpream = AH_TRUE;
927 bf->bf_shpream = AH_FALSE;
929 bf->bf_flags = HAL_TXDESC_CLRDMASK;
930 bf->bf_atype = HAL_PKT_TYPE_NORMAL;
936 ath_get_pktlen(struct ath_tx_buf *bf, a_int32_t hdrlen)
938 adf_nbuf_t skb = bf->bf_skb;
941 skb = adf_nbuf_queue_first(&bf->bf_skbhead);
942 pktlen = adf_nbuf_len(skb);
944 pktlen -= (hdrlen & 3);
945 pktlen += IEEE80211_CRC_LEN;
951 ath_tgt_tx_send_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
953 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
954 struct ath_rc_series rcs[4];
955 struct ath_rc_series mrcs[4];
956 a_int32_t shortPreamble = 0;
957 a_int32_t isProbe = 0;
959 adf_os_mem_set(rcs, 0, sizeof(struct ath_rc_series)*4 );
960 adf_os_mem_set(mrcs, 0, sizeof(struct ath_rc_series)*4 );
962 if (!bf->bf_ismcast) {
963 ath_tgt_rate_findrate(sc, an, shortPreamble,
966 ath_hal_memcpy(bf->bf_rcs, rcs, sizeof(rcs));
968 mrcs[1].tries = mrcs[2].tries = mrcs[3].tries = 0;
969 mrcs[1].rix = mrcs[2].rix = mrcs[3].rix = 0;
973 ath_hal_memcpy(bf->bf_rcs, mrcs, sizeof(mrcs));
976 ath_buf_set_rate(sc, bf);
977 bf->bf_txq_add(sc, bf);
981 ath_tx_freebuf(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
984 struct ath_tx_desc *bfd = NULL;
986 for (bfd = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; bfd++, i++) {
987 ath_hal_clr11n_aggr(sc->sc_ah, bfd);
988 ath_hal_set11n_burstduration(sc->sc_ah, bfd, 0);
989 ath_hal_set11n_virtualmorefrag(sc->sc_ah, bfd, 0);
992 ath_dma_unmap(sc, bf);
994 ath_tgt_skb_free(sc, &bf->bf_skbhead,bf->bf_endpt);
1000 bf = ath_buf_toggle(sc, bf, 0);
1002 bf->bf_isretried = 0;
1005 asf_tailq_insert_tail(&sc->sc_txbuf, bf, bf_list);
1009 ath_tx_uc_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1011 ath_tx_status_update(sc, bf);
1012 ath_update_stats(sc, bf);
1013 ath_rate_tx_complete(sc, ATH_NODE_TARGET(bf->bf_node),
1014 bf->bf_lastds, bf->bf_rcs, 1, 0);
1018 ath_update_stats(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1020 struct ath_tx_desc *ds = bf->bf_desc;
1023 if (ds->ds_txstat.ts_status == 0) {
1024 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE)
1025 sc->sc_tx_stats.ast_tx_altrate++;
1027 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY)
1028 sc->sc_tx_stats.ast_tx_xretries++;
1029 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO)
1030 sc->sc_tx_stats.ast_tx_fifoerr++;
1031 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
1032 sc->sc_tx_stats.ast_tx_filtered++;
1033 if (ds->ds_txstat.ts_status & HAL_TXERR_TIMER_EXPIRED)
1034 sc->sc_tx_stats.ast_tx_timer_exp++;
1036 sr = ds->ds_txstat.ts_shortretry;
1037 lr = ds->ds_txstat.ts_longretry;
1038 sc->sc_tx_stats.ast_tx_shortretry += sr;
1039 sc->sc_tx_stats.ast_tx_longretry += lr;
1043 ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t hdr_buf, adf_nbuf_t skb,
1044 HTC_ENDPOINT_ID endpt)
1046 struct ieee80211_node_target *ni;
1047 struct ieee80211vap_target *vap;
1048 struct ath_vap_target *avp;
1049 struct ath_hal *ah = sc->sc_ah;
1050 a_uint8_t rix, txrate, ctsrate, cix = 0xff, *data;
1051 a_uint32_t ivlen = 0, icvlen = 0, subtype, flags, ctsduration;
1052 a_int32_t i, iswep, ismcast, hdrlen, pktlen, try0, len;
1053 struct ath_tx_desc *ds=NULL;
1054 struct ath_txq *txq=NULL;
1055 struct ath_tx_buf *bf;
1057 const HAL_RATE_TABLE *rt;
1058 HAL_BOOL shortPreamble;
1059 struct ieee80211_frame *wh;
1060 struct ath_rc_series rcs[4];
1061 HAL_11N_RATE_SERIES series[4];
1066 adf_nbuf_peek_header(skb, &data, &len);
1067 adf_nbuf_pull_head(skb, sizeof(ath_mgt_hdr_t));
1069 adf_nbuf_peek_header(hdr_buf, &data, &len);
1072 adf_os_assert(len >= sizeof(ath_mgt_hdr_t));
1074 mh = (ath_mgt_hdr_t *)data;
1075 adf_nbuf_peek_header(skb, &data, &len);
1076 wh = (struct ieee80211_frame *)data;
1078 adf_os_mem_set(rcs, 0, sizeof(struct ath_rc_series)*4);
1079 adf_os_mem_set(series, 0, sizeof(HAL_11N_RATE_SERIES)*4);
1081 bf = asf_tailq_first(&sc->sc_txbuf);
1085 asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
1087 ni = ath_tgt_find_node(sc, mh->ni_index);
1091 bf->bf_endpt = endpt;
1092 bf->bf_cookie = mh->cookie;
1093 bf->bf_protmode = mh->flags & (IEEE80211_PROT_RTSCTS | IEEE80211_PROT_CTSONLY);
1094 txq = &sc->sc_txq[1];
1095 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
1096 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
1097 hdrlen = ieee80211_anyhdrsize(wh);
1099 keyix = HAL_TXKEYIX_INVALID;
1100 pktlen -= (hdrlen & 3);
1101 pktlen += IEEE80211_CRC_LEN;
1106 adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, skb, ADF_OS_DMA_TO_DEVICE);
1109 adf_nbuf_queue_add(&bf->bf_skbhead, skb);
1112 rt = sc->sc_currates;
1113 adf_os_assert(rt != NULL);
1115 if (mh->flags == ATH_SHORT_PREAMBLE)
1116 shortPreamble = AH_TRUE;
1118 shortPreamble = AH_FALSE;
1120 flags = HAL_TXDESC_CLRDMASK;
1122 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
1123 case IEEE80211_FC0_TYPE_MGT:
1124 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
1126 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
1127 atype = HAL_PKT_TYPE_PROBE_RESP;
1128 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM)
1129 atype = HAL_PKT_TYPE_ATIM;
1131 atype = HAL_PKT_TYPE_NORMAL;
1135 atype = HAL_PKT_TYPE_NORMAL;
1139 avp = &sc->sc_vap[mh->vap_index];
1141 rcs[0].rix = ath_get_minrateidx(sc, avp);
1142 rcs[0].tries = ATH_TXMAXTRY;
1145 adf_os_mem_copy(bf->bf_rcs, rcs, sizeof(rcs));
1147 try0 = rcs[0].tries;
1148 txrate = rt->info[rix].rateCode;
1151 txrate |= rt->info[rix].shortPreamble;
1158 flags |= HAL_TXDESC_NOACK;
1160 } else if (pktlen > vap->iv_rtsthreshold) {
1161 flags |= HAL_TXDESC_RTSENA;
1162 cix = rt->info[rix].controlRate;
1165 if ((bf->bf_protmode != IEEE80211_PROT_NONE) &&
1166 rt->info[rix].phy == IEEE80211_T_OFDM &&
1167 (flags & HAL_TXDESC_NOACK) == 0) {
1168 cix = rt->info[sc->sc_protrix].controlRate;
1169 sc->sc_tx_stats.ast_tx_protect++;
1172 *(a_uint16_t *)&wh->i_seq[0] = adf_os_cpu_to_le16(ni->ni_txseqmgmt <<
1173 IEEE80211_SEQ_SEQ_SHIFT);
1174 INCR(ni->ni_txseqmgmt, IEEE80211_SEQ_MAX);
1177 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) {
1178 adf_os_assert(cix != 0xff);
1179 ctsrate = rt->info[cix].rateCode;
1180 if (shortPreamble) {
1181 ctsrate |= rt->info[cix].shortPreamble;
1182 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
1183 ctsduration += rt->info[cix].spAckDuration;
1184 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
1185 ctsduration += rt->info[cix].spAckDuration;
1187 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
1188 ctsduration += rt->info[cix].lpAckDuration;
1189 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
1190 ctsduration += rt->info[cix].lpAckDuration;
1192 ctsduration += ath_hal_computetxtime(ah,
1193 rt, pktlen, rix, shortPreamble);
1198 flags |= HAL_TXDESC_INTREQ;
1200 ath_hal_setuptxdesc(ah, ds
1213 , ATH_COMP_PROC_NO_COMP_NO_CCS);
1215 bf->bf_flags = flags;
1218 * Set key type in tx desc while sending the encrypted challenge to AP
1219 * in Auth frame 3 of Shared Authentication, owl needs this.
1221 if (iswep && (keyix != HAL_TXKEYIX_INVALID) &&
1222 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == IEEE80211_FC0_SUBTYPE_AUTH)
1223 ath_hal_fillkeytxdesc(ah, ds, mh->keytype);
1225 ath_filltxdesc(sc, bf);
1227 for (i=0; i<4; i++) {
1228 series[i].Tries = 2;
1229 series[i].Rate = txrate;
1230 series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
1231 series[i].RateFlags = 0;
1233 ath_hal_set11n_ratescenario(ah, ds, 0, ctsrate, ctsduration, series, 4, 0);
1234 ath_tgt_txqaddbuf(sc, txq, bf, bf->bf_lastds);
1238 HTC_ReturnBuffers(sc->tgt_htc_handle, endpt, skb);
1243 ath_tgt_txqaddbuf(struct ath_softc_tgt *sc,
1244 struct ath_txq *txq, struct ath_tx_buf *bf,
1245 struct ath_tx_desc *lastds)
1247 struct ath_hal *ah = sc->sc_ah;
1249 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
1251 if (txq->axq_link == NULL) {
1252 ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
1254 *txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
1257 txq->axq_link = &lastds->ds_link;
1258 ah->ah_startTxDma(ah, txq->axq_qnum);
1261 void ath_tgt_handle_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1264 struct ath_node_target *an;
1266 an = (struct ath_node_target *)bf->bf_node;
1269 tid = &an->tid[bf->bf_tidno];
1272 bf->bf_comp = ath_tgt_tx_comp_normal;
1273 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1274 ath_tgt_tx_send_normal(sc, bf);
1278 ath_tgt_tx_enqueue(struct ath_txq *txq, struct ath_atx_tid *tid)
1286 tid->sched = AH_TRUE;
1287 asf_tailq_insert_tail(&txq->axq_tidq, tid, tid_qelem);
1291 ath_tgt_txq_schedule(struct ath_softc_tgt *sc, struct ath_txq *txq)
1293 struct ath_atx_tid *tid;
1299 TAILQ_DEQ(&txq->axq_tidq, tid, tid_qelem);
1304 tid->sched = AH_FALSE;
1309 if (!(tid->flag & TID_AGGR_ENABLED))
1310 ath_tgt_tx_sched_normal(sc,tid);
1312 ath_tgt_tx_sched_aggr(sc,tid);
1316 if (!asf_tailq_empty(&tid->buf_q)) {
1317 ath_tgt_tx_enqueue(txq, tid);
1320 } while (!asf_tailq_empty(&txq->axq_tidq) && !bdone);
1324 ath_tgt_handle_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1327 struct ath_node_target *an;
1328 struct ath_txq *txq = bf->bf_txq;
1329 a_bool_t queue_frame, within_baw;
1331 an = (struct ath_node_target *)bf->bf_node;
1334 tid = &an->tid[bf->bf_tidno];
1337 bf->bf_comp = ath_tgt_tx_comp_aggr;
1339 within_baw = BAW_WITHIN(tid->seq_start, tid->baw_size,
1340 SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1342 queue_frame = ( (txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) ||
1343 (!asf_tailq_empty(&tid->buf_q)) ||
1344 (tid->paused) || (!within_baw) );
1347 asf_tailq_insert_tail(&tid->buf_q, bf, bf_list);
1348 ath_tgt_tx_enqueue(txq, tid);
1350 ath_tx_addto_baw(tid, bf);
1351 __stats(sc, txaggr_nframes);
1352 ath_tgt_tx_send_normal(sc, bf);
1357 ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
1359 struct ath_tx_buf *bf;
1360 struct ath_txq *txq =TID_TO_ACTXQ(tid->tidno);;
1363 if (asf_tailq_empty(&tid->buf_q))
1366 bf = asf_tailq_first(&tid->buf_q);
1367 asf_tailq_remove(&tid->buf_q, bf, bf_list);
1368 ath_tgt_tx_send_normal(sc, bf);
1370 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH);
1374 ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
1376 struct ath_tx_buf *bf, *bf_last;
1377 ATH_AGGR_STATUS status;
1378 ath_tx_bufhead bf_q;
1379 struct ath_txq *txq = TID_TO_ACTXQ(tid->tidno);
1380 struct ath_tx_desc *ds = NULL;
1384 if (asf_tailq_empty(&tid->buf_q))
1388 if (asf_tailq_empty(&tid->buf_q))
1391 asf_tailq_init(&bf_q);
1393 status = ath_tgt_tx_form_aggr(sc, tid, &bf_q);
1395 if (asf_tailq_empty(&bf_q))
1398 bf = asf_tailq_first(&bf_q);
1399 bf_last = asf_tailq_last(&bf_q, ath_tx_bufhead_s);
1401 if (bf->bf_nframes == 1) {
1403 if(bf->bf_retries == 0)
1404 __stats(sc, txaggr_single);
1406 bf->bf_lastds = &(bf->bf_descarr[bf->bf_dmamap_info.nsegs -1]);
1407 bf->bf_lastds->ds_link = 0;
1410 for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
1411 ath_hal_clr11n_aggr(sc->sc_ah, ds);
1413 ath_buf_set_rate(sc, bf);
1414 bf->bf_txq_add(sc, bf);
1419 bf_last->bf_next = NULL;
1420 bf_last->bf_lastds->ds_link = 0;
1421 bf_last->bf_ndelim = 0;
1424 ath_buf_set_rate(sc, bf);
1425 ath_hal_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al,
1427 bf->bf_lastds = bf_last->bf_lastds;
1429 for (i = 0; i < bf_last->bf_dmamap_info.nsegs; i++)
1430 ath_hal_set11n_aggr_last(sc->sc_ah, &bf_last->bf_descarr[i]);
1432 if (status == ATH_AGGR_8K_LIMITED) {
1437 bf->bf_txq_add(sc, bf);
1438 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
1439 status != ATH_TGT_AGGR_BAW_CLOSED);
1442 static u_int32_t ath_lookup_rate(struct ath_softc_tgt *sc,
1443 struct ath_node_target *an,
1444 struct ath_tx_buf *bf)
1447 u_int32_t max4msframelen, frame_length;
1448 u_int16_t aggr_limit, legacy=0;
1449 const HAL_RATE_TABLE *rt = sc->sc_currates;
1450 struct ieee80211_node_target *ieee_node = (struct ieee80211_node_target *)an;
1452 if (bf->bf_ismcast) {
1453 bf->bf_rcs[1].tries = bf->bf_rcs[2].tries = bf->bf_rcs[3].tries = 0;
1454 bf->bf_rcs[0].rix = 0xb;
1455 bf->bf_rcs[0].tries = ATH_TXMAXTRY - 1;
1456 bf->bf_rcs[0].flags = 0;
1458 ath_tgt_rate_findrate(sc, an, AH_TRUE, 0, ATH_TXMAXTRY-1, 4, 1,
1459 ATH_RC_PROBE_ALLOWED, bf->bf_rcs, &prate);
1462 max4msframelen = IEEE80211_AMPDU_LIMIT_MAX;
1464 for (i = 0; i < 4; i++) {
1465 if (bf->bf_rcs[i].tries) {
1466 frame_length = bf->bf_rcs[i].max4msframelen;
1468 if (rt->info[bf->bf_rcs[i].rix].phy != IEEE80211_T_HT) {
1473 max4msframelen = ATH_MIN(max4msframelen, frame_length);
1477 if (prate || legacy)
1480 if (sc->sc_ic.ic_enable_coex)
1481 aggr_limit = ATH_MIN((max4msframelen*3)/8, sc->sc_ic.ic_ampdu_limit);
1483 aggr_limit = ATH_MIN(max4msframelen, sc->sc_ic.ic_ampdu_limit);
1485 if (ieee_node->ni_maxampdu)
1486 aggr_limit = ATH_MIN(aggr_limit, ieee_node->ni_maxampdu);
1491 int ath_tgt_tx_form_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid,
1492 ath_tx_bufhead *bf_q)
1494 struct ath_tx_buf *bf_first ,*bf_prev = NULL;
1495 int nframes = 0, rl = 0;;
1496 struct ath_tx_desc *ds = NULL;
1497 struct ath_tx_buf *bf;
1498 u_int16_t aggr_limit = (64*1024 -1), al = 0, bpad = 0, al_delta;
1499 u_int16_t h_baw = tid->baw_size/2, prev_al = 0, prev_frames = 0;
1501 bf_first = asf_tailq_first(&tid->buf_q);
1504 bf = asf_tailq_first(&tid->buf_q);
1507 if (!BAW_WITHIN(tid->seq_start, tid->baw_size,
1508 SEQNO_FROM_BF_SEQNO(bf->bf_seqno))) {
1510 bf_first->bf_al= al;
1511 bf_first->bf_nframes = nframes;
1512 return ATH_TGT_AGGR_BAW_CLOSED;
1516 aggr_limit = ath_lookup_rate(sc, tid->an, bf);
1520 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_pktlen;
1522 if (nframes && (aggr_limit < (al + bpad + al_delta + prev_al))) {
1523 bf_first->bf_al= al;
1524 bf_first->bf_nframes = nframes;
1525 return ATH_TGT_AGGR_LIMITED;
1529 if ((nframes + prev_frames) >= ATH_MIN((h_baw), 17)) {
1531 if ((nframes + prev_frames) >= ATH_MIN((h_baw), 22)) {
1533 bf_first->bf_al= al;
1534 bf_first->bf_nframes = nframes;
1535 return ATH_TGT_AGGR_LIMITED;
1538 ath_tx_addto_baw(tid, bf);
1539 asf_tailq_remove(&tid->buf_q, bf, bf_list);
1540 asf_tailq_insert_tail(bf_q, bf, bf_list);
1545 adf_os_assert(bf->bf_comp == ath_tgt_tx_comp_aggr);
1547 al += bpad + al_delta;
1548 bf->bf_ndelim = ATH_AGGR_GET_NDELIM(bf->bf_pktlen);
1550 switch (bf->bf_keytype) {
1551 case HAL_KEY_TYPE_AES:
1552 bf->bf_ndelim += ATH_AGGR_ENCRYPTDELIM;
1554 case HAL_KEY_TYPE_WEP:
1555 case HAL_KEY_TYPE_TKIP:
1556 bf->bf_ndelim += 64;
1558 case HAL_KEY_TYPE_WAPI:
1559 bf->bf_ndelim += 12;
1565 bpad = PADBYTES(al_delta) + (bf->bf_ndelim << 2);
1568 bf_prev->bf_next = bf;
1569 bf_prev->bf_lastds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
1573 for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
1574 ath_hal_set11n_aggr_middle(sc->sc_ah, ds, bf->bf_ndelim);
1576 } while (!asf_tailq_empty(&tid->buf_q));
1578 bf_first->bf_al= al;
1579 bf_first->bf_nframes = nframes;
1581 return ATH_TGT_AGGR_DONE;
1584 void ath_tx_addto_baw(ath_atx_tid_t *tid, struct ath_tx_buf *bf)
1588 if (bf->bf_isretried) {
1592 index = ATH_BA_INDEX(tid->seq_start, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1593 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1595 TX_BUF_BITMAP_SET(tid->tx_buf_bitmap, cindex);
1597 if (index >= ((tid->baw_tail - tid->baw_head) & (ATH_TID_MAX_BUFS - 1))) {
1598 tid->baw_tail = cindex;
1599 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
1603 void ath_tgt_tx_comp_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1605 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1606 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1607 struct ath_tx_desc lastds;
1608 struct ath_tx_desc *ds = &lastds;
1609 struct ath_rc_series rcs[4];
1614 int nframes = bf->bf_nframes;
1615 struct ath_tx_buf *bf_next;
1616 ath_tx_bufhead bf_q;
1618 struct ath_tx_buf *bar = NULL;
1619 struct ath_txq *txq;
1623 if (tid->flag & TID_CLEANUP_INPROGRES) {
1624 ath_tx_comp_cleanup(sc, bf);
1628 adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
1629 adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
1631 if (ds->ds_txstat.ts_flags == HAL_TX_SW_FILTERED) {
1636 if (!bf->bf_isaggr) {
1637 ath_tx_comp_unaggr(sc, bf);
1641 __stats(sc, tx_compaggr);
1643 asf_tailq_init(&bf_q);
1645 seq_st = ATH_DS_BA_SEQ(ds);
1646 ba = ATH_DS_BA_BITMAP(ds);
1647 tx_ok = (ATH_DS_TX_STATUS(ds) == HAL_OK);
1649 if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
1650 ath_tx_comp_aggr_error(sc, bf, tid);
1654 if (tx_ok && !ATH_DS_TX_BA(ds)) {
1655 __stats(sc, txaggr_babug);
1656 adf_os_print("BA Bug?\n");
1657 ath_tx_comp_aggr_error(sc, bf, tid);
1662 ba_index = ATH_BA_INDEX(seq_st, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1663 bf_next = bf->bf_next;
1665 if (tx_ok && ATH_BA_ISSET(ba, ba_index)) {
1666 __stats(sc, txaggr_compgood);
1667 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1668 ath_tx_status_update_aggr(sc, bf, ds, rcs, 1);
1669 ath_tx_freebuf(sc, bf);
1671 ath_tx_retry_subframe(sc, bf, &bf_q, &bar);
1677 ath_update_aggr_stats(sc, ds, nframes, nbad);
1678 ath_rate_tx_complete(sc, an, ds, rcs, nframes, nbad);
1681 ath_bar_tx(sc, tid, bar);
1684 if (!asf_tailq_empty(&bf_q)) {
1685 __stats(sc, txaggr_prepends);
1686 TAILQ_INSERTQ_HEAD(&tid->buf_q, &bf_q, bf_list);
1687 ath_tgt_tx_enqueue(txq, tid);
1692 ath_tx_comp_aggr_error(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
1697 struct ath_tx_desc lastds;
1698 struct ath_tx_desc *ds = &lastds;
1699 struct ath_rc_series rcs[4];
1700 struct ath_tx_buf *bar = NULL;
1701 struct ath_tx_buf *bf_next;
1702 int nframes = bf->bf_nframes;
1703 ath_tx_bufhead bf_q;
1704 struct ath_txq *txq;
1706 asf_tailq_init(&bf_q);
1709 adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
1710 adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
1713 bf_next = bf->bf_next;
1714 ath_tx_retry_subframe(sc, bf, &bf_q, &bar);
1718 ath_update_aggr_stats(sc, ds, nframes, nframes);
1719 ath_rate_tx_complete(sc, tid->an, ds, rcs, nframes, nframes);
1722 ath_bar_tx(sc, tid, bar);
1725 if (!asf_tailq_empty(&bf_q)) {
1726 __stats(sc, txaggr_prepends);
1727 TAILQ_INSERTQ_HEAD(&tid->buf_q, &bf_q, bf_list);
1728 ath_tgt_tx_enqueue(txq, tid);
1733 ath_tx_comp_cleanup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1736 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1737 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1738 struct ath_tx_desc lastds;
1739 struct ath_tx_desc *ds = &lastds;
1740 struct ath_rc_series rcs[4];
1745 int nframes = bf->bf_nframes;
1746 struct ath_tx_buf *bf_next;
1749 adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
1750 adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
1752 seq_st = ATH_DS_BA_SEQ(ds);
1753 ba = ATH_DS_BA_BITMAP(ds);
1754 tx_ok = (ATH_DS_TX_STATUS(ds) == HAL_OK);
1756 if (!bf->bf_isaggr) {
1757 ath_update_stats(sc, bf);
1759 __stats(sc, tx_compunaggr);
1761 ath_tx_status_update(sc, bf);
1763 ath_tx_freebuf(sc, bf);
1765 if (tid->flag & TID_CLEANUP_INPROGRES) {
1766 owl_tgt_tid_cleanup(sc, tid);
1774 ba_index = ATH_BA_INDEX(seq_st, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1775 bf_next = bf->bf_next;
1777 ath_tx_status_update_aggr(sc, bf, ds, rcs, 0);
1779 ath_tx_freebuf(sc, bf);
1783 tid->flag &= ~TID_CLEANUP_INPROGRES;
1784 ath_aggr_resume_tid(sc, tid);
1791 ath_update_aggr_stats(sc, ds, nframes, nbad);
1792 ath_rate_tx_complete(sc, an, ds, rcs, nframes, nbad);
1796 ath_tx_retry_subframe(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
1797 ath_tx_bufhead *bf_q, struct ath_tx_buf **bar)
1800 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1801 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1802 struct ath_tx_desc *ds = NULL;
1805 __stats(sc, txaggr_compretries);
1807 for(ds = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; ds++, i++) {
1808 ath_hal_clr11n_aggr(sc->sc_ah, ds);
1809 ath_hal_set11n_burstduration(sc->sc_ah, ds, 0);
1810 ath_hal_set11n_virtualmorefrag(sc->sc_ah, ds, 0);
1813 if (bf->bf_retries >= OWLMAX_RETRIES) {
1814 __stats(sc, txaggr_xretries);
1815 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1816 ath_tx_status_update_aggr(sc, bf, bf->bf_lastds, NULL, 0);
1821 ath_tx_freebuf(sc, bf);
1826 __stats(sc, txaggr_errlast);
1827 bf = ath_buf_toggle(sc, bf, 1);
1829 bf->bf_lastds = &(bf->bf_descarr[bf->bf_dmamap_info.nsegs - 1]);
1831 ath_tx_set_retry(sc, bf);
1832 asf_tailq_insert_tail(bf_q, bf, bf_list);
1836 ath_update_aggr_stats(struct ath_softc_tgt *sc,
1837 struct ath_tx_desc *ds, int nframes,
1841 u_int8_t status = ATH_DS_TX_STATUS(ds);
1842 u_int8_t txflags = ATH_DS_TX_FLAGS(ds);
1844 __statsn(sc, txaggr_longretries, ds->ds_txstat.ts_longretry);
1845 __statsn(sc, txaggr_shortretries, ds->ds_txstat.ts_shortretry);
1847 if (txflags & HAL_TX_DESC_CFG_ERR)
1848 __stats(sc, txaggr_desc_cfgerr);
1850 if (txflags & HAL_TX_DATA_UNDERRUN)
1851 __stats(sc, txaggr_data_urun);
1853 if (txflags & HAL_TX_DELIM_UNDERRUN)
1854 __stats(sc, txaggr_delim_urun);
1860 if (status & HAL_TXERR_XRETRY)
1861 __stats(sc, txaggr_compxretry);
1863 if (status & HAL_TXERR_FILT)
1864 __stats(sc, txaggr_filtered);
1866 if (status & HAL_TXERR_FIFO)
1867 __stats(sc, txaggr_fifo);
1869 if (status & HAL_TXERR_XTXOP)
1870 __stats(sc, txaggr_xtxop);
1872 if (status & HAL_TXERR_TIMER_EXPIRED)
1873 __stats(sc, txaggr_timer_exp);
1877 ath_tx_comp_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1879 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1880 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1881 struct ath_tx_desc *ds = bf->bf_lastds;
1883 ath_update_stats(sc, bf);
1884 ath_rate_tx_complete(sc, an, ds, bf->bf_rcs, 1, 0);
1886 if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
1887 ath_tx_retry_unaggr(sc, bf);
1890 __stats(sc, tx_compunaggr);
1892 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1893 ath_tx_status_update(sc, bf);
1894 ath_tx_freebuf(sc, bf);
1898 ath_tx_retry_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1900 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1901 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1902 struct ath_txq *txq;
1906 if (bf->bf_retries >= OWLMAX_RETRIES) {
1907 __stats(sc, txunaggr_xretry);
1908 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1909 ath_tx_status_update(sc, bf);
1910 ath_bar_tx(sc, tid, bf);
1914 __stats(sc, txunaggr_compretries);
1915 if (!bf->bf_lastds->ds_link) {
1916 __stats(sc, txunaggr_errlast);
1917 bf = ath_buf_toggle(sc, bf, 1);
1920 ath_tx_set_retry(sc, bf);
1921 asf_tailq_insert_head(&tid->buf_q, bf, bf_list);
1922 ath_tgt_tx_enqueue(txq, tid);
1926 ath_tx_update_baw(ath_atx_tid_t *tid, int seqno)
1931 index = ATH_BA_INDEX(tid->seq_start, seqno);
1932 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1934 TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, cindex);
1936 while (tid->baw_head != tid->baw_tail &&
1937 (!TX_BUF_BITMAP_IS_SET(tid->tx_buf_bitmap, tid->baw_head))) {
1938 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1939 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
1943 static void ath_tx_set_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1945 struct ieee80211_frame *wh;
1947 __stats(sc, txaggr_retries);
1949 bf->bf_isretried = 1;
1951 wh = ATH_SKB_2_WH(bf->bf_skb);
1952 wh->i_fc[1] |= IEEE80211_FC1_RETRY;
1955 void ath_tgt_tx_cleanup(struct ath_softc_tgt *sc, struct ath_node_target *an,
1956 ath_atx_tid_t *tid, a_uint8_t discard_all)
1958 struct ath_tx_buf *bf;
1959 struct ath_tx_buf *bf_next;
1960 struct ath_txq *txq;
1962 txq = TID_TO_ACTXQ(tid->tidno);
1964 bf = asf_tailq_first(&tid->buf_q);
1967 if (discard_all || bf->bf_isretried) {
1968 bf_next = asf_tailq_next(bf, bf_list);
1969 TAILQ_DEQ(&tid->buf_q, bf, bf_list);
1970 if (bf->bf_isretried)
1971 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1972 ath_tx_freebuf(sc, bf);
1976 bf->bf_comp = ath_tgt_tx_comp_normal;
1977 bf = asf_tailq_next(bf, bf_list);
1980 ath_aggr_pause_tid(sc, tid);
1982 while (tid->baw_head != tid->baw_tail) {
1983 if (TX_BUF_BITMAP_IS_SET(tid->tx_buf_bitmap, tid->baw_head)) {
1985 tid->flag |= TID_CLEANUP_INPROGRES;
1986 TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, tid->baw_head);
1988 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
1989 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1992 if (!(tid->flag & TID_CLEANUP_INPROGRES)) {
1993 ath_aggr_resume_tid(sc, tid);
1997 /******************/
1998 /* BAR Management */
1999 /******************/
2001 static void ath_tgt_delba_send(struct ath_softc_tgt *sc,
2002 struct ieee80211_node_target *ni,
2003 a_uint8_t tidno, a_uint8_t initiator,
2004 a_uint16_t reasoncode)
2006 struct ath_node_target *an = ATH_NODE_TARGET(ni);
2007 ath_atx_tid_t *tid = ATH_AN_2_TID(an, tidno);
2008 struct wmi_data_delba wmi_delba;
2010 tid->flag &= ~TID_AGGR_ENABLED;
2012 ath_tgt_tx_cleanup(sc, an, tid, 1);
2014 wmi_delba.ni_nodeindex = ni->ni_nodeindex;
2015 wmi_delba.tidno = tid->tidno;
2016 wmi_delba.initiator = 1;
2017 wmi_delba.reasoncode = IEEE80211_REASON_UNSPECIFIED;
2019 __stats(sc, txbar_xretry);
2020 wmi_event(sc->tgt_wmi_handle,
2026 static void ath_bar_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
2028 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
2029 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
2031 if (bf->bf_retries >= OWLMAX_BAR_RETRIES) {
2032 ath_tgt_delba_send(sc, bf->bf_node, tid->tidno, 1,
2033 IEEE80211_REASON_UNSPECIFIED);
2034 ath_tgt_tid_drain(sc, tid);
2037 ath_buf_comp(sc, bf);
2041 __stats(sc, txbar_compretries);
2043 if (!bf->bf_lastds->ds_link) {
2044 __stats(sc, txbar_errlast);
2045 bf = ath_buf_toggle(sc, bf, 1);
2048 bf->bf_lastds->ds_link = 0;
2050 ath_tx_set_retry(sc, bf);
2051 ath_tgt_txq_add_ucast(sc, bf);
2054 static void ath_bar_tx_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
2056 struct ath_tx_desc *ds = bf->bf_lastds;
2057 struct ath_node_target *an;
2059 struct ath_txq *txq;
2061 an = (struct ath_node_target *)bf->bf_node;
2062 tid = &an->tid[bf->bf_tidno];
2063 txq = TID_TO_ACTXQ(tid->tidno);
2065 if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
2066 ath_bar_retry(sc, bf);
2070 ath_aggr_resume_tid(sc, tid);
2073 ath_buf_comp(sc, bf);
2076 static void ath_bar_tx(struct ath_softc_tgt *sc,
2077 ath_atx_tid_t *tid, struct ath_tx_buf *bf)
2080 struct ieee80211_frame_bar *bar;
2082 struct ath_tx_desc *ds, *ds0;
2083 HAL_11N_RATE_SERIES series[4];
2085 adf_nbuf_queue_t skbhead;
2089 __stats(sc, tx_bars);
2091 adf_os_mem_set(&series, 0, sizeof(series));
2093 ath_aggr_pause_tid(sc, tid);
2095 skb = adf_nbuf_queue_remove(&bf->bf_skbhead);
2096 adf_nbuf_peek_header(skb, &anbdata, &anblen);
2097 adf_nbuf_trim_tail(skb, anblen);
2098 bar = (struct ieee80211_frame_bar *) anbdata;
2102 ath_dma_unmap(sc, bf);
2103 adf_nbuf_queue_add(&bf->bf_skbhead, skb);
2105 bar->i_fc[1] = IEEE80211_FC1_DIR_NODS;
2106 bar->i_fc[0] = IEEE80211_FC0_VERSION_0 |
2107 IEEE80211_FC0_TYPE_CTL |
2108 IEEE80211_FC0_SUBTYPE_BAR;
2109 bar->i_ctl = tid->tidno << IEEE80211_BAR_CTL_TID_S |
2110 IEEE80211_BAR_CTL_COMBA;
2111 bar->i_seq = adf_os_cpu_to_le16(tid->seq_start << IEEE80211_SEQ_SEQ_SHIFT);
2113 bf->bf_seqno = tid->seq_start << IEEE80211_SEQ_SEQ_SHIFT;
2115 adf_nbuf_put_tail(skb, sizeof(struct ieee80211_frame_bar));
2117 bf->bf_comp = ath_bar_tx_comp;
2118 bf->bf_tidno = tid->tidno;
2119 bf->bf_node = &tid->an->ni;
2120 ath_dma_map(sc, bf);
2121 adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info);
2124 ath_hal_setuptxdesc(sc->sc_ah, ds
2125 , adf_nbuf_len(skb) + IEEE80211_CRC_LEN
2127 , HAL_PKT_TYPE_NORMAL
2134 | HAL_TXDESC_CLRDMASK
2136 , ATH_COMP_PROC_NO_COMP_NO_CCS);
2138 skbhead = bf->bf_skbhead;
2142 for (ds0 = ds, i=0; i < bf->bf_dmamap_info.nsegs; ds0++, i++) {
2143 ath_hal_clr11n_aggr(sc->sc_ah, ds0);
2146 ath_filltxdesc(sc, bf);
2148 for (i = 0 ; i < 4; i++) {
2149 series[i].Tries = ATH_TXMAXTRY;
2150 series[i].Rate = min_rate;
2151 series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
2154 ath_hal_set11n_ratescenario(sc->sc_ah, bf->bf_desc, 0, 0, 0, series, 4, 4);
2155 ath_tgt_txq_add_ucast(sc, bf);