2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <adf_os_types.h>
37 #include <adf_os_dma.h>
38 #include <adf_os_timer.h>
39 #include <adf_os_lock.h>
40 #include <adf_os_io.h>
41 #include <adf_os_mem.h>
42 #include <adf_os_util.h>
43 #include <adf_os_stdtypes.h>
44 #include <adf_os_defer.h>
45 #include <adf_os_atomic.h>
48 #include <adf_net_wcmd.h>
50 #include "if_ethersubr.h"
53 #ifdef USE_HEADERLEN_RESV
57 #include <ieee80211_var.h>
58 #include "if_athrate.h"
59 #include "if_athvar.h"
61 #include "if_ath_pci.h"
63 #define ath_tgt_free_skb adf_nbuf_free
65 #define OFDM_PLCP_BITS 22
66 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
67 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
73 #define HT_LTF(_ns) (4 * (_ns))
74 #define SYMBOL_TIME(_ns) ((_ns) << 2) // ns * 4 us
75 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) // ns * 3.6 us
77 static a_uint16_t bits_per_symbol[][2] = {
79 { 26, 54 }, // 0: BPSK
80 { 52, 108 }, // 1: QPSK 1/2
81 { 78, 162 }, // 2: QPSK 3/4
82 { 104, 216 }, // 3: 16-QAM 1/2
83 { 156, 324 }, // 4: 16-QAM 3/4
84 { 208, 432 }, // 5: 64-QAM 2/3
85 { 234, 486 }, // 6: 64-QAM 3/4
86 { 260, 540 }, // 7: 64-QAM 5/6
87 { 52, 108 }, // 8: BPSK
88 { 104, 216 }, // 9: QPSK 1/2
89 { 156, 324 }, // 10: QPSK 3/4
90 { 208, 432 }, // 11: 16-QAM 1/2
91 { 312, 648 }, // 12: 16-QAM 3/4
92 { 416, 864 }, // 13: 64-QAM 2/3
93 { 468, 972 }, // 14: 64-QAM 3/4
94 { 520, 1080 }, // 15: 64-QAM 5/6
97 void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,
98 owl_txq_state_t txqstate);
99 static void ath_tgt_txqaddbuf(struct ath_softc_tgt *sc, struct ath_txq *txq,
100 struct ath_buf *bf, struct ath_desc *lastds);
101 void ath_rate_findrate_11n_Hardcoded(struct ath_softc_tgt *sc,
102 struct ath_rc_series series[]);
103 void ath_buf_set_rate_Hardcoded(struct ath_softc_tgt *sc,
104 struct ath_tx_buf *bf) ;
105 static a_int32_t ath_tgt_txbuf_setup(struct ath_softc_tgt *sc,
106 struct ath_tx_buf *bf, ath_data_hdr_t *dh);
107 static void ath_tx_freebuf(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
108 static void ath_tx_uc_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
109 static void ath_update_stats(struct ath_softc_tgt *sc, struct ath_buf *bf);
110 void adf_print_buf(adf_nbuf_t buf);
111 static void ath_tgt_tx_enqueue(struct ath_txq *txq, struct ath_atx_tid *tid);
113 struct ath_buf * ath_tgt_tx_prepare(struct ath_softc_tgt *sc,
114 adf_nbuf_t skb, ath_data_hdr_t *dh);
115 void ath_tgt_tx_comp_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
116 struct ieee80211_frame *ATH_SKB_2_WH(adf_nbuf_t skb);
118 void ath_tgt_tx_send_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
120 static void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
121 static void ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
123 extern a_int32_t ath_chainmask_sel_logic(void *);
124 static a_int32_t ath_get_pktlen(struct ath_buf *bf, a_int32_t hdrlen);
125 static void ath_tgt_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
127 typedef void (*ath_ft_set_atype_t)(struct ath_softc_tgt *sc, struct ath_buf *bf);
130 ath_tx_set_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
133 ath_bar_tx(struct ath_softc_tgt *sc, ath_atx_tid_t *tid, struct ath_tx_buf *bf);
135 ath_tx_update_baw(ath_atx_tid_t *tid, int seqno);
137 ath_tx_retry_subframe(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
138 ath_bufhead *bf_q, struct ath_tx_buf **bar);
141 ath_tx_comp_aggr_error(struct ath_softc_tgt *sc, struct ath_tx_buf *bf, ath_atx_tid_t *tid);
143 void ath_tx_addto_baw(ath_atx_tid_t *tid, struct ath_tx_buf *bf);
144 static inline void ath_tx_retry_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
145 static void ath_tx_comp_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
146 static void ath_update_aggr_stats(struct ath_softc_tgt *sc, struct ath_tx_desc *ds,
147 int nframes, int nbad);
148 static inline void ath_aggr_resume_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
149 static void ath_tx_comp_cleanup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
151 int ath_tgt_tx_add_to_aggr(struct ath_softc_tgt *sc,
152 struct ath_buf *bf,int datatype,
153 ath_atx_tid_t *tid, int is_burst);
155 struct ieee80211_frame *ATH_SKB_2_WH(adf_nbuf_t skb)
160 adf_nbuf_peek_header(skb, &anbdata, &anblen);
162 return((struct ieee80211_frame *)anbdata);
165 #undef adf_os_cpu_to_le16
167 static a_uint16_t adf_os_cpu_to_le16(a_uint16_t x)
169 return ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8));
173 ath_aggr_resume_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
177 txq = TID_TO_ACTXQ(tid->tidno);
180 if (asf_tailq_empty(&tid->buf_q))
183 ath_tgt_tx_enqueue(txq, tid);
184 ath_tgt_txq_schedule(sc, txq);
188 ath_aggr_pause_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
193 static a_uint32_t ath_pkt_duration(struct ath_softc_tgt *sc,
194 a_uint8_t rix, struct ath_tx_buf *bf,
195 a_int32_t width, a_int32_t half_gi)
197 const HAL_RATE_TABLE *rt = sc->sc_currates;
198 a_uint32_t nbits, nsymbits, duration, nsymbols;
203 pktlen = bf->bf_isaggr ? bf->bf_al : bf->bf_pktlen;
204 rc = rt->info[rix].rateCode;
207 return ath_hal_computetxtime(sc->sc_ah, rt, pktlen, rix,
210 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
211 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
212 nsymbols = (nbits + nsymbits - 1) / nsymbits;
215 duration = SYMBOL_TIME(nsymbols);
217 duration = SYMBOL_TIME_HALFGI(nsymbols);
219 streams = HT_RC_2_STREAMS(rc);
220 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
225 static void ath_dma_map(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
227 adf_nbuf_t skb = bf->bf_skb;
229 skb = adf_nbuf_queue_first(&bf->bf_skbhead);
230 adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, skb, ADF_OS_DMA_TO_DEVICE);
233 static void ath_dma_unmap(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
235 adf_nbuf_t skb = bf->bf_skb;
237 skb = adf_nbuf_queue_first(&bf->bf_skbhead);
238 adf_nbuf_unmap( sc->sc_dev, bf->bf_dmamap, ADF_OS_DMA_TO_DEVICE);
241 static void ath_filltxdesc(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
243 struct ath_desc *ds0, *ds = bf->bf_desc;
247 adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info);
249 for (i = 0; i < bf->bf_dmamap_info.nsegs; i++, ds++) {
251 ds->ds_data = bf->bf_dmamap_info.dma_segs[i].paddr;
253 if (i == (bf->bf_dmamap_info.nsegs - 1)) {
257 ds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, i+1);
259 ath_hal_filltxdesc(sc->sc_ah, ds
260 , bf->bf_dmamap_info.dma_segs[i].len
262 , i == (bf->bf_dmamap_info.nsegs - 1)
267 static void ath_tx_tgt_setds(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
269 struct ath_desc *ds = bf->bf_desc;
271 switch (bf->bf_protmode) {
272 case IEEE80211_PROT_RTSCTS:
273 bf->bf_flags |= HAL_TXDESC_RTSENA;
275 case IEEE80211_PROT_CTSONLY:
276 bf->bf_flags |= HAL_TXDESC_CTSENA;
282 ath_hal_set11n_txdesc(sc->sc_ah, ds
288 , bf->bf_flags | HAL_TXDESC_INTREQ);
290 ath_filltxdesc(sc, bf);
293 static struct ath_buf *ath_buf_toggle(struct ath_softc_tgt *sc,
294 struct ath_tx_buf *bf,
297 struct ath_tx_buf *tmp = NULL;
298 adf_nbuf_t buf = NULL;
300 adf_os_assert(sc->sc_txbuf_held != NULL);
302 tmp = sc->sc_txbuf_held;
305 ath_dma_unmap(sc, bf);
306 adf_nbuf_queue_init(&tmp->bf_skbhead);
307 buf = adf_nbuf_queue_remove(&bf->bf_skbhead);
309 adf_nbuf_queue_add(&tmp->bf_skbhead, buf);
311 adf_os_assert(adf_nbuf_queue_len(&bf->bf_skbhead) == 0);
313 tmp->bf_next = bf->bf_next;
314 tmp->bf_endpt = bf->bf_endpt;
315 tmp->bf_tidno = bf->bf_tidno;
316 tmp->bf_skb = bf->bf_skb;
317 tmp->bf_node = bf->bf_node;
318 tmp->bf_isaggr = bf->bf_isaggr;
319 tmp->bf_flags = bf->bf_flags;
320 tmp->bf_state = bf->bf_state;
321 tmp->bf_retries = bf->bf_retries;
322 tmp->bf_comp = bf->bf_comp;
323 tmp->bf_nframes = bf->bf_nframes;
324 tmp->bf_cookie = bf->bf_cookie;
336 ath_dma_map(sc, tmp);
337 ath_tx_tgt_setds(sc, tmp);
340 sc->sc_txbuf_held = bf;
345 static void ath_tgt_skb_free(struct ath_softc_tgt *sc,
346 adf_nbuf_queue_t *head,
347 HTC_ENDPOINT_ID endpt)
351 while (adf_nbuf_queue_len(head) != 0) {
352 tskb = adf_nbuf_queue_remove(head);
353 ath_free_tx_skb(sc->tgt_htc_handle,endpt,tskb);
357 static void ath_buf_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
359 ath_dma_unmap(sc, bf);
360 ath_tgt_skb_free(sc, &bf->bf_skbhead,bf->bf_endpt);
363 bf = ath_buf_toggle(sc, bf, 0);
365 asf_tailq_insert_tail(&sc->sc_txbuf, bf, bf_list);
369 static void ath_buf_set_rate(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
371 struct ath_hal *ah = sc->sc_ah;
372 const HAL_RATE_TABLE *rt;
373 struct ath_desc *ds = bf->bf_desc;
374 HAL_11N_RATE_SERIES series[4];
376 a_uint8_t rix, cix, rtsctsrate;
377 a_uint32_t ctsduration = 0;
378 a_int32_t prot_mode = AH_FALSE;
380 rt = sc->sc_currates;
381 rix = bf->bf_rcs[0].rix;
382 flags = (bf->bf_flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA));
383 cix = rt->info[sc->sc_protrix].controlRate;
385 if (bf->bf_protmode != IEEE80211_PROT_NONE &&
386 (rt->info[rix].phy == IEEE80211_T_OFDM ||
387 rt->info[rix].phy == IEEE80211_T_HT) &&
388 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
389 cix = rt->info[sc->sc_protrix].controlRate;
392 if (ath_hal_htsupported(ah) && (!bf->bf_ismcast))
393 flags = HAL_TXDESC_RTSENA;
396 if (bf->bf_rcs[i].tries) {
397 cix = rt->info[bf->bf_rcs[i].rix].controlRate;
404 adf_os_mem_set(series, 0, sizeof(HAL_11N_RATE_SERIES) * 4);
406 for (i = 0; i < 4; i++) {
407 if (!bf->bf_rcs[i].tries)
410 rix = bf->bf_rcs[i].rix;
412 series[i].Rate = rt->info[rix].rateCode |
413 (bf->bf_shpream ? rt->info[rix].shortPreamble : 0);
415 series[i].Tries = bf->bf_rcs[i].tries;
417 series[i].RateFlags = ((bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
418 HAL_RATESERIES_RTS_CTS : 0 ) |
419 ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
420 HAL_RATESERIES_2040 : 0 ) |
421 ((bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG) ?
422 HAL_RATESERIES_HALFGI : 0 ) |
423 ((bf->bf_rcs[i].flags & ATH_RC_TX_STBC_FLAG) ?
424 HAL_RATESERIES_STBC: 0);
426 series[i].RateFlags = ((bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
427 HAL_RATESERIES_RTS_CTS : 0 ) |
428 ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
429 HAL_RATESERIES_2040 : 0 ) |
430 ((bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG) ?
431 HAL_RATESERIES_HALFGI : 0 );
433 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
434 (bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) != 0,
435 (bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG));
437 series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
440 series[i].RateFlags |= HAL_RATESERIES_RTS_CTS;
442 if (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG)
443 series[i].RateFlags |= HAL_RATESERIES_RTS_CTS;
446 rtsctsrate = rt->info[cix].rateCode |
447 (bf->bf_shpream ? rt->info[cix].shortPreamble : 0);
449 ath_hal_set11n_ratescenario(ah, ds, 1,
450 rtsctsrate, ctsduration,
455 static void ath_tgt_rate_findrate(struct ath_softc_tgt *sc,
456 struct ath_node_target *an,
457 a_int32_t shortPreamble,
463 struct ath_rc_series series[],
466 ath_rate_findrate(sc, an, 1, frameLen, 10, 4, 1,
467 ATH_RC_PROBE_ALLOWED, series, isProbe);
470 static void owl_tgt_tid_init(struct ath_atx_tid *tid)
474 tid->seq_start = tid->seq_next = 0;
475 tid->baw_size = WME_MAX_BA;
476 tid->baw_head = tid->baw_tail = 0;
479 tid->sched = AH_FALSE;
481 asf_tailq_init(&tid->buf_q);
483 for (i = 0; i < ATH_TID_MAX_BUFS; i++) {
484 TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, i);
488 static void owl_tgt_tid_cleanup(struct ath_softc_tgt *sc,
489 struct ath_atx_tid *tid)
496 tid->flag &= ~TID_CLEANUP_INPROGRES;
498 if (tid->flag & TID_REINITIALIZE) {
499 adf_os_print("TID REINIT DONE for tid %p\n", tid);
500 tid->flag &= ~TID_REINITIALIZE;
501 owl_tgt_tid_init(tid);
503 ath_aggr_resume_tid(sc, tid);
507 void owl_tgt_node_init(struct ath_node_target * an)
509 struct ath_atx_tid *tid;
512 for (tidno = 0, tid = &an->tid[tidno]; tidno < WME_NUM_TID;tidno++, tid++) {
516 if ( tid->flag & TID_CLEANUP_INPROGRES ) {
517 tid->flag |= TID_REINITIALIZE;
518 adf_os_print("tid[%p]->incomp is not 0: %d\n",
521 owl_tgt_tid_init(tid);
526 void ath_tx_status_clear(struct ath_softc_tgt *sc)
530 for (i = 0; i < 2; i++) {
531 sc->tx_status[i].cnt = 0;
535 static WMI_TXSTATUS_EVENT *ath_tx_status_get(struct ath_softc_tgt *sc)
537 WMI_TXSTATUS_EVENT *txs = NULL;
540 for (i = 0; i < 2; i++) {
541 if (sc->tx_status[i].cnt < HTC_MAX_TX_STATUS) {
542 txs = &sc->tx_status[i];
550 void ath_tx_status_update(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
552 struct ath_tx_desc *ds = bf->bf_lastds;
553 WMI_TXSTATUS_EVENT *txs;
555 if (sc->sc_tx_draining)
558 txs = ath_tx_status_get(sc);
562 txs->txstatus[txs->cnt].cookie = bf->bf_cookie;
563 txs->txstatus[txs->cnt].ts_rate = SM(bf->bf_endpt, ATH9K_HTC_TXSTAT_EPID);
565 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
566 txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_FILT;
568 if (!(ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) &&
569 !(ds->ds_txstat.ts_status & HAL_TXERR_FIFO) &&
570 !(ds->ds_txstat.ts_status & HAL_TXERR_TIMER_EXPIRED) &&
571 !(ds->ds_txstat.ts_status & HAL_TXERR_FILT))
572 txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_ACK;
574 ath_tx_status_update_rate(sc, bf->bf_rcs, ds->ds_txstat.ts_rate, txs);
579 void ath_tx_status_update_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
580 struct ath_tx_desc *ds, struct ath_rc_series rcs[],
583 WMI_TXSTATUS_EVENT *txs;
585 if (sc->sc_tx_draining)
588 txs = ath_tx_status_get(sc);
592 txs->txstatus[txs->cnt].cookie = bf->bf_cookie;
593 txs->txstatus[txs->cnt].ts_rate = SM(bf->bf_endpt, ATH9K_HTC_TXSTAT_EPID);
596 txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_ACK;
599 ath_tx_status_update_rate(sc, rcs, ds->ds_txstat.ts_rate, txs);
604 void ath_tx_status_send(struct ath_softc_tgt *sc)
608 if (sc->sc_tx_draining)
611 for (i = 0; i < 2; i++) {
612 if (sc->tx_status[i].cnt) {
613 wmi_event(sc->tgt_wmi_handle, WMI_TXSTATUS_EVENTID,
614 &sc->tx_status[i], sizeof(WMI_TXSTATUS_EVENT));
615 /* FIXME: Handle failures. */
616 sc->tx_status[i].cnt = 0;
621 static void owltgt_tx_process_cabq(struct ath_softc_tgt *sc, struct ath_txq *txq)
623 ath_hal_intrset(sc->sc_ah, sc->sc_imask & ~HAL_INT_SWBA);
624 owltgt_tx_processq(sc, txq, OWL_TXQ_ACTIVE);
625 ath_hal_intrset(sc->sc_ah, sc->sc_imask);
628 void owl_tgt_tx_tasklet(TQUEUE_ARG data)
630 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
634 ath_tx_status_clear(sc);
636 for (i = 0; i < (HAL_NUM_TX_QUEUES - 6); i++) {
637 txq = ATH_TXQ(sc, i);
639 if (ATH_TXQ_SETUP(sc, i)) {
640 if (txq == sc->sc_cabq)
641 owltgt_tx_process_cabq(sc, txq);
643 owltgt_tx_processq(sc, txq, OWL_TXQ_ACTIVE);
647 ath_tx_status_send(sc);
650 void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,
651 owl_txq_state_t txqstate)
653 struct ath_tx_buf *bf;
654 struct ath_tx_desc *ds;
658 if (asf_tailq_empty(&txq->axq_q)) {
659 txq->axq_link = NULL;
660 txq->axq_linkbuf = NULL;
664 bf = asf_tailq_first(&txq->axq_q);
667 status = ath_hal_txprocdesc(sc->sc_ah, ds);
669 if (status == HAL_EINPROGRESS) {
670 if (txqstate == OWL_TXQ_ACTIVE)
672 else if (txqstate == OWL_TXQ_STOPPED) {
673 __stats(sc, tx_stopfiltered);
674 ds->ds_txstat.ts_flags = 0;
675 ds->ds_txstat.ts_status = HAL_OK;
677 ds->ds_txstat.ts_flags = HAL_TX_SW_FILTERED;
681 ATH_TXQ_REMOVE_HEAD(txq, bf, bf_list);
682 if ((asf_tailq_empty(&txq->axq_q))) {
683 __stats(sc, tx_qnull);
684 txq->axq_link = NULL;
685 txq->axq_linkbuf = NULL;
691 ath_tx_status_update(sc, bf);
692 ath_buf_comp(sc, bf);
695 if (txqstate == OWL_TXQ_ACTIVE) {
696 ath_tgt_txq_schedule(sc, txq);
701 static struct ieee80211_frame* ATH_SKB2_WH(adf_nbuf_t skb)
706 adf_nbuf_peek_header(skb, &anbdata, &anblen);
707 return((struct ieee80211_frame *)anbdata);
711 ath_tgt_tid_drain(struct ath_softc_tgt *sc, struct ath_atx_tid *tid)
713 struct ath_tx_buf *bf;
715 while (!asf_tailq_empty(&tid->buf_q)) {
716 TAILQ_DEQ(&tid->buf_q, bf, bf_list);
717 ath_tx_freebuf(sc, bf);
720 tid->seq_next = tid->seq_start;
721 tid->baw_tail = tid->baw_head;
724 static void ath_tgt_tx_comp_normal(struct ath_softc_tgt *sc,
725 struct ath_tx_buf *bf)
727 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
728 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
730 if (tid->flag & TID_CLEANUP_INPROGRES) {
731 owl_tgt_tid_cleanup(sc, tid);
735 ath_tx_uc_comp(sc, bf);
738 ath_tx_freebuf(sc, bf);
741 static struct ieee80211_node_target * ath_tgt_find_node(struct ath_softc_tgt *sc,
742 a_int32_t node_index)
744 struct ath_node_target *an;
745 struct ieee80211_node_target *ni;
747 if (node_index > TARGET_NODE_MAX)
750 an = &sc->sc_sta[node_index];
754 if (ni->ni_vap == NULL) {
763 static struct ath_buf* ath_buf_alloc(struct ath_softc_tgt *sc)
765 struct ath_tx_buf *bf = NULL;
767 bf = asf_tailq_first(&sc->sc_txbuf);
769 adf_os_mem_set(&bf->bf_state, 0, sizeof(struct ath_buf_state));
770 asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
778 struct ath_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc,
779 adf_nbuf_t skb, ath_data_hdr_t *dh)
781 struct ath_tx_buf *bf;
782 struct ieee80211_node_target *ni;
783 struct ath_atx_tid *tid;
785 ni = ath_tgt_find_node(sc, dh->ni_index);
789 tid = ATH_AN_2_TID(ATH_NODE_TARGET(ni), dh->tidno);
790 if (tid->flag & TID_REINITIALIZE) {
791 adf_os_print("drop frame due to TID reinit\n");
795 bf = ath_buf_alloc(sc);
797 __stats(sc, tx_nobufs);
801 bf->bf_tidno = dh->tidno;
802 bf->bf_txq = TID_TO_ACTXQ(bf->bf_tidno);
803 bf->bf_keytype = dh->keytype;
804 bf->bf_keyix = dh->keyix;
805 bf->bf_protmode = dh->flags & (IEEE80211_PROT_RTSCTS | IEEE80211_PROT_CTSONLY);
806 bf->bf_node = (struct ath_node_target *)ni;
808 adf_nbuf_queue_add(&bf->bf_skbhead, skb);
809 skb = adf_nbuf_queue_first(&(bf->bf_skbhead));
811 if (adf_nbuf_queue_len(&(bf->bf_skbhead)) == 0) {
812 __stats(sc, tx_noskbs);
820 ath_tgt_txbuf_setup(sc, bf, dh);
822 ath_tx_tgt_setds(sc, bf);
827 static void ath_tgt_tx_seqno_normal(struct ath_tx_buf *bf)
829 struct ieee80211_node_target *ni = bf->bf_node;
830 struct ath_node_target *an = ATH_NODE_TARGET(ni);
831 struct ieee80211_frame *wh = ATH_SKB_2_WH(bf->bf_skb);
832 struct ath_atx_tid *tid = ATH_AN_2_TID(an, bf->bf_tidno);
834 u_int8_t fragno = (wh->i_seq[0] & 0xf);
836 INCR(ni->ni_txseqmgmt, IEEE80211_SEQ_MAX);
838 bf->bf_seqno = (tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
840 *(u_int16_t *)wh->i_seq = adf_os_cpu_to_le16(bf->bf_seqno);
841 wh->i_seq[0] |= fragno;
843 if (!(wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG))
844 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
847 static a_int32_t ath_key_setup(struct ieee80211_node_target *ni,
848 struct ath_tx_buf *bf)
850 struct ieee80211_frame *wh = ATH_SKB_2_WH(bf->bf_skb);
852 if (!(wh->i_fc[1] & IEEE80211_FC1_WEP)) {
853 bf->bf_keytype = HAL_KEY_TYPE_CLEAR;
854 bf->bf_keyix = HAL_TXKEYIX_INVALID;
858 switch (bf->bf_keytype) {
859 case HAL_KEY_TYPE_WEP:
860 bf->bf_pktlen += IEEE80211_WEP_ICVLEN;
862 case HAL_KEY_TYPE_AES:
863 bf->bf_pktlen += IEEE80211_WEP_MICLEN;
865 case HAL_KEY_TYPE_TKIP:
866 bf->bf_pktlen += IEEE80211_WEP_ICVLEN;
872 if (bf->bf_keytype == HAL_KEY_TYPE_AES ||
873 bf->bf_keytype == HAL_KEY_TYPE_TKIP)
874 ieee80211_tgt_crypto_encap(wh, ni, bf->bf_keytype);
879 static void ath_tgt_txq_add_ucast(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
881 struct ath_hal *ah = sc->sc_ah;
884 volatile a_int32_t txe_val;
890 status = ath_hal_txprocdesc(sc->sc_ah, bf->bf_lastds);
892 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
894 if (txq->axq_link == NULL) {
895 ath_hal_puttxbuf(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
897 *txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
899 txe_val = OS_REG_READ(ah, 0x840);
900 if (!(txe_val & (1<< txq->axq_qnum)))
901 ath_hal_puttxbuf(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
904 txq->axq_link = &bf->bf_lastds->ds_link;
905 ath_hal_txstart(ah, txq->axq_qnum);
908 static a_int32_t ath_tgt_txbuf_setup(struct ath_softc_tgt *sc,
909 struct ath_tx_buf *bf,
913 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
914 struct ieee80211_frame *wh = ATH_SKB2_WH(bf->bf_skb);
915 struct ieee80211_node_target *ni = (struct ieee80211_node_target *)an;
916 struct ieee80211vap_target *vap = ni->ni_vap;
917 struct ieee80211com_target *ic = &sc->sc_ic;
918 a_int32_t retval, fragno = 0;
919 a_uint32_t flags = adf_os_ntohl(dh->flags);
921 ath_tgt_tx_seqno_normal(bf);
923 bf->bf_txq_add = ath_tgt_txq_add_ucast;
924 bf->bf_hdrlen = ieee80211_anyhdrsize(wh);
925 bf->bf_pktlen = ath_get_pktlen(bf, bf->bf_hdrlen);
926 bf->bf_ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
928 if ((retval = ath_key_setup(bf->bf_node, bf)) < 0)
931 if (flags & ATH_SHORT_PREAMBLE)
932 bf->bf_shpream = AH_TRUE;
934 bf->bf_shpream = AH_FALSE;
936 bf->bf_flags = HAL_TXDESC_CLRDMASK;
937 bf->bf_atype = HAL_PKT_TYPE_NORMAL;
943 ath_get_pktlen(struct ath_buf *bf, a_int32_t hdrlen)
945 adf_nbuf_t skb = bf->bf_skb;
948 skb = adf_nbuf_queue_first(&bf->bf_skbhead);
949 pktlen = adf_nbuf_len(skb);
951 pktlen -= (hdrlen & 3);
952 pktlen += IEEE80211_CRC_LEN;
958 ath_tgt_tx_send_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
960 struct ath_node_target *an = bf->bf_node;
961 struct ath_rc_series rcs[4];
962 struct ath_rc_series mrcs[4];
963 a_int32_t shortPreamble = 0;
964 a_int32_t isProbe = 0;
966 adf_os_mem_set(rcs, 0, sizeof(struct ath_rc_series)*4 );
967 adf_os_mem_set(mrcs, 0, sizeof(struct ath_rc_series)*4 );
969 if (!bf->bf_ismcast) {
970 ath_tgt_rate_findrate(sc, an, shortPreamble,
973 ath_hal_memcpy(bf->bf_rcs, rcs, sizeof(rcs));
975 mrcs[1].tries = mrcs[2].tries = mrcs[3].tries = 0;
976 mrcs[1].rix = mrcs[2].rix = mrcs[3].rix = 0;
980 ath_hal_memcpy(bf->bf_rcs, mrcs, sizeof(mrcs));
983 ath_buf_set_rate(sc, bf);
984 bf->bf_txq_add(sc, bf);
988 ath_tx_freebuf(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
991 struct ath_desc *bfd = NULL;
993 for (bfd = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; bfd++, i++) {
994 ath_hal_clr11n_aggr(sc->sc_ah, bfd);
995 ath_hal_set11n_burstduration(sc->sc_ah, bfd, 0);
996 ath_hal_set11n_virtualmorefrag(sc->sc_ah, bfd, 0);
999 ath_dma_unmap(sc, bf);
1001 ath_tgt_skb_free(sc, &bf->bf_skbhead,bf->bf_endpt);
1007 bf = ath_buf_toggle(sc, bf, 0);
1009 bf->bf_isretried = 0;
1012 asf_tailq_insert_tail(&sc->sc_txbuf, bf, bf_list);
1016 ath_tx_uc_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1018 ath_tx_status_update(sc, bf);
1019 ath_update_stats(sc, bf);
1020 ath_rate_tx_complete(sc, ATH_NODE_TARGET(bf->bf_node),
1021 bf->bf_lastds, bf->bf_rcs, 1, 0);
1025 ath_update_stats(struct ath_softc_tgt *sc, struct ath_buf *bf)
1027 struct ath_tx_desc *ds = bf->bf_desc;
1030 if (ds->ds_txstat.ts_status == 0) {
1031 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE)
1032 sc->sc_tx_stats.ast_tx_altrate++;
1034 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY)
1035 sc->sc_tx_stats.ast_tx_xretries++;
1036 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO)
1037 sc->sc_tx_stats.ast_tx_fifoerr++;
1038 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
1039 sc->sc_tx_stats.ast_tx_filtered++;
1040 if (ds->ds_txstat.ts_status & HAL_TXERR_TIMER_EXPIRED)
1041 sc->sc_tx_stats.ast_tx_timer_exp++;
1043 sr = ds->ds_txstat.ts_shortretry;
1044 lr = ds->ds_txstat.ts_longretry;
1045 sc->sc_tx_stats.ast_tx_shortretry += sr;
1046 sc->sc_tx_stats.ast_tx_longretry += lr;
1050 ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t hdr_buf, adf_nbuf_t skb,
1051 HTC_ENDPOINT_ID endpt)
1053 struct ieee80211_node_target *ni;
1054 struct ieee80211vap_target *vap;
1055 struct ath_vap_target *avp;
1056 struct ath_hal *ah = sc->sc_ah;
1057 a_uint8_t rix, txrate, ctsrate, cix = 0xff, *data;
1058 a_uint32_t ivlen = 0, icvlen = 0, subtype, flags, ctsduration;
1059 a_int32_t i, iswep, ismcast, hdrlen, pktlen, try0, len;
1060 struct ath_desc *ds=NULL;
1061 struct ath_txq *txq=NULL;
1062 struct ath_tx_buf *bf;
1064 const HAL_RATE_TABLE *rt;
1065 HAL_BOOL shortPreamble;
1066 struct ieee80211_frame *wh;
1067 struct ath_rc_series rcs[4];
1068 HAL_11N_RATE_SERIES series[4];
1073 adf_nbuf_peek_header(skb, &data, &len);
1074 adf_nbuf_pull_head(skb, sizeof(ath_mgt_hdr_t));
1076 adf_nbuf_peek_header(hdr_buf, &data, &len);
1079 adf_os_assert(len >= sizeof(ath_mgt_hdr_t));
1081 mh = (ath_mgt_hdr_t *)data;
1082 adf_nbuf_peek_header(skb, &data, &len);
1083 wh = (struct ieee80211_frame *)data;
1085 adf_os_mem_set(rcs, 0, sizeof(struct ath_rc_series)*4);
1086 adf_os_mem_set(series, 0, sizeof(HAL_11N_RATE_SERIES)*4);
1088 bf = asf_tailq_first(&sc->sc_txbuf);
1092 asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
1094 ni = ath_tgt_find_node(sc, mh->ni_index);
1098 bf->bf_endpt = endpt;
1099 bf->bf_cookie = mh->cookie;
1100 bf->bf_protmode = mh->flags & (IEEE80211_PROT_RTSCTS | IEEE80211_PROT_CTSONLY);
1101 txq = &sc->sc_txq[1];
1102 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
1103 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
1104 hdrlen = ieee80211_anyhdrsize(wh);
1106 keyix = HAL_TXKEYIX_INVALID;
1107 pktlen -= (hdrlen & 3);
1108 pktlen += IEEE80211_CRC_LEN;
1113 adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, skb, ADF_OS_DMA_TO_DEVICE);
1116 adf_nbuf_queue_add(&bf->bf_skbhead, skb);
1119 rt = sc->sc_currates;
1120 adf_os_assert(rt != NULL);
1122 if (mh->flags == ATH_SHORT_PREAMBLE)
1123 shortPreamble = AH_TRUE;
1125 shortPreamble = AH_FALSE;
1127 flags = HAL_TXDESC_CLRDMASK;
1129 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
1130 case IEEE80211_FC0_TYPE_MGT:
1131 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
1133 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
1134 atype = HAL_PKT_TYPE_PROBE_RESP;
1135 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM)
1136 atype = HAL_PKT_TYPE_ATIM;
1138 atype = HAL_PKT_TYPE_NORMAL;
1142 atype = HAL_PKT_TYPE_NORMAL;
1146 avp = &sc->sc_vap[mh->vap_index];
1148 rcs[0].rix = ath_get_minrateidx(sc, avp);
1149 rcs[0].tries = ATH_TXMAXTRY;
1152 adf_os_mem_copy(bf->bf_rcs, rcs, sizeof(rcs));
1154 try0 = rcs[0].tries;
1155 txrate = rt->info[rix].rateCode;
1158 txrate |= rt->info[rix].shortPreamble;
1165 flags |= HAL_TXDESC_NOACK;
1167 } else if (pktlen > vap->iv_rtsthreshold) {
1168 flags |= HAL_TXDESC_RTSENA;
1169 cix = rt->info[rix].controlRate;
1172 if ((bf->bf_protmode != IEEE80211_PROT_NONE) &&
1173 rt->info[rix].phy == IEEE80211_T_OFDM &&
1174 (flags & HAL_TXDESC_NOACK) == 0) {
1175 cix = rt->info[sc->sc_protrix].controlRate;
1176 sc->sc_tx_stats.ast_tx_protect++;
1179 *(a_uint16_t *)&wh->i_seq[0] = adf_os_cpu_to_le16(ni->ni_txseqmgmt <<
1180 IEEE80211_SEQ_SEQ_SHIFT);
1181 INCR(ni->ni_txseqmgmt, IEEE80211_SEQ_MAX);
1184 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) {
1185 adf_os_assert(cix != 0xff);
1186 ctsrate = rt->info[cix].rateCode;
1187 if (shortPreamble) {
1188 ctsrate |= rt->info[cix].shortPreamble;
1189 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
1190 ctsduration += rt->info[cix].spAckDuration;
1191 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
1192 ctsduration += rt->info[cix].spAckDuration;
1194 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
1195 ctsduration += rt->info[cix].lpAckDuration;
1196 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
1197 ctsduration += rt->info[cix].lpAckDuration;
1199 ctsduration += ath_hal_computetxtime(ah,
1200 rt, pktlen, rix, shortPreamble);
1205 flags |= HAL_TXDESC_INTREQ;
1207 ath_hal_setuptxdesc(ah, ds
1220 , ATH_COMP_PROC_NO_COMP_NO_CCS);
1222 bf->bf_flags = flags;
1225 * Set key type in tx desc while sending the encrypted challenge to AP
1226 * in Auth frame 3 of Shared Authentication, owl needs this.
1228 if (iswep && (keyix != HAL_TXKEYIX_INVALID) &&
1229 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == IEEE80211_FC0_SUBTYPE_AUTH)
1230 ath_hal_fillkeytxdesc(ah, ds, mh->keytype);
1232 ath_filltxdesc(sc, bf);
1234 for (i=0; i<4; i++) {
1235 series[i].Tries = 2;
1236 series[i].Rate = txrate;
1237 series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
1238 series[i].RateFlags = 0;
1240 ath_hal_set11n_ratescenario(ah, ds, 0, ctsrate, ctsduration, series, 4, 0);
1241 ath_tgt_txqaddbuf(sc, txq, bf, bf->bf_lastds);
1245 HTC_ReturnBuffers(sc->tgt_htc_handle, endpt, skb);
1250 ath_tgt_txqaddbuf(struct ath_softc_tgt *sc,
1251 struct ath_txq *txq, struct ath_buf *bf,
1252 struct ath_desc *lastds)
1254 struct ath_hal *ah = sc->sc_ah;
1256 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
1258 if (txq->axq_link == NULL) {
1259 ath_hal_puttxbuf(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
1261 *txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
1264 txq->axq_link = &lastds->ds_link;
1265 ath_hal_txstart(ah, txq->axq_qnum);
1268 void ath_tgt_handle_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1271 struct ath_node_target *an;
1273 an = (struct ath_node_target *)bf->bf_node;
1276 tid = &an->tid[bf->bf_tidno];
1279 bf->bf_comp = ath_tgt_tx_comp_normal;
1280 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1281 ath_tgt_tx_send_normal(sc, bf);
1285 ath_tgt_tx_enqueue(struct ath_txq *txq, struct ath_atx_tid *tid)
1293 tid->sched = AH_TRUE;
1294 asf_tailq_insert_tail(&txq->axq_tidq, tid, tid_qelem);
1298 ath_tgt_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1300 struct ath_atx_tid *tid;
1306 TAILQ_DEQ(&txq->axq_tidq, tid, tid_qelem);
1311 tid->sched = AH_FALSE;
1316 if (!(tid->flag & TID_AGGR_ENABLED))
1317 ath_tgt_tx_sched_normal(sc,tid);
1319 ath_tgt_tx_sched_aggr(sc,tid);
1323 if (!asf_tailq_empty(&tid->buf_q)) {
1324 ath_tgt_tx_enqueue(txq, tid);
1327 } while (!asf_tailq_empty(&txq->axq_tidq) && !bdone);
1331 ath_tgt_handle_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1334 struct ath_node_target *an;
1335 struct ath_txq *txq = bf->bf_txq;
1336 a_bool_t queue_frame, within_baw;
1338 an = (struct ath_node_target *)bf->bf_node;
1341 tid = &an->tid[bf->bf_tidno];
1344 bf->bf_comp = ath_tgt_tx_comp_aggr;
1346 within_baw = BAW_WITHIN(tid->seq_start, tid->baw_size,
1347 SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1349 queue_frame = ( (txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) ||
1350 (!asf_tailq_empty(&tid->buf_q)) ||
1351 (tid->paused) || (!within_baw) );
1354 asf_tailq_insert_tail(&tid->buf_q, bf, bf_list);
1355 ath_tgt_tx_enqueue(txq, tid);
1357 ath_tx_addto_baw(tid, bf);
1358 __stats(sc, txaggr_nframes);
1359 ath_tgt_tx_send_normal(sc, bf);
1364 ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
1367 struct ath_txq *txq =TID_TO_ACTXQ(tid->tidno);;
1370 if (asf_tailq_empty(&tid->buf_q))
1373 bf = asf_tailq_first(&tid->buf_q);
1374 asf_tailq_remove(&tid->buf_q, bf, bf_list);
1375 ath_tgt_tx_send_normal(sc, bf);
1377 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH);
1381 ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
1383 struct ath_tx_buf *bf, *bf_last;
1384 ATH_AGGR_STATUS status;
1386 struct ath_txq *txq = TID_TO_ACTXQ(tid->tidno);
1387 struct ath_desc *ds = NULL;
1391 if (asf_tailq_empty(&tid->buf_q))
1395 if (asf_tailq_empty(&tid->buf_q))
1398 asf_tailq_init(&bf_q);
1400 status = ath_tgt_tx_form_aggr(sc, tid, &bf_q);
1402 if (asf_tailq_empty(&bf_q))
1405 bf = asf_tailq_first(&bf_q);
1406 bf_last = asf_tailq_last(&bf_q, ath_bufhead_s);
1408 if (bf->bf_nframes == 1) {
1410 if(bf->bf_retries == 0)
1411 __stats(sc, txaggr_single);
1413 bf->bf_lastds = &(bf->bf_descarr[bf->bf_dmamap_info.nsegs -1]);
1414 bf->bf_lastds->ds_link = 0;
1417 for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
1418 ath_hal_clr11n_aggr(sc->sc_ah, ds);
1420 ath_buf_set_rate(sc, bf);
1421 bf->bf_txq_add(sc, bf);
1426 bf_last->bf_next = NULL;
1427 bf_last->bf_lastds->ds_link = 0;
1428 bf_last->bf_ndelim = 0;
1431 ath_buf_set_rate(sc, bf);
1432 ath_hal_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al,
1434 bf->bf_lastds = bf_last->bf_lastds;
1436 for (i = 0; i < bf_last->bf_dmamap_info.nsegs; i++)
1437 ath_hal_set11n_aggr_last(sc->sc_ah, &bf_last->bf_descarr[i]);
1439 if (status == ATH_AGGR_8K_LIMITED) {
1444 bf->bf_txq_add(sc, bf);
1445 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
1446 status != ATH_TGT_AGGR_BAW_CLOSED);
1449 static u_int32_t ath_lookup_rate(struct ath_softc_tgt *sc,
1450 struct ath_node_target *an,
1451 struct ath_tx_buf *bf)
1454 u_int32_t max4msframelen, frame_length;
1455 u_int16_t aggr_limit, legacy=0;
1456 const HAL_RATE_TABLE *rt = sc->sc_currates;
1457 struct ieee80211_node_target *ieee_node = (struct ieee80211_node_target *)an;
1459 if (bf->bf_ismcast) {
1460 bf->bf_rcs[1].tries = bf->bf_rcs[2].tries = bf->bf_rcs[3].tries = 0;
1461 bf->bf_rcs[0].rix = 0xb;
1462 bf->bf_rcs[0].tries = ATH_TXMAXTRY - 1;
1463 bf->bf_rcs[0].flags = 0;
1465 ath_tgt_rate_findrate(sc, an, AH_TRUE, 0, ATH_TXMAXTRY-1, 4, 1,
1466 ATH_RC_PROBE_ALLOWED, bf->bf_rcs, &prate);
1469 max4msframelen = IEEE80211_AMPDU_LIMIT_MAX;
1471 for (i = 0; i < 4; i++) {
1472 if (bf->bf_rcs[i].tries) {
1473 frame_length = bf->bf_rcs[i].max4msframelen;
1475 if (rt->info[bf->bf_rcs[i].rix].phy != IEEE80211_T_HT) {
1480 max4msframelen = ATH_MIN(max4msframelen, frame_length);
1484 if (prate || legacy)
1487 if (sc->sc_ic.ic_enable_coex)
1488 aggr_limit = ATH_MIN((max4msframelen*3)/8, sc->sc_ic.ic_ampdu_limit);
1490 aggr_limit = ATH_MIN(max4msframelen, sc->sc_ic.ic_ampdu_limit);
1492 if (ieee_node->ni_maxampdu)
1493 aggr_limit = ATH_MIN(aggr_limit, ieee_node->ni_maxampdu);
1498 int ath_tgt_tx_form_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid,
1501 struct ath_tx_buf *bf_first ,*bf_prev = NULL;
1502 int nframes = 0, rl = 0;;
1503 struct ath_desc *ds = NULL;
1504 struct ath_tx_buf *bf;
1505 u_int16_t aggr_limit = (64*1024 -1), al = 0, bpad = 0, al_delta;
1506 u_int16_t h_baw = tid->baw_size/2, prev_al = 0, prev_frames = 0;
1508 bf_first = asf_tailq_first(&tid->buf_q);
1511 bf = asf_tailq_first(&tid->buf_q);
1514 if (!BAW_WITHIN(tid->seq_start, tid->baw_size,
1515 SEQNO_FROM_BF_SEQNO(bf->bf_seqno))) {
1517 bf_first->bf_al= al;
1518 bf_first->bf_nframes = nframes;
1519 return ATH_TGT_AGGR_BAW_CLOSED;
1523 aggr_limit = ath_lookup_rate(sc, tid->an, bf);
1527 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_pktlen;
1529 if (nframes && (aggr_limit < (al + bpad + al_delta + prev_al))) {
1530 bf_first->bf_al= al;
1531 bf_first->bf_nframes = nframes;
1532 return ATH_TGT_AGGR_LIMITED;
1536 if ((nframes + prev_frames) >= ATH_MIN((h_baw), 17)) {
1538 if ((nframes + prev_frames) >= ATH_MIN((h_baw), 22)) {
1540 bf_first->bf_al= al;
1541 bf_first->bf_nframes = nframes;
1542 return ATH_TGT_AGGR_LIMITED;
1545 ath_tx_addto_baw(tid, bf);
1546 asf_tailq_remove(&tid->buf_q, bf, bf_list);
1547 asf_tailq_insert_tail(bf_q, bf, bf_list);
1552 adf_os_assert(bf->bf_comp == ath_tgt_tx_comp_aggr);
1554 al += bpad + al_delta;
1555 bf->bf_ndelim = ATH_AGGR_GET_NDELIM(bf->bf_pktlen);
1557 switch (bf->bf_keytype) {
1558 case HAL_KEY_TYPE_AES:
1559 bf->bf_ndelim += ATH_AGGR_ENCRYPTDELIM;
1561 case HAL_KEY_TYPE_WEP:
1562 case HAL_KEY_TYPE_TKIP:
1563 bf->bf_ndelim += 64;
1565 case HAL_KEY_TYPE_WAPI:
1566 bf->bf_ndelim += 12;
1572 bpad = PADBYTES(al_delta) + (bf->bf_ndelim << 2);
1575 bf_prev->bf_next = bf;
1576 bf_prev->bf_lastds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
1580 for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
1581 ath_hal_set11n_aggr_middle(sc->sc_ah, ds, bf->bf_ndelim);
1583 } while (!asf_tailq_empty(&tid->buf_q));
1585 bf_first->bf_al= al;
1586 bf_first->bf_nframes = nframes;
1588 return ATH_TGT_AGGR_DONE;
1591 void ath_tx_addto_baw(ath_atx_tid_t *tid, struct ath_tx_buf *bf)
1595 if (bf->bf_isretried) {
1599 index = ATH_BA_INDEX(tid->seq_start, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1600 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1602 TX_BUF_BITMAP_SET(tid->tx_buf_bitmap, cindex);
1604 if (index >= ((tid->baw_tail - tid->baw_head) & (ATH_TID_MAX_BUFS - 1))) {
1605 tid->baw_tail = cindex;
1606 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
1610 void ath_tgt_tx_comp_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1612 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1613 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1614 struct ath_tx_desc lastds;
1615 struct ath_tx_desc *ds = &lastds;
1616 struct ath_rc_series rcs[4];
1621 int nframes = bf->bf_nframes;
1622 struct ath_buf *bf_next;
1625 struct ath_buf *bar = NULL;
1626 struct ath_txq *txq;
1630 if (tid->flag & TID_CLEANUP_INPROGRES) {
1631 ath_tx_comp_cleanup(sc, bf);
1635 adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
1636 adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
1638 if (ds->ds_txstat.ts_flags == HAL_TX_SW_FILTERED) {
1643 if (!bf->bf_isaggr) {
1644 ath_tx_comp_unaggr(sc, bf);
1648 __stats(sc, tx_compaggr);
1650 asf_tailq_init(&bf_q);
1652 seq_st = ATH_DS_BA_SEQ(ds);
1653 ba = ATH_DS_BA_BITMAP(ds);
1654 tx_ok = (ATH_DS_TX_STATUS(ds) == HAL_OK);
1656 if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
1657 ath_tx_comp_aggr_error(sc, bf, tid);
1661 if (tx_ok && !ATH_DS_TX_BA(ds)) {
1662 __stats(sc, txaggr_babug);
1663 adf_os_print("BA Bug?\n");
1664 ath_tx_comp_aggr_error(sc, bf, tid);
1669 ba_index = ATH_BA_INDEX(seq_st, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1670 bf_next = bf->bf_next;
1672 if (tx_ok && ATH_BA_ISSET(ba, ba_index)) {
1673 __stats(sc, txaggr_compgood);
1674 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1675 ath_tx_status_update_aggr(sc, bf, ds, rcs, 1);
1676 ath_tx_freebuf(sc, bf);
1678 ath_tx_retry_subframe(sc, bf, &bf_q, &bar);
1684 ath_update_aggr_stats(sc, ds, nframes, nbad);
1685 ath_rate_tx_complete(sc, an, ds, rcs, nframes, nbad);
1688 ath_bar_tx(sc, tid, bar);
1691 if (!asf_tailq_empty(&bf_q)) {
1692 __stats(sc, txaggr_prepends);
1693 TAILQ_INSERTQ_HEAD(&tid->buf_q, &bf_q, bf_list);
1694 ath_tgt_tx_enqueue(txq, tid);
1699 ath_tx_comp_aggr_error(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
1704 struct ath_tx_desc lastds;
1705 struct ath_desc *ds = &lastds;
1706 struct ath_rc_series rcs[4];
1707 struct ath_buf *bar = NULL;
1708 struct ath_buf *bf_next;
1709 int nframes = bf->bf_nframes;
1711 struct ath_txq *txq;
1713 asf_tailq_init(&bf_q);
1716 adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
1717 adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
1720 bf_next = bf->bf_next;
1721 ath_tx_retry_subframe(sc, bf, &bf_q, &bar);
1725 ath_update_aggr_stats(sc, ds, nframes, nframes);
1726 ath_rate_tx_complete(sc, tid->an, ds, rcs, nframes, nframes);
1729 ath_bar_tx(sc, tid, bar);
1732 if (!asf_tailq_empty(&bf_q)) {
1733 __stats(sc, txaggr_prepends);
1734 TAILQ_INSERTQ_HEAD(&tid->buf_q, &bf_q, bf_list);
1735 ath_tgt_tx_enqueue(txq, tid);
1740 ath_tx_comp_cleanup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1743 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1744 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1745 struct ath_tx_desc lastds;
1746 struct ath_tx_desc *ds = &lastds;
1747 struct ath_rc_series rcs[4];
1752 int nframes = bf->bf_nframes;
1753 struct ath_buf *bf_next;
1756 adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
1757 adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
1759 seq_st = ATH_DS_BA_SEQ(ds);
1760 ba = ATH_DS_BA_BITMAP(ds);
1761 tx_ok = (ATH_DS_TX_STATUS(ds) == HAL_OK);
1763 if (!bf->bf_isaggr) {
1764 ath_update_stats(sc, bf);
1766 __stats(sc, tx_compunaggr);
1768 ath_tx_status_update(sc, bf);
1770 ath_tx_freebuf(sc, bf);
1772 if (tid->flag & TID_CLEANUP_INPROGRES) {
1773 owl_tgt_tid_cleanup(sc, tid);
1781 ba_index = ATH_BA_INDEX(seq_st, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1782 bf_next = bf->bf_next;
1784 ath_tx_status_update_aggr(sc, bf, ds, rcs, 0);
1786 ath_tx_freebuf(sc, bf);
1790 tid->flag &= ~TID_CLEANUP_INPROGRES;
1791 ath_aggr_resume_tid(sc, tid);
1798 ath_update_aggr_stats(sc, ds, nframes, nbad);
1799 ath_rate_tx_complete(sc, an, ds, rcs, nframes, nbad);
1803 ath_tx_retry_subframe(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
1804 ath_bufhead *bf_q, struct ath_tx_buf **bar)
1807 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1808 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1809 struct ath_desc *ds = NULL;
1812 __stats(sc, txaggr_compretries);
1814 for(ds = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; ds++, i++) {
1815 ath_hal_clr11n_aggr(sc->sc_ah, ds);
1816 ath_hal_set11n_burstduration(sc->sc_ah, ds, 0);
1817 ath_hal_set11n_virtualmorefrag(sc->sc_ah, ds, 0);
1820 if (bf->bf_retries >= OWLMAX_RETRIES) {
1821 __stats(sc, txaggr_xretries);
1822 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1823 ath_tx_status_update_aggr(sc, bf, bf->bf_lastds, NULL, 0);
1828 ath_tx_freebuf(sc, bf);
1833 __stats(sc, txaggr_errlast);
1834 bf = ath_buf_toggle(sc, bf, 1);
1836 bf->bf_lastds = &(bf->bf_descarr[bf->bf_dmamap_info.nsegs - 1]);
1838 ath_tx_set_retry(sc, bf);
1839 asf_tailq_insert_tail(bf_q, bf, bf_list);
1843 ath_update_aggr_stats(struct ath_softc_tgt *sc,
1844 struct ath_tx_desc *ds, int nframes,
1848 u_int8_t status = ATH_DS_TX_STATUS(ds);
1849 u_int8_t txflags = ATH_DS_TX_FLAGS(ds);
1851 __statsn(sc, txaggr_longretries, ds->ds_txstat.ts_longretry);
1852 __statsn(sc, txaggr_shortretries, ds->ds_txstat.ts_shortretry);
1854 if (txflags & HAL_TX_DESC_CFG_ERR)
1855 __stats(sc, txaggr_desc_cfgerr);
1857 if (txflags & HAL_TX_DATA_UNDERRUN)
1858 __stats(sc, txaggr_data_urun);
1860 if (txflags & HAL_TX_DELIM_UNDERRUN)
1861 __stats(sc, txaggr_delim_urun);
1867 if (status & HAL_TXERR_XRETRY)
1868 __stats(sc, txaggr_compxretry);
1870 if (status & HAL_TXERR_FILT)
1871 __stats(sc, txaggr_filtered);
1873 if (status & HAL_TXERR_FIFO)
1874 __stats(sc, txaggr_fifo);
1876 if (status & HAL_TXERR_XTXOP)
1877 __stats(sc, txaggr_xtxop);
1879 if (status & HAL_TXERR_TIMER_EXPIRED)
1880 __stats(sc, txaggr_timer_exp);
1884 ath_tx_comp_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1886 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1887 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1888 struct ath_desc *ds = bf->bf_lastds;
1890 ath_update_stats(sc, bf);
1891 ath_rate_tx_complete(sc, an, ds, bf->bf_rcs, 1, 0);
1893 if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
1894 ath_tx_retry_unaggr(sc, bf);
1897 __stats(sc, tx_compunaggr);
1899 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1900 ath_tx_status_update(sc, bf);
1901 ath_tx_freebuf(sc, bf);
1905 ath_tx_retry_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1907 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1908 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1909 struct ath_txq *txq;
1913 if (bf->bf_retries >= OWLMAX_RETRIES) {
1914 __stats(sc, txunaggr_xretry);
1915 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1916 ath_tx_status_update(sc, bf);
1917 ath_bar_tx(sc, tid, bf);
1921 __stats(sc, txunaggr_compretries);
1922 if (!bf->bf_lastds->ds_link) {
1923 __stats(sc, txunaggr_errlast);
1924 bf = ath_buf_toggle(sc, bf, 1);
1927 ath_tx_set_retry(sc, bf);
1928 asf_tailq_insert_head(&tid->buf_q, bf, bf_list);
1929 ath_tgt_tx_enqueue(txq, tid);
1933 ath_tx_update_baw(ath_atx_tid_t *tid, int seqno)
1938 index = ATH_BA_INDEX(tid->seq_start, seqno);
1939 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1941 TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, cindex);
1943 while (tid->baw_head != tid->baw_tail &&
1944 (!TX_BUF_BITMAP_IS_SET(tid->tx_buf_bitmap, tid->baw_head))) {
1945 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1946 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
1950 static void ath_tx_set_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1952 struct ieee80211_frame *wh;
1954 __stats(sc, txaggr_retries);
1956 bf->bf_isretried = 1;
1958 wh = ATH_SKB_2_WH(bf->bf_skb);
1959 wh->i_fc[1] |= IEEE80211_FC1_RETRY;
1962 void ath_tgt_tx_cleanup(struct ath_softc_tgt *sc, struct ath_node_target *an,
1963 ath_atx_tid_t *tid, a_uint8_t discard_all)
1965 struct ath_tx_buf *bf;
1966 struct ath_tx_buf *bf_next;
1967 struct ath_txq *txq;
1969 txq = TID_TO_ACTXQ(tid->tidno);
1971 bf = asf_tailq_first(&tid->buf_q);
1974 if (discard_all || bf->bf_isretried) {
1975 bf_next = asf_tailq_next(bf, bf_list);
1976 TAILQ_DEQ(&tid->buf_q, bf, bf_list);
1977 if (bf->bf_isretried)
1978 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1979 ath_tx_freebuf(sc, bf);
1983 bf->bf_comp = ath_tgt_tx_comp_normal;
1984 bf = asf_tailq_next(bf, bf_list);
1987 ath_aggr_pause_tid(sc, tid);
1989 while (tid->baw_head != tid->baw_tail) {
1990 if (TX_BUF_BITMAP_IS_SET(tid->tx_buf_bitmap, tid->baw_head)) {
1992 tid->flag |= TID_CLEANUP_INPROGRES;
1993 TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, tid->baw_head);
1995 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
1996 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1999 if (!(tid->flag & TID_CLEANUP_INPROGRES)) {
2000 ath_aggr_resume_tid(sc, tid);
2004 /******************/
2005 /* BAR Management */
2006 /******************/
2008 static void ath_tgt_delba_send(struct ath_softc_tgt *sc,
2009 struct ieee80211_node_target *ni,
2010 a_uint8_t tidno, a_uint8_t initiator,
2011 a_uint16_t reasoncode)
2013 struct ath_node_target *an = ATH_NODE_TARGET(ni);
2014 ath_atx_tid_t *tid = ATH_AN_2_TID(an, tidno);
2015 struct wmi_data_delba wmi_delba;
2017 tid->flag &= ~TID_AGGR_ENABLED;
2019 ath_tgt_tx_cleanup(sc, an, tid, 1);
2021 wmi_delba.ni_nodeindex = ni->ni_nodeindex;
2022 wmi_delba.tidno = tid->tidno;
2023 wmi_delba.initiator = 1;
2024 wmi_delba.reasoncode = IEEE80211_REASON_UNSPECIFIED;
2026 __stats(sc, txbar_xretry);
2027 wmi_event(sc->tgt_wmi_handle,
2033 static void ath_bar_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
2035 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
2036 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
2038 if (bf->bf_retries >= OWLMAX_BAR_RETRIES) {
2039 ath_tgt_delba_send(sc, bf->bf_node, tid->tidno, 1,
2040 IEEE80211_REASON_UNSPECIFIED);
2041 ath_tgt_tid_drain(sc, tid);
2044 ath_buf_comp(sc, bf);
2048 __stats(sc, txbar_compretries);
2050 if (!bf->bf_lastds->ds_link) {
2051 __stats(sc, txbar_errlast);
2052 bf = ath_buf_toggle(sc, bf, 1);
2055 bf->bf_lastds->ds_link = 0;
2057 ath_tx_set_retry(sc, bf);
2058 ath_tgt_txq_add_ucast(sc, bf);
2061 static void ath_bar_tx_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
2063 struct ath_desc *ds = bf->bf_lastds;
2064 struct ath_node_target *an;
2066 struct ath_txq *txq;
2068 an = (struct ath_node_target *)bf->bf_node;
2069 tid = &an->tid[bf->bf_tidno];
2070 txq = TID_TO_ACTXQ(tid->tidno);
2072 if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
2073 ath_bar_retry(sc, bf);
2077 ath_aggr_resume_tid(sc, tid);
2080 ath_buf_comp(sc, bf);
2083 static void ath_bar_tx(struct ath_softc_tgt *sc,
2084 ath_atx_tid_t *tid, struct ath_tx_buf *bf)
2087 struct ieee80211_frame_bar *bar;
2089 struct ath_desc *ds, *ds0;
2090 HAL_11N_RATE_SERIES series[4];
2092 adf_nbuf_queue_t skbhead;
2096 __stats(sc, tx_bars);
2098 memset(&series, 0, sizeof(series));
2100 ath_aggr_pause_tid(sc, tid);
2102 skb = adf_nbuf_queue_remove(&bf->bf_skbhead);
2103 adf_nbuf_peek_header(skb, &anbdata, &anblen);
2104 adf_nbuf_trim_tail(skb, anblen);
2105 bar = (struct ieee80211_frame_bar *) anbdata;
2109 ath_dma_unmap(sc, bf);
2110 adf_nbuf_queue_add(&bf->bf_skbhead, skb);
2112 bar->i_fc[1] = IEEE80211_FC1_DIR_NODS;
2113 bar->i_fc[0] = IEEE80211_FC0_VERSION_0 |
2114 IEEE80211_FC0_TYPE_CTL |
2115 IEEE80211_FC0_SUBTYPE_BAR;
2116 bar->i_ctl = tid->tidno << IEEE80211_BAR_CTL_TID_S |
2117 IEEE80211_BAR_CTL_COMBA;
2118 bar->i_seq = adf_os_cpu_to_le16(tid->seq_start << IEEE80211_SEQ_SEQ_SHIFT);
2120 bf->bf_seqno = tid->seq_start << IEEE80211_SEQ_SEQ_SHIFT;
2122 adf_nbuf_put_tail(skb, sizeof(struct ieee80211_frame_bar));
2124 bf->bf_comp = ath_bar_tx_comp;
2125 bf->bf_tidno = tid->tidno;
2126 bf->bf_node = &tid->an->ni;
2127 ath_dma_map(sc, bf);
2128 adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info);
2131 ath_hal_setuptxdesc(sc->sc_ah, ds
2132 , adf_nbuf_len(skb) + IEEE80211_CRC_LEN
2134 , HAL_PKT_TYPE_NORMAL
2141 | HAL_TXDESC_CLRDMASK
2143 , ATH_COMP_PROC_NO_COMP_NO_CCS);
2145 skbhead = bf->bf_skbhead;
2149 for (ds0 = ds, i=0; i < bf->bf_dmamap_info.nsegs; ds0++, i++) {
2150 ath_hal_clr11n_aggr(sc->sc_ah, ds0);
2153 ath_filltxdesc(sc, bf);
2155 for (i = 0 ; i < 4; i++) {
2156 series[i].Tries = ATH_TXMAXTRY;
2157 series[i].Rate = min_rate;
2158 series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
2161 ath_hal_set11n_ratescenario(sc->sc_ah, bf->bf_desc, 0, 0, 0, series, 4, 4);
2162 ath_tgt_txq_add_ucast(sc, bf);