2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <adf_os_types.h>
37 #include <adf_os_dma.h>
38 #include <adf_os_timer.h>
39 #include <adf_os_lock.h>
40 #include <adf_os_io.h>
41 #include <adf_os_mem.h>
42 #include <adf_os_util.h>
43 #include <adf_os_stdtypes.h>
44 #include <adf_os_defer.h>
45 #include <adf_os_atomic.h>
48 #include <adf_net_wcmd.h>
52 #ifdef USE_HEADERLEN_RESV
56 #include <ieee80211_var.h>
57 #include "if_athrate.h"
58 #include "if_athvar.h"
60 #include "ah_internal.h"
62 #define ath_tgt_free_skb adf_nbuf_free
64 #define OFDM_PLCP_BITS 22
65 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
66 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
72 #define HT_LTF(_ns) (4 * (_ns))
73 #define SYMBOL_TIME(_ns) ((_ns) << 2) // ns * 4 us
74 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) // ns * 3.6 us
76 static a_uint16_t bits_per_symbol[][2] = {
78 { 26, 54 }, // 0: BPSK
79 { 52, 108 }, // 1: QPSK 1/2
80 { 78, 162 }, // 2: QPSK 3/4
81 { 104, 216 }, // 3: 16-QAM 1/2
82 { 156, 324 }, // 4: 16-QAM 3/4
83 { 208, 432 }, // 5: 64-QAM 2/3
84 { 234, 486 }, // 6: 64-QAM 3/4
85 { 260, 540 }, // 7: 64-QAM 5/6
86 { 52, 108 }, // 8: BPSK
87 { 104, 216 }, // 9: QPSK 1/2
88 { 156, 324 }, // 10: QPSK 3/4
89 { 208, 432 }, // 11: 16-QAM 1/2
90 { 312, 648 }, // 12: 16-QAM 3/4
91 { 416, 864 }, // 13: 64-QAM 2/3
92 { 468, 972 }, // 14: 64-QAM 3/4
93 { 520, 1080 }, // 15: 64-QAM 5/6
96 void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,
97 owl_txq_state_t txqstate);
98 static void ath_tgt_txqaddbuf(struct ath_softc_tgt *sc, struct ath_txq *txq,
99 struct ath_tx_buf *bf, struct ath_tx_desc *lastds);
100 void ath_rate_findrate_11n_Hardcoded(struct ath_softc_tgt *sc,
101 struct ath_rc_series series[]);
102 void ath_buf_set_rate_Hardcoded(struct ath_softc_tgt *sc,
103 struct ath_tx_buf *bf) ;
104 static a_int32_t ath_tgt_txbuf_setup(struct ath_softc_tgt *sc,
105 struct ath_tx_buf *bf, ath_data_hdr_t *dh);
106 static void ath_tx_freebuf(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
107 static void ath_tx_uc_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
108 static void ath_update_stats(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
109 void adf_print_buf(adf_nbuf_t buf);
110 static void ath_tgt_tx_enqueue(struct ath_txq *txq, struct ath_atx_tid *tid);
112 void ath_tgt_tx_comp_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
113 struct ieee80211_frame *ATH_SKB_2_WH(adf_nbuf_t skb);
115 void ath_tgt_tx_send_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
117 static void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
118 static void ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
120 extern a_int32_t ath_chainmask_sel_logic(void *);
121 static a_int32_t ath_get_pktlen(struct ath_tx_buf *bf, a_int32_t hdrlen);
122 static void ath_tgt_txq_schedule(struct ath_softc_tgt *sc, struct ath_txq *txq);
124 typedef void (*ath_ft_set_atype_t)(struct ath_softc_tgt *sc, struct ath_buf *bf);
127 ath_tx_set_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
130 ath_bar_tx(struct ath_softc_tgt *sc, ath_atx_tid_t *tid, struct ath_tx_buf *bf);
132 ath_tx_update_baw(ath_atx_tid_t *tid, int seqno);
134 ath_tx_retry_subframe(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
135 ath_tx_bufhead *bf_q, struct ath_tx_buf **bar);
138 ath_tx_comp_aggr_error(struct ath_softc_tgt *sc, struct ath_tx_buf *bf, ath_atx_tid_t *tid);
140 void ath_tx_addto_baw(ath_atx_tid_t *tid, struct ath_tx_buf *bf);
141 static inline void ath_tx_retry_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
142 static void ath_tx_comp_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
143 static void ath_update_aggr_stats(struct ath_softc_tgt *sc, struct ath_tx_desc *ds,
144 int nframes, int nbad);
145 static inline void ath_aggr_resume_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
146 static void ath_tx_comp_cleanup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
148 int ath_tgt_tx_add_to_aggr(struct ath_softc_tgt *sc,
149 struct ath_buf *bf,int datatype,
150 ath_atx_tid_t *tid, int is_burst);
151 int ath_tgt_tx_form_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid,
152 ath_tx_bufhead *bf_q);
154 struct ieee80211_frame *ATH_SKB_2_WH(adf_nbuf_t skb)
159 adf_nbuf_peek_header(skb, &anbdata, &anblen);
161 return((struct ieee80211_frame *)anbdata);
164 #undef adf_os_cpu_to_le16
166 static a_uint16_t adf_os_cpu_to_le16(a_uint16_t x)
168 return ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8));
172 ath_aggr_resume_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
176 txq = TID_TO_ACTXQ(tid->tidno);
179 if (asf_tailq_empty(&tid->buf_q))
182 ath_tgt_tx_enqueue(txq, tid);
183 ath_tgt_txq_schedule(sc, txq);
187 ath_aggr_pause_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
192 static a_uint32_t ath_pkt_duration(struct ath_softc_tgt *sc,
193 a_uint8_t rix, struct ath_tx_buf *bf,
194 a_int32_t width, a_int32_t half_gi)
196 const HAL_RATE_TABLE *rt = sc->sc_currates;
197 a_uint32_t nbits, nsymbits, duration, nsymbols;
202 pktlen = bf->bf_isaggr ? bf->bf_al : bf->bf_pktlen;
203 rc = rt->info[rix].rateCode;
206 return ath_hal_computetxtime(sc->sc_ah, rt, pktlen, rix,
209 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
210 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
211 nsymbols = (nbits + nsymbits - 1) / nsymbits;
214 duration = SYMBOL_TIME(nsymbols);
216 duration = SYMBOL_TIME_HALFGI(nsymbols);
218 streams = HT_RC_2_STREAMS(rc);
219 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
224 static void ath_dma_map(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
226 adf_nbuf_t skb = bf->bf_skb;
228 skb = adf_nbuf_queue_first(&bf->bf_skbhead);
229 adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, skb, ADF_OS_DMA_TO_DEVICE);
232 static void ath_dma_unmap(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
234 adf_nbuf_t skb = bf->bf_skb;
236 skb = adf_nbuf_queue_first(&bf->bf_skbhead);
237 adf_nbuf_unmap( sc->sc_dev, bf->bf_dmamap, ADF_OS_DMA_TO_DEVICE);
240 static void ath_filltxdesc(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
242 struct ath_tx_desc *ds0, *ds = bf->bf_desc;
243 struct ath_hal *ah = sc->sc_ah;
247 adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info);
249 for (i = 0; i < bf->bf_dmamap_info.nsegs; i++, ds++) {
251 ds->ds_data = bf->bf_dmamap_info.dma_segs[i].paddr;
253 if (i == (bf->bf_dmamap_info.nsegs - 1)) {
257 ds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, i+1);
260 , bf->bf_dmamap_info.dma_segs[i].len
262 , i == (bf->bf_dmamap_info.nsegs - 1)
267 static void ath_tx_tgt_setds(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
269 struct ath_tx_desc *ds = bf->bf_desc;
270 struct ath_hal *ah = sc->sc_ah;
272 switch (bf->bf_protmode) {
273 case IEEE80211_PROT_RTSCTS:
274 bf->bf_flags |= HAL_TXDESC_RTSENA;
276 case IEEE80211_PROT_CTSONLY:
277 bf->bf_flags |= HAL_TXDESC_CTSENA;
283 ah->ah_set11nTxDesc(ds
289 , bf->bf_flags | HAL_TXDESC_INTREQ);
291 ath_filltxdesc(sc, bf);
294 static struct ath_tx_buf *ath_buf_toggle(struct ath_softc_tgt *sc,
295 struct ath_tx_buf *bf,
298 struct ath_tx_buf *tmp = NULL;
299 adf_nbuf_t buf = NULL;
301 adf_os_assert(sc->sc_txbuf_held != NULL);
303 tmp = sc->sc_txbuf_held;
306 ath_dma_unmap(sc, bf);
307 adf_nbuf_queue_init(&tmp->bf_skbhead);
308 buf = adf_nbuf_queue_remove(&bf->bf_skbhead);
310 adf_nbuf_queue_add(&tmp->bf_skbhead, buf);
312 adf_os_assert(adf_nbuf_queue_len(&bf->bf_skbhead) == 0);
314 tmp->bf_next = bf->bf_next;
315 tmp->bf_endpt = bf->bf_endpt;
316 tmp->bf_tidno = bf->bf_tidno;
317 tmp->bf_skb = bf->bf_skb;
318 tmp->bf_node = bf->bf_node;
319 tmp->bf_isaggr = bf->bf_isaggr;
320 tmp->bf_flags = bf->bf_flags;
321 tmp->bf_state = bf->bf_state;
322 tmp->bf_retries = bf->bf_retries;
323 tmp->bf_comp = bf->bf_comp;
324 tmp->bf_nframes = bf->bf_nframes;
325 tmp->bf_cookie = bf->bf_cookie;
337 ath_dma_map(sc, tmp);
338 ath_tx_tgt_setds(sc, tmp);
341 sc->sc_txbuf_held = bf;
346 static void ath_tgt_skb_free(struct ath_softc_tgt *sc,
347 adf_nbuf_queue_t *head,
348 HTC_ENDPOINT_ID endpt)
352 while (adf_nbuf_queue_len(head) != 0) {
353 tskb = adf_nbuf_queue_remove(head);
354 ath_free_tx_skb(sc->tgt_htc_handle,endpt,tskb);
358 static void ath_buf_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
360 ath_dma_unmap(sc, bf);
361 ath_tgt_skb_free(sc, &bf->bf_skbhead,bf->bf_endpt);
364 bf = ath_buf_toggle(sc, bf, 0);
366 asf_tailq_insert_tail(&sc->sc_txbuf, bf, bf_list);
370 static void ath_buf_set_rate(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
372 struct ath_hal *ah = sc->sc_ah;
373 const HAL_RATE_TABLE *rt;
374 struct ath_tx_desc *ds = bf->bf_desc;
375 HAL_11N_RATE_SERIES series[4];
377 a_uint8_t rix, cix, rtsctsrate;
378 a_int32_t prot_mode = AH_FALSE;
380 rt = sc->sc_currates;
381 rix = bf->bf_rcs[0].rix;
382 flags = (bf->bf_flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA));
383 cix = rt->info[sc->sc_protrix].controlRate;
385 if (bf->bf_protmode != IEEE80211_PROT_NONE &&
386 (rt->info[rix].phy == IEEE80211_T_OFDM ||
387 rt->info[rix].phy == IEEE80211_T_HT) &&
388 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
389 cix = rt->info[sc->sc_protrix].controlRate;
392 if (ath_hal_getcapability(ah, HAL_CAP_HT) && (!bf->bf_ismcast))
393 flags = HAL_TXDESC_RTSENA;
396 if (bf->bf_rcs[i].tries) {
397 cix = rt->info[bf->bf_rcs[i].rix].controlRate;
404 adf_os_mem_set(series, 0, sizeof(HAL_11N_RATE_SERIES) * 4);
406 for (i = 0; i < 4; i++) {
407 if (!bf->bf_rcs[i].tries)
410 rix = bf->bf_rcs[i].rix;
412 series[i].Rate = rt->info[rix].rateCode |
413 (bf->bf_shpream ? rt->info[rix].shortPreamble : 0);
415 series[i].Tries = bf->bf_rcs[i].tries;
417 series[i].RateFlags = ((bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
418 HAL_RATESERIES_RTS_CTS : 0 ) |
419 ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
420 HAL_RATESERIES_2040 : 0 ) |
421 ((bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG) ?
422 HAL_RATESERIES_HALFGI : 0 ) |
423 ((bf->bf_rcs[i].flags & ATH_RC_TX_STBC_FLAG) ?
424 HAL_RATESERIES_STBC: 0);
426 series[i].RateFlags = ((bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
427 HAL_RATESERIES_RTS_CTS : 0 ) |
428 ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
429 HAL_RATESERIES_2040 : 0 ) |
430 ((bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG) ?
431 HAL_RATESERIES_HALFGI : 0 );
433 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
434 (bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) != 0,
435 (bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG));
437 series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
440 series[i].RateFlags |= HAL_RATESERIES_RTS_CTS;
442 if (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG)
443 series[i].RateFlags |= HAL_RATESERIES_RTS_CTS;
446 rtsctsrate = rt->info[cix].rateCode |
447 (bf->bf_shpream ? rt->info[cix].shortPreamble : 0);
449 ah->ah_set11nRateScenario(ds, 1,
455 static void ath_tgt_rate_findrate(struct ath_softc_tgt *sc,
456 struct ath_node_target *an,
457 a_int32_t shortPreamble,
463 struct ath_rc_series series[],
466 ath_rate_findrate(sc, an, 1, frameLen, 10, 4, 1,
467 ATH_RC_PROBE_ALLOWED, series, isProbe);
470 static void owl_tgt_tid_init(struct ath_atx_tid *tid)
474 tid->seq_start = tid->seq_next = 0;
475 tid->baw_size = WME_MAX_BA;
476 tid->baw_head = tid->baw_tail = 0;
479 tid->sched = AH_FALSE;
481 asf_tailq_init(&tid->buf_q);
483 for (i = 0; i < ATH_TID_MAX_BUFS; i++) {
484 TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, i);
488 static void owl_tgt_tid_cleanup(struct ath_softc_tgt *sc,
489 struct ath_atx_tid *tid)
496 tid->flag &= ~TID_CLEANUP_INPROGRES;
498 if (tid->flag & TID_REINITIALIZE) {
499 adf_os_print("TID REINIT DONE for tid %p\n", tid);
500 tid->flag &= ~TID_REINITIALIZE;
501 owl_tgt_tid_init(tid);
503 ath_aggr_resume_tid(sc, tid);
507 void owl_tgt_node_init(struct ath_node_target * an)
509 struct ath_atx_tid *tid;
512 for (tidno = 0, tid = &an->tid[tidno]; tidno < WME_NUM_TID;tidno++, tid++) {
516 if ( tid->flag & TID_CLEANUP_INPROGRES ) {
517 tid->flag |= TID_REINITIALIZE;
518 adf_os_print("tid[%p]->incomp is not 0: %d\n",
521 owl_tgt_tid_init(tid);
526 void ath_tx_status_clear(struct ath_softc_tgt *sc)
530 for (i = 0; i < 2; i++) {
531 sc->tx_status[i].cnt = 0;
535 static WMI_TXSTATUS_EVENT *ath_tx_status_get(struct ath_softc_tgt *sc)
537 WMI_TXSTATUS_EVENT *txs = NULL;
540 for (i = 0; i < 2; i++) {
541 if (sc->tx_status[i].cnt < HTC_MAX_TX_STATUS) {
542 txs = &sc->tx_status[i];
550 void ath_tx_status_update(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
552 struct ath_tx_desc *ds = bf->bf_lastds;
553 WMI_TXSTATUS_EVENT *txs;
555 if (sc->sc_tx_draining)
558 txs = ath_tx_status_get(sc);
562 txs->txstatus[txs->cnt].ts_flags = 0;
564 txs->txstatus[txs->cnt].cookie = bf->bf_cookie;
565 txs->txstatus[txs->cnt].ts_rate = SM(bf->bf_endpt, ATH9K_HTC_TXSTAT_EPID);
567 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
568 txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_FILT;
570 if (!(ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) &&
571 !(ds->ds_txstat.ts_status & HAL_TXERR_FIFO) &&
572 !(ds->ds_txstat.ts_status & HAL_TXERR_TIMER_EXPIRED) &&
573 !(ds->ds_txstat.ts_status & HAL_TXERR_FILT))
574 txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_ACK;
576 ath_tx_status_update_rate(sc, bf->bf_rcs, ds->ds_txstat.ts_rate, txs);
581 void ath_tx_status_update_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
582 struct ath_tx_desc *ds, struct ath_rc_series rcs[],
585 WMI_TXSTATUS_EVENT *txs;
587 if (sc->sc_tx_draining)
590 txs = ath_tx_status_get(sc);
594 txs->txstatus[txs->cnt].cookie = bf->bf_cookie;
595 txs->txstatus[txs->cnt].ts_rate = SM(bf->bf_endpt, ATH9K_HTC_TXSTAT_EPID);
598 txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_ACK;
601 ath_tx_status_update_rate(sc, rcs, ds->ds_txstat.ts_rate, txs);
606 void ath_tx_status_send(struct ath_softc_tgt *sc)
610 if (sc->sc_tx_draining)
613 for (i = 0; i < 2; i++) {
614 if (sc->tx_status[i].cnt) {
615 wmi_event(sc->tgt_wmi_handle, WMI_TXSTATUS_EVENTID,
616 &sc->tx_status[i], sizeof(WMI_TXSTATUS_EVENT));
617 /* FIXME: Handle failures. */
618 sc->tx_status[i].cnt = 0;
623 static void owltgt_tx_process_cabq(struct ath_softc_tgt *sc, struct ath_txq *txq)
625 struct ath_hal *ah = sc->sc_ah;
626 ah->ah_setInterrupts(ah, sc->sc_imask & ~HAL_INT_SWBA);
627 owltgt_tx_processq(sc, txq, OWL_TXQ_ACTIVE);
628 ah->ah_setInterrupts(ah, sc->sc_imask);
631 void owl_tgt_tx_tasklet(TQUEUE_ARG data)
633 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
637 ath_tx_status_clear(sc);
639 for (i = 0; i < (HAL_NUM_TX_QUEUES - 6); i++) {
640 txq = ATH_TXQ(sc, i);
642 if (ATH_TXQ_SETUP(sc, i)) {
643 if (txq == sc->sc_cabq)
644 owltgt_tx_process_cabq(sc, txq);
646 owltgt_tx_processq(sc, txq, OWL_TXQ_ACTIVE);
650 ath_tx_status_send(sc);
653 void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,
654 owl_txq_state_t txqstate)
656 struct ath_tx_buf *bf;
657 struct ath_tx_desc *ds;
658 struct ath_hal *ah = sc->sc_ah;
662 if (asf_tailq_empty(&txq->axq_q)) {
663 txq->axq_link = NULL;
664 txq->axq_linkbuf = NULL;
668 bf = asf_tailq_first(&txq->axq_q);
671 status = ah->ah_procTxDesc(ah, ds);
673 if (status == HAL_EINPROGRESS) {
674 if (txqstate == OWL_TXQ_ACTIVE)
676 else if (txqstate == OWL_TXQ_STOPPED) {
677 __stats(sc, tx_stopfiltered);
678 ds->ds_txstat.ts_flags = 0;
679 ds->ds_txstat.ts_status = HAL_OK;
681 ds->ds_txstat.ts_flags = HAL_TX_SW_FILTERED;
685 ATH_TXQ_REMOVE_HEAD(txq, bf, bf_list);
686 if ((asf_tailq_empty(&txq->axq_q))) {
687 __stats(sc, tx_qnull);
688 txq->axq_link = NULL;
689 txq->axq_linkbuf = NULL;
695 ath_tx_status_update(sc, bf);
696 ath_buf_comp(sc, bf);
699 if (txqstate == OWL_TXQ_ACTIVE) {
700 ath_tgt_txq_schedule(sc, txq);
705 static struct ieee80211_frame* ATH_SKB2_WH(adf_nbuf_t skb)
710 adf_nbuf_peek_header(skb, &anbdata, &anblen);
711 return((struct ieee80211_frame *)anbdata);
715 ath_tgt_tid_drain(struct ath_softc_tgt *sc, struct ath_atx_tid *tid)
717 struct ath_tx_buf *bf;
719 while (!asf_tailq_empty(&tid->buf_q)) {
720 TAILQ_DEQ(&tid->buf_q, bf, bf_list);
721 ath_tx_freebuf(sc, bf);
724 tid->seq_next = tid->seq_start;
725 tid->baw_tail = tid->baw_head;
728 static void ath_tgt_tx_comp_normal(struct ath_softc_tgt *sc,
729 struct ath_tx_buf *bf)
731 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
732 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
734 if (tid->flag & TID_CLEANUP_INPROGRES) {
735 owl_tgt_tid_cleanup(sc, tid);
739 ath_tx_uc_comp(sc, bf);
742 ath_tx_freebuf(sc, bf);
745 static struct ieee80211_node_target * ath_tgt_find_node(struct ath_softc_tgt *sc,
746 a_int32_t node_index)
748 struct ath_node_target *an;
749 struct ieee80211_node_target *ni;
751 if (node_index > TARGET_NODE_MAX)
754 an = &sc->sc_sta[node_index];
758 if (ni->ni_vap == NULL) {
767 static struct ath_tx_buf* ath_tx_buf_alloc(struct ath_softc_tgt *sc)
769 struct ath_tx_buf *bf = NULL;
771 bf = asf_tailq_first(&sc->sc_txbuf);
773 adf_os_mem_set(&bf->bf_state, 0, sizeof(struct ath_buf_state));
774 asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
782 struct ath_tx_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc,
783 adf_nbuf_t skb, ath_data_hdr_t *dh)
785 struct ath_tx_buf *bf;
786 struct ieee80211_node_target *ni;
787 struct ath_atx_tid *tid;
789 ni = ath_tgt_find_node(sc, dh->ni_index);
793 tid = ATH_AN_2_TID(ATH_NODE_TARGET(ni), dh->tidno);
794 if (tid->flag & TID_REINITIALIZE) {
795 adf_os_print("drop frame due to TID reinit\n");
799 bf = ath_tx_buf_alloc(sc);
801 __stats(sc, tx_nobufs);
805 bf->bf_tidno = dh->tidno;
806 bf->bf_txq = TID_TO_ACTXQ(bf->bf_tidno);
807 bf->bf_keytype = dh->keytype;
808 bf->bf_keyix = dh->keyix;
809 bf->bf_protmode = dh->flags & (IEEE80211_PROT_RTSCTS | IEEE80211_PROT_CTSONLY);
812 adf_nbuf_queue_add(&bf->bf_skbhead, skb);
813 skb = adf_nbuf_queue_first(&(bf->bf_skbhead));
815 if (adf_nbuf_queue_len(&(bf->bf_skbhead)) == 0) {
816 __stats(sc, tx_noskbs);
824 ath_tgt_txbuf_setup(sc, bf, dh);
826 ath_tx_tgt_setds(sc, bf);
831 static void ath_tgt_tx_seqno_normal(struct ath_tx_buf *bf)
833 struct ieee80211_node_target *ni = bf->bf_node;
834 struct ath_node_target *an = ATH_NODE_TARGET(ni);
835 struct ieee80211_frame *wh = ATH_SKB_2_WH(bf->bf_skb);
836 struct ath_atx_tid *tid = ATH_AN_2_TID(an, bf->bf_tidno);
838 u_int8_t fragno = (wh->i_seq[0] & 0xf);
840 INCR(ni->ni_txseqmgmt, IEEE80211_SEQ_MAX);
842 bf->bf_seqno = (tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
844 *(u_int16_t *)wh->i_seq = adf_os_cpu_to_le16(bf->bf_seqno);
845 wh->i_seq[0] |= fragno;
847 if (!(wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG))
848 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
851 static a_int32_t ath_key_setup(struct ieee80211_node_target *ni,
852 struct ath_tx_buf *bf)
854 struct ieee80211_frame *wh = ATH_SKB_2_WH(bf->bf_skb);
856 if (!(wh->i_fc[1] & IEEE80211_FC1_WEP)) {
857 bf->bf_keytype = HAL_KEY_TYPE_CLEAR;
858 bf->bf_keyix = HAL_TXKEYIX_INVALID;
862 switch (bf->bf_keytype) {
863 case HAL_KEY_TYPE_WEP:
864 bf->bf_pktlen += IEEE80211_WEP_ICVLEN;
866 case HAL_KEY_TYPE_AES:
867 bf->bf_pktlen += IEEE80211_WEP_MICLEN;
869 case HAL_KEY_TYPE_TKIP:
870 bf->bf_pktlen += IEEE80211_WEP_ICVLEN;
876 if (bf->bf_keytype == HAL_KEY_TYPE_AES ||
877 bf->bf_keytype == HAL_KEY_TYPE_TKIP)
878 ieee80211_tgt_crypto_encap(wh, ni, bf->bf_keytype);
883 static void ath_tgt_txq_add_ucast(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
885 struct ath_hal *ah = sc->sc_ah;
888 volatile a_int32_t txe_val;
894 status = ah->ah_procTxDesc(ah, bf->bf_lastds);
896 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
898 if (txq->axq_link == NULL) {
899 ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
901 *txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
903 txe_val = ioread32_mac(0x0840);
904 if (!(txe_val & (1<< txq->axq_qnum)))
905 ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
908 txq->axq_link = &bf->bf_lastds->ds_link;
909 ah->ah_startTxDma(ah, txq->axq_qnum);
912 static a_int32_t ath_tgt_txbuf_setup(struct ath_softc_tgt *sc,
913 struct ath_tx_buf *bf,
917 struct ieee80211_frame *wh = ATH_SKB2_WH(bf->bf_skb);
919 a_uint32_t flags = adf_os_ntohl(dh->flags);
921 ath_tgt_tx_seqno_normal(bf);
923 bf->bf_txq_add = ath_tgt_txq_add_ucast;
924 bf->bf_hdrlen = ieee80211_anyhdrsize(wh);
925 bf->bf_pktlen = ath_get_pktlen(bf, bf->bf_hdrlen);
926 bf->bf_ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
928 if ((retval = ath_key_setup(bf->bf_node, bf)) < 0)
931 if (flags & ATH_SHORT_PREAMBLE)
932 bf->bf_shpream = AH_TRUE;
934 bf->bf_shpream = AH_FALSE;
936 bf->bf_flags = HAL_TXDESC_CLRDMASK;
937 bf->bf_atype = HAL_PKT_TYPE_NORMAL;
943 ath_get_pktlen(struct ath_tx_buf *bf, a_int32_t hdrlen)
945 adf_nbuf_t skb = bf->bf_skb;
948 skb = adf_nbuf_queue_first(&bf->bf_skbhead);
949 pktlen = adf_nbuf_len(skb);
951 pktlen -= (hdrlen & 3);
952 pktlen += IEEE80211_CRC_LEN;
958 ath_tgt_tx_send_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
960 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
961 struct ath_rc_series rcs[4];
962 struct ath_rc_series mrcs[4];
963 a_int32_t shortPreamble = 0;
964 a_int32_t isProbe = 0;
966 adf_os_mem_set(rcs, 0, sizeof(struct ath_rc_series)*4 );
967 adf_os_mem_set(mrcs, 0, sizeof(struct ath_rc_series)*4 );
969 if (!bf->bf_ismcast) {
970 ath_tgt_rate_findrate(sc, an, shortPreamble,
973 ath_hal_memcpy(bf->bf_rcs, rcs, sizeof(rcs));
975 mrcs[1].tries = mrcs[2].tries = mrcs[3].tries = 0;
976 mrcs[1].rix = mrcs[2].rix = mrcs[3].rix = 0;
980 ath_hal_memcpy(bf->bf_rcs, mrcs, sizeof(mrcs));
983 ath_buf_set_rate(sc, bf);
984 bf->bf_txq_add(sc, bf);
988 ath_tx_freebuf(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
991 struct ath_tx_desc *bfd = NULL;
992 struct ath_hal *ah = sc->sc_ah;
994 for (bfd = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; bfd++, i++) {
995 ah->ah_clr11nAggr(bfd);
996 ah->ah_set11nBurstDuration(bfd, 0);
997 ah->ah_set11nVirtualMoreFrag(bfd, 0);
1000 ath_dma_unmap(sc, bf);
1002 ath_tgt_skb_free(sc, &bf->bf_skbhead,bf->bf_endpt);
1008 bf = ath_buf_toggle(sc, bf, 0);
1010 bf->bf_isretried = 0;
1013 asf_tailq_insert_tail(&sc->sc_txbuf, bf, bf_list);
1017 ath_tx_uc_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1019 ath_tx_status_update(sc, bf);
1020 ath_update_stats(sc, bf);
1021 ath_rate_tx_complete(sc, ATH_NODE_TARGET(bf->bf_node),
1022 bf->bf_lastds, bf->bf_rcs, 1, 0);
1026 ath_update_stats(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1028 struct ath_tx_desc *ds = bf->bf_desc;
1029 struct ieee80211_frame *wh = ATH_SKB2_WH(bf->bf_skb);
1032 if (ds->ds_txstat.ts_status == 0) {
1033 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE)
1034 sc->sc_tx_stats.ast_tx_altrate++;
1036 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY &&
1037 !IEEE80211_IS_MULTICAST(wh->i_addr1))
1038 sc->sc_tx_stats.ast_tx_xretries++;
1039 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO)
1040 sc->sc_tx_stats.ast_tx_fifoerr++;
1041 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
1042 sc->sc_tx_stats.ast_tx_filtered++;
1043 if (ds->ds_txstat.ts_status & HAL_TXERR_TIMER_EXPIRED)
1044 sc->sc_tx_stats.ast_tx_timer_exp++;
1046 sr = ds->ds_txstat.ts_shortretry;
1047 lr = ds->ds_txstat.ts_longretry;
1048 sc->sc_tx_stats.ast_tx_shortretry += sr;
1049 sc->sc_tx_stats.ast_tx_longretry += lr;
1053 ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t hdr_buf, adf_nbuf_t skb,
1054 HTC_ENDPOINT_ID endpt)
1056 struct ieee80211_node_target *ni;
1057 struct ieee80211vap_target *vap;
1058 struct ath_vap_target *avp;
1059 struct ath_hal *ah = sc->sc_ah;
1060 a_uint8_t rix, txrate, ctsrate, cix = 0xff, *data;
1061 a_uint32_t subtype, flags, ctsduration;
1062 a_int32_t i, iswep, ismcast, hdrlen, pktlen, try0, len;
1063 struct ath_tx_desc *ds=NULL;
1064 struct ath_txq *txq=NULL;
1065 struct ath_tx_buf *bf;
1067 const HAL_RATE_TABLE *rt;
1068 HAL_BOOL shortPreamble;
1069 struct ieee80211_frame *wh;
1070 struct ath_rc_series rcs[4];
1071 HAL_11N_RATE_SERIES series[4];
1076 adf_nbuf_peek_header(skb, &data, &len);
1077 adf_nbuf_pull_head(skb, sizeof(ath_mgt_hdr_t));
1079 adf_nbuf_peek_header(hdr_buf, &data, &len);
1082 adf_os_assert(len >= sizeof(ath_mgt_hdr_t));
1084 mh = (ath_mgt_hdr_t *)data;
1085 adf_nbuf_peek_header(skb, &data, &len);
1086 wh = (struct ieee80211_frame *)data;
1088 adf_os_mem_set(rcs, 0, sizeof(struct ath_rc_series)*4);
1089 adf_os_mem_set(series, 0, sizeof(HAL_11N_RATE_SERIES)*4);
1091 bf = asf_tailq_first(&sc->sc_txbuf);
1095 asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
1097 ni = ath_tgt_find_node(sc, mh->ni_index);
1101 bf->bf_endpt = endpt;
1102 bf->bf_cookie = mh->cookie;
1103 bf->bf_protmode = mh->flags & (IEEE80211_PROT_RTSCTS | IEEE80211_PROT_CTSONLY);
1104 txq = &sc->sc_txq[1];
1105 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
1106 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
1107 hdrlen = ieee80211_anyhdrsize(wh);
1109 keyix = HAL_TXKEYIX_INVALID;
1110 pktlen -= (hdrlen & 3);
1111 pktlen += IEEE80211_CRC_LEN;
1116 adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, skb, ADF_OS_DMA_TO_DEVICE);
1119 adf_nbuf_queue_add(&bf->bf_skbhead, skb);
1122 rt = sc->sc_currates;
1123 adf_os_assert(rt != NULL);
1125 if (mh->flags == ATH_SHORT_PREAMBLE)
1126 shortPreamble = AH_TRUE;
1128 shortPreamble = AH_FALSE;
1130 flags = HAL_TXDESC_CLRDMASK;
1132 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
1133 case IEEE80211_FC0_TYPE_MGT:
1134 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
1136 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
1137 atype = HAL_PKT_TYPE_PROBE_RESP;
1138 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM)
1139 atype = HAL_PKT_TYPE_ATIM;
1141 atype = HAL_PKT_TYPE_NORMAL;
1145 atype = HAL_PKT_TYPE_NORMAL;
1149 avp = &sc->sc_vap[mh->vap_index];
1151 rcs[0].rix = ath_get_minrateidx(sc, avp);
1152 rcs[0].tries = ATH_TXMAXTRY;
1155 adf_os_mem_copy(bf->bf_rcs, rcs, sizeof(rcs));
1157 try0 = rcs[0].tries;
1158 txrate = rt->info[rix].rateCode;
1161 txrate |= rt->info[rix].shortPreamble;
1168 flags |= HAL_TXDESC_NOACK;
1170 } else if (pktlen > vap->iv_rtsthreshold) {
1171 flags |= HAL_TXDESC_RTSENA;
1172 cix = rt->info[rix].controlRate;
1175 if ((bf->bf_protmode != IEEE80211_PROT_NONE) &&
1176 rt->info[rix].phy == IEEE80211_T_OFDM &&
1177 (flags & HAL_TXDESC_NOACK) == 0) {
1178 cix = rt->info[sc->sc_protrix].controlRate;
1179 sc->sc_tx_stats.ast_tx_protect++;
1182 *(a_uint16_t *)&wh->i_seq[0] = adf_os_cpu_to_le16(ni->ni_txseqmgmt <<
1183 IEEE80211_SEQ_SEQ_SHIFT);
1184 INCR(ni->ni_txseqmgmt, IEEE80211_SEQ_MAX);
1187 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) {
1188 adf_os_assert(cix != 0xff);
1189 ctsrate = rt->info[cix].rateCode;
1190 if (shortPreamble) {
1191 ctsrate |= rt->info[cix].shortPreamble;
1192 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
1193 ctsduration += rt->info[cix].spAckDuration;
1194 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
1195 ctsduration += rt->info[cix].spAckDuration;
1197 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
1198 ctsduration += rt->info[cix].lpAckDuration;
1199 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
1200 ctsduration += rt->info[cix].lpAckDuration;
1202 ctsduration += ath_hal_computetxtime(ah,
1203 rt, pktlen, rix, shortPreamble);
1208 flags |= HAL_TXDESC_INTREQ;
1210 ah->ah_setupTxDesc(ds
1221 bf->bf_flags = flags;
1224 * Set key type in tx desc while sending the encrypted challenge to AP
1225 * in Auth frame 3 of Shared Authentication, owl needs this.
1227 if (iswep && (keyix != HAL_TXKEYIX_INVALID) &&
1228 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == IEEE80211_FC0_SUBTYPE_AUTH)
1229 ah->ah_fillKeyTxDesc(ds, mh->keytype);
1231 ath_filltxdesc(sc, bf);
1233 for (i=0; i<4; i++) {
1234 series[i].Tries = 2;
1235 series[i].Rate = txrate;
1236 series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
1237 series[i].RateFlags = 0;
1239 ah->ah_set11nRateScenario(ds, 0, ctsrate, series, 4, 0);
1240 ath_tgt_txqaddbuf(sc, txq, bf, bf->bf_lastds);
1244 HTC_ReturnBuffers(sc->tgt_htc_handle, endpt, skb);
1249 ath_tgt_txqaddbuf(struct ath_softc_tgt *sc,
1250 struct ath_txq *txq, struct ath_tx_buf *bf,
1251 struct ath_tx_desc *lastds)
1253 struct ath_hal *ah = sc->sc_ah;
1255 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
1257 if (txq->axq_link == NULL) {
1258 ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
1260 *txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
1263 txq->axq_link = &lastds->ds_link;
1264 ah->ah_startTxDma(ah, txq->axq_qnum);
1267 void ath_tgt_handle_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1270 struct ath_node_target *an;
1272 an = (struct ath_node_target *)bf->bf_node;
1275 tid = &an->tid[bf->bf_tidno];
1278 bf->bf_comp = ath_tgt_tx_comp_normal;
1279 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1280 ath_tgt_tx_send_normal(sc, bf);
1284 ath_tgt_tx_enqueue(struct ath_txq *txq, struct ath_atx_tid *tid)
1292 tid->sched = AH_TRUE;
1293 asf_tailq_insert_tail(&txq->axq_tidq, tid, tid_qelem);
1297 ath_tgt_txq_schedule(struct ath_softc_tgt *sc, struct ath_txq *txq)
1299 struct ath_atx_tid *tid;
1305 TAILQ_DEQ(&txq->axq_tidq, tid, tid_qelem);
1310 tid->sched = AH_FALSE;
1315 if (!(tid->flag & TID_AGGR_ENABLED))
1316 ath_tgt_tx_sched_normal(sc,tid);
1318 ath_tgt_tx_sched_aggr(sc,tid);
1322 if (!asf_tailq_empty(&tid->buf_q)) {
1323 ath_tgt_tx_enqueue(txq, tid);
1326 } while (!asf_tailq_empty(&txq->axq_tidq) && !bdone);
1330 ath_tgt_handle_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1333 struct ath_node_target *an;
1334 struct ath_txq *txq = bf->bf_txq;
1335 a_bool_t queue_frame, within_baw;
1337 an = (struct ath_node_target *)bf->bf_node;
1340 tid = &an->tid[bf->bf_tidno];
1343 bf->bf_comp = ath_tgt_tx_comp_aggr;
1345 within_baw = BAW_WITHIN(tid->seq_start, tid->baw_size,
1346 SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1348 queue_frame = ( (txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) ||
1349 (!asf_tailq_empty(&tid->buf_q)) ||
1350 (tid->paused) || (!within_baw) );
1353 asf_tailq_insert_tail(&tid->buf_q, bf, bf_list);
1354 ath_tgt_tx_enqueue(txq, tid);
1356 ath_tx_addto_baw(tid, bf);
1357 __stats(sc, txaggr_nframes);
1358 ath_tgt_tx_send_normal(sc, bf);
1363 ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
1365 struct ath_tx_buf *bf;
1366 struct ath_txq *txq =TID_TO_ACTXQ(tid->tidno);;
1369 if (asf_tailq_empty(&tid->buf_q))
1372 bf = asf_tailq_first(&tid->buf_q);
1373 asf_tailq_remove(&tid->buf_q, bf, bf_list);
1374 ath_tgt_tx_send_normal(sc, bf);
1376 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH);
1380 ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
1382 struct ath_tx_buf *bf, *bf_last;
1383 ATH_AGGR_STATUS status;
1384 ath_tx_bufhead bf_q;
1385 struct ath_txq *txq = TID_TO_ACTXQ(tid->tidno);
1386 struct ath_tx_desc *ds = NULL;
1387 struct ath_hal *ah = sc->sc_ah;
1391 if (asf_tailq_empty(&tid->buf_q))
1395 if (asf_tailq_empty(&tid->buf_q))
1398 asf_tailq_init(&bf_q);
1400 status = ath_tgt_tx_form_aggr(sc, tid, &bf_q);
1402 if (asf_tailq_empty(&bf_q))
1405 bf = asf_tailq_first(&bf_q);
1406 bf_last = asf_tailq_last(&bf_q, ath_tx_bufhead_s);
1408 if (bf->bf_nframes == 1) {
1410 if(bf->bf_retries == 0)
1411 __stats(sc, txaggr_single);
1413 bf->bf_lastds = &(bf->bf_descarr[bf->bf_dmamap_info.nsegs -1]);
1414 bf->bf_lastds->ds_link = 0;
1417 for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
1418 ah->ah_clr11nAggr(ds);
1420 ath_buf_set_rate(sc, bf);
1421 bf->bf_txq_add(sc, bf);
1426 bf_last->bf_next = NULL;
1427 bf_last->bf_lastds->ds_link = 0;
1428 bf_last->bf_ndelim = 0;
1431 ath_buf_set_rate(sc, bf);
1432 ah->ah_set11nAggrFirst(bf->bf_desc, bf->bf_al,
1434 bf->bf_lastds = bf_last->bf_lastds;
1436 for (i = 0; i < bf_last->bf_dmamap_info.nsegs; i++)
1437 ah->ah_set11nAggrLast(&bf_last->bf_descarr[i]);
1439 if (status == ATH_AGGR_8K_LIMITED) {
1444 bf->bf_txq_add(sc, bf);
1445 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
1446 status != ATH_TGT_AGGR_BAW_CLOSED);
1449 static u_int32_t ath_lookup_rate(struct ath_softc_tgt *sc,
1450 struct ath_node_target *an,
1451 struct ath_tx_buf *bf)
1454 u_int32_t max4msframelen, frame_length;
1455 u_int16_t aggr_limit, legacy=0;
1456 const HAL_RATE_TABLE *rt = sc->sc_currates;
1457 struct ieee80211_node_target *ieee_node = (struct ieee80211_node_target *)an;
1459 if (bf->bf_ismcast) {
1460 bf->bf_rcs[1].tries = bf->bf_rcs[2].tries = bf->bf_rcs[3].tries = 0;
1461 bf->bf_rcs[0].rix = 0xb;
1462 bf->bf_rcs[0].tries = ATH_TXMAXTRY - 1;
1463 bf->bf_rcs[0].flags = 0;
1465 ath_tgt_rate_findrate(sc, an, AH_TRUE, 0, ATH_TXMAXTRY-1, 4, 1,
1466 ATH_RC_PROBE_ALLOWED, bf->bf_rcs, &prate);
1469 max4msframelen = IEEE80211_AMPDU_LIMIT_MAX;
1471 for (i = 0; i < 4; i++) {
1472 if (bf->bf_rcs[i].tries) {
1473 frame_length = bf->bf_rcs[i].max4msframelen;
1475 if (rt->info[bf->bf_rcs[i].rix].phy != IEEE80211_T_HT) {
1480 max4msframelen = ATH_MIN(max4msframelen, frame_length);
1484 if (prate || legacy)
1487 if (sc->sc_ic.ic_enable_coex)
1488 aggr_limit = ATH_MIN((max4msframelen*3)/8, sc->sc_ic.ic_ampdu_limit);
1490 aggr_limit = ATH_MIN(max4msframelen, sc->sc_ic.ic_ampdu_limit);
1492 if (ieee_node->ni_maxampdu)
1493 aggr_limit = ATH_MIN(aggr_limit, ieee_node->ni_maxampdu);
1498 int ath_tgt_tx_form_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid,
1499 ath_tx_bufhead *bf_q)
1501 struct ath_tx_buf *bf_first ,*bf_prev = NULL;
1502 int nframes = 0, rl = 0;;
1503 struct ath_tx_desc *ds = NULL;
1504 struct ath_tx_buf *bf;
1505 struct ath_hal *ah = sc->sc_ah;
1506 u_int16_t aggr_limit = (64*1024 -1), al = 0, bpad = 0, al_delta;
1507 u_int16_t h_baw = tid->baw_size/2, prev_al = 0, prev_frames = 0;
1509 bf_first = asf_tailq_first(&tid->buf_q);
1512 bf = asf_tailq_first(&tid->buf_q);
1515 if (!BAW_WITHIN(tid->seq_start, tid->baw_size,
1516 SEQNO_FROM_BF_SEQNO(bf->bf_seqno))) {
1518 bf_first->bf_al= al;
1519 bf_first->bf_nframes = nframes;
1520 return ATH_TGT_AGGR_BAW_CLOSED;
1524 aggr_limit = ath_lookup_rate(sc, tid->an, bf);
1528 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_pktlen;
1530 if (nframes && (aggr_limit < (al + bpad + al_delta + prev_al))) {
1531 bf_first->bf_al= al;
1532 bf_first->bf_nframes = nframes;
1533 return ATH_TGT_AGGR_LIMITED;
1537 if ((nframes + prev_frames) >= ATH_MIN((h_baw), 17)) {
1539 if ((nframes + prev_frames) >= ATH_MIN((h_baw), 22)) {
1541 bf_first->bf_al= al;
1542 bf_first->bf_nframes = nframes;
1543 return ATH_TGT_AGGR_LIMITED;
1546 ath_tx_addto_baw(tid, bf);
1547 asf_tailq_remove(&tid->buf_q, bf, bf_list);
1548 asf_tailq_insert_tail(bf_q, bf, bf_list);
1553 adf_os_assert(bf->bf_comp == ath_tgt_tx_comp_aggr);
1555 al += bpad + al_delta;
1556 bf->bf_ndelim = ATH_AGGR_GET_NDELIM(bf->bf_pktlen);
1558 switch (bf->bf_keytype) {
1559 case HAL_KEY_TYPE_AES:
1560 bf->bf_ndelim += ATH_AGGR_ENCRYPTDELIM;
1562 case HAL_KEY_TYPE_WEP:
1563 case HAL_KEY_TYPE_TKIP:
1564 bf->bf_ndelim += 64;
1566 case HAL_KEY_TYPE_WAPI:
1567 bf->bf_ndelim += 12;
1573 bpad = PADBYTES(al_delta) + (bf->bf_ndelim << 2);
1576 bf_prev->bf_next = bf;
1577 bf_prev->bf_lastds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
1581 for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
1582 ah->ah_set11nAggrMiddle(ds, bf->bf_ndelim);
1584 } while (!asf_tailq_empty(&tid->buf_q));
1586 bf_first->bf_al= al;
1587 bf_first->bf_nframes = nframes;
1589 return ATH_TGT_AGGR_DONE;
1592 void ath_tx_addto_baw(ath_atx_tid_t *tid, struct ath_tx_buf *bf)
1596 if (bf->bf_isretried) {
1600 index = ATH_BA_INDEX(tid->seq_start, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1601 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1603 TX_BUF_BITMAP_SET(tid->tx_buf_bitmap, cindex);
1605 if (index >= ((tid->baw_tail - tid->baw_head) & (ATH_TID_MAX_BUFS - 1))) {
1606 tid->baw_tail = cindex;
1607 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
1611 void ath_tgt_tx_comp_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1613 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1614 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1615 struct ath_tx_desc lastds;
1616 struct ath_tx_desc *ds = &lastds;
1617 struct ath_rc_series rcs[4];
1622 int nframes = bf->bf_nframes;
1623 struct ath_tx_buf *bf_next;
1624 ath_tx_bufhead bf_q;
1626 struct ath_tx_buf *bar = NULL;
1627 struct ath_txq *txq;
1631 if (tid->flag & TID_CLEANUP_INPROGRES) {
1632 ath_tx_comp_cleanup(sc, bf);
1636 adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
1637 adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
1639 if (ds->ds_txstat.ts_flags == HAL_TX_SW_FILTERED) {
1644 if (!bf->bf_isaggr) {
1645 ath_tx_comp_unaggr(sc, bf);
1649 __stats(sc, tx_compaggr);
1651 asf_tailq_init(&bf_q);
1653 seq_st = ATH_DS_BA_SEQ(ds);
1654 ba = ATH_DS_BA_BITMAP(ds);
1655 tx_ok = (ATH_DS_TX_STATUS(ds) == HAL_OK);
1657 if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
1658 ath_tx_comp_aggr_error(sc, bf, tid);
1662 if (tx_ok && !ATH_DS_TX_BA(ds)) {
1663 __stats(sc, txaggr_babug);
1664 adf_os_print("BA Bug?\n");
1665 ath_tx_comp_aggr_error(sc, bf, tid);
1670 ba_index = ATH_BA_INDEX(seq_st, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1671 bf_next = bf->bf_next;
1673 if (tx_ok && ATH_BA_ISSET(ba, ba_index)) {
1674 __stats(sc, txaggr_compgood);
1675 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1676 ath_tx_status_update_aggr(sc, bf, ds, rcs, 1);
1677 ath_tx_freebuf(sc, bf);
1679 ath_tx_retry_subframe(sc, bf, &bf_q, &bar);
1685 ath_update_aggr_stats(sc, ds, nframes, nbad);
1686 ath_rate_tx_complete(sc, an, ds, rcs, nframes, nbad);
1689 ath_bar_tx(sc, tid, bar);
1692 if (!asf_tailq_empty(&bf_q)) {
1693 __stats(sc, txaggr_prepends);
1694 TAILQ_INSERTQ_HEAD(&tid->buf_q, &bf_q, bf_list);
1695 ath_tgt_tx_enqueue(txq, tid);
1700 ath_tx_comp_aggr_error(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
1705 struct ath_tx_desc lastds;
1706 struct ath_tx_desc *ds = &lastds;
1707 struct ath_rc_series rcs[4];
1708 struct ath_tx_buf *bar = NULL;
1709 struct ath_tx_buf *bf_next;
1710 int nframes = bf->bf_nframes;
1711 ath_tx_bufhead bf_q;
1712 struct ath_txq *txq;
1714 asf_tailq_init(&bf_q);
1717 adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
1718 adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
1721 bf_next = bf->bf_next;
1722 ath_tx_retry_subframe(sc, bf, &bf_q, &bar);
1726 ath_update_aggr_stats(sc, ds, nframes, nframes);
1727 ath_rate_tx_complete(sc, tid->an, ds, rcs, nframes, nframes);
1730 ath_bar_tx(sc, tid, bar);
1733 if (!asf_tailq_empty(&bf_q)) {
1734 __stats(sc, txaggr_prepends);
1735 TAILQ_INSERTQ_HEAD(&tid->buf_q, &bf_q, bf_list);
1736 ath_tgt_tx_enqueue(txq, tid);
1741 ath_tx_comp_cleanup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1744 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1745 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1746 struct ath_tx_desc lastds;
1747 struct ath_tx_desc *ds = &lastds;
1748 struct ath_rc_series rcs[4];
1753 int nframes = bf->bf_nframes;
1754 struct ath_tx_buf *bf_next;
1757 adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
1758 adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
1760 seq_st = ATH_DS_BA_SEQ(ds);
1761 ba = ATH_DS_BA_BITMAP(ds);
1762 tx_ok = (ATH_DS_TX_STATUS(ds) == HAL_OK);
1764 if (!bf->bf_isaggr) {
1765 ath_update_stats(sc, bf);
1767 __stats(sc, tx_compunaggr);
1769 ath_tx_status_update(sc, bf);
1771 ath_tx_freebuf(sc, bf);
1773 if (tid->flag & TID_CLEANUP_INPROGRES) {
1774 owl_tgt_tid_cleanup(sc, tid);
1782 ba_index = ATH_BA_INDEX(seq_st, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1783 bf_next = bf->bf_next;
1785 ath_tx_status_update_aggr(sc, bf, ds, rcs, 0);
1787 ath_tx_freebuf(sc, bf);
1791 tid->flag &= ~TID_CLEANUP_INPROGRES;
1792 ath_aggr_resume_tid(sc, tid);
1799 ath_update_aggr_stats(sc, ds, nframes, nbad);
1800 ath_rate_tx_complete(sc, an, ds, rcs, nframes, nbad);
1804 ath_tx_retry_subframe(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
1805 ath_tx_bufhead *bf_q, struct ath_tx_buf **bar)
1808 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1809 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1810 struct ath_tx_desc *ds = NULL;
1811 struct ath_hal *ah = sc->sc_ah;
1814 __stats(sc, txaggr_compretries);
1816 for(ds = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; ds++, i++) {
1817 ah->ah_clr11nAggr(ds);
1818 ah->ah_set11nBurstDuration(ds, 0);
1819 ah->ah_set11nVirtualMoreFrag(ds, 0);
1822 if (bf->bf_retries >= OWLMAX_RETRIES) {
1823 __stats(sc, txaggr_xretries);
1824 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1825 ath_tx_status_update_aggr(sc, bf, bf->bf_lastds, NULL, 0);
1830 ath_tx_freebuf(sc, bf);
1835 __stats(sc, txaggr_errlast);
1836 bf = ath_buf_toggle(sc, bf, 1);
1838 bf->bf_lastds = &(bf->bf_descarr[bf->bf_dmamap_info.nsegs - 1]);
1840 ath_tx_set_retry(sc, bf);
1841 asf_tailq_insert_tail(bf_q, bf, bf_list);
1845 ath_update_aggr_stats(struct ath_softc_tgt *sc,
1846 struct ath_tx_desc *ds, int nframes,
1850 u_int8_t status = ATH_DS_TX_STATUS(ds);
1851 u_int8_t txflags = ATH_DS_TX_FLAGS(ds);
1853 __statsn(sc, txaggr_longretries, ds->ds_txstat.ts_longretry);
1854 __statsn(sc, txaggr_shortretries, ds->ds_txstat.ts_shortretry);
1856 if (txflags & HAL_TX_DESC_CFG_ERR)
1857 __stats(sc, txaggr_desc_cfgerr);
1859 if (txflags & HAL_TX_DATA_UNDERRUN)
1860 __stats(sc, txaggr_data_urun);
1862 if (txflags & HAL_TX_DELIM_UNDERRUN)
1863 __stats(sc, txaggr_delim_urun);
1869 if (status & HAL_TXERR_XRETRY)
1870 __stats(sc, txaggr_compxretry);
1872 if (status & HAL_TXERR_FILT)
1873 __stats(sc, txaggr_filtered);
1875 if (status & HAL_TXERR_FIFO)
1876 __stats(sc, txaggr_fifo);
1878 if (status & HAL_TXERR_XTXOP)
1879 __stats(sc, txaggr_xtxop);
1881 if (status & HAL_TXERR_TIMER_EXPIRED)
1882 __stats(sc, txaggr_timer_exp);
1886 ath_tx_comp_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1888 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1889 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1890 struct ath_tx_desc *ds = bf->bf_lastds;
1892 ath_update_stats(sc, bf);
1893 ath_rate_tx_complete(sc, an, ds, bf->bf_rcs, 1, 0);
1895 if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
1896 ath_tx_retry_unaggr(sc, bf);
1899 __stats(sc, tx_compunaggr);
1901 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1902 ath_tx_status_update(sc, bf);
1903 ath_tx_freebuf(sc, bf);
1907 ath_tx_retry_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1909 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1910 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1911 struct ath_txq *txq;
1915 if (bf->bf_retries >= OWLMAX_RETRIES) {
1916 __stats(sc, txunaggr_xretry);
1917 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1918 ath_tx_status_update(sc, bf);
1919 ath_bar_tx(sc, tid, bf);
1923 __stats(sc, txunaggr_compretries);
1924 if (!bf->bf_lastds->ds_link) {
1925 __stats(sc, txunaggr_errlast);
1926 bf = ath_buf_toggle(sc, bf, 1);
1929 ath_tx_set_retry(sc, bf);
1930 asf_tailq_insert_head(&tid->buf_q, bf, bf_list);
1931 ath_tgt_tx_enqueue(txq, tid);
1935 ath_tx_update_baw(ath_atx_tid_t *tid, int seqno)
1940 index = ATH_BA_INDEX(tid->seq_start, seqno);
1941 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1943 TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, cindex);
1945 while (tid->baw_head != tid->baw_tail &&
1946 (!TX_BUF_BITMAP_IS_SET(tid->tx_buf_bitmap, tid->baw_head))) {
1947 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1948 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
1952 static void ath_tx_set_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1954 struct ieee80211_frame *wh;
1956 __stats(sc, txaggr_retries);
1958 bf->bf_isretried = 1;
1960 wh = ATH_SKB_2_WH(bf->bf_skb);
1961 wh->i_fc[1] |= IEEE80211_FC1_RETRY;
1964 void ath_tgt_tx_cleanup(struct ath_softc_tgt *sc, struct ath_node_target *an,
1965 ath_atx_tid_t *tid, a_uint8_t discard_all)
1967 struct ath_tx_buf *bf;
1968 struct ath_tx_buf *bf_next;
1969 struct ath_txq *txq;
1971 txq = TID_TO_ACTXQ(tid->tidno);
1973 bf = asf_tailq_first(&tid->buf_q);
1976 if (discard_all || bf->bf_isretried) {
1977 bf_next = asf_tailq_next(bf, bf_list);
1978 TAILQ_DEQ(&tid->buf_q, bf, bf_list);
1979 if (bf->bf_isretried)
1980 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1981 ath_tx_freebuf(sc, bf);
1985 bf->bf_comp = ath_tgt_tx_comp_normal;
1986 bf = asf_tailq_next(bf, bf_list);
1989 ath_aggr_pause_tid(sc, tid);
1991 while (tid->baw_head != tid->baw_tail) {
1992 if (TX_BUF_BITMAP_IS_SET(tid->tx_buf_bitmap, tid->baw_head)) {
1994 tid->flag |= TID_CLEANUP_INPROGRES;
1995 TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, tid->baw_head);
1997 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
1998 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
2001 if (!(tid->flag & TID_CLEANUP_INPROGRES)) {
2002 ath_aggr_resume_tid(sc, tid);
2006 /******************/
2007 /* BAR Management */
2008 /******************/
2010 static void ath_tgt_delba_send(struct ath_softc_tgt *sc,
2011 struct ieee80211_node_target *ni,
2012 a_uint8_t tidno, a_uint8_t initiator,
2013 a_uint16_t reasoncode)
2015 struct ath_node_target *an = ATH_NODE_TARGET(ni);
2016 ath_atx_tid_t *tid = ATH_AN_2_TID(an, tidno);
2017 struct wmi_data_delba wmi_delba;
2019 tid->flag &= ~TID_AGGR_ENABLED;
2021 ath_tgt_tx_cleanup(sc, an, tid, 1);
2023 wmi_delba.ni_nodeindex = ni->ni_nodeindex;
2024 wmi_delba.tidno = tid->tidno;
2025 wmi_delba.initiator = 1;
2026 wmi_delba.reasoncode = IEEE80211_REASON_UNSPECIFIED;
2028 __stats(sc, txbar_xretry);
2029 wmi_event(sc->tgt_wmi_handle,
2035 static void ath_bar_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
2037 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
2038 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
2040 if (bf->bf_retries >= OWLMAX_BAR_RETRIES) {
2041 ath_tgt_delba_send(sc, bf->bf_node, tid->tidno, 1,
2042 IEEE80211_REASON_UNSPECIFIED);
2043 ath_tgt_tid_drain(sc, tid);
2046 ath_buf_comp(sc, bf);
2050 __stats(sc, txbar_compretries);
2052 if (!bf->bf_lastds->ds_link) {
2053 __stats(sc, txbar_errlast);
2054 bf = ath_buf_toggle(sc, bf, 1);
2057 bf->bf_lastds->ds_link = 0;
2059 ath_tx_set_retry(sc, bf);
2060 ath_tgt_txq_add_ucast(sc, bf);
2063 static void ath_bar_tx_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
2065 struct ath_tx_desc *ds = bf->bf_lastds;
2066 struct ath_node_target *an;
2068 struct ath_txq *txq;
2070 an = (struct ath_node_target *)bf->bf_node;
2071 tid = &an->tid[bf->bf_tidno];
2072 txq = TID_TO_ACTXQ(tid->tidno);
2074 if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
2075 ath_bar_retry(sc, bf);
2079 ath_aggr_resume_tid(sc, tid);
2082 ath_buf_comp(sc, bf);
2085 static void ath_bar_tx(struct ath_softc_tgt *sc,
2086 ath_atx_tid_t *tid, struct ath_tx_buf *bf)
2089 struct ieee80211_frame_bar *bar;
2091 struct ath_tx_desc *ds, *ds0;
2092 struct ath_hal *ah = sc->sc_ah;
2093 HAL_11N_RATE_SERIES series[4];
2095 adf_nbuf_queue_t skbhead;
2099 __stats(sc, tx_bars);
2101 adf_os_mem_set(&series, 0, sizeof(series));
2103 ath_aggr_pause_tid(sc, tid);
2105 skb = adf_nbuf_queue_remove(&bf->bf_skbhead);
2106 adf_nbuf_peek_header(skb, &anbdata, &anblen);
2107 adf_nbuf_trim_tail(skb, anblen);
2108 bar = (struct ieee80211_frame_bar *) anbdata;
2112 ath_dma_unmap(sc, bf);
2113 adf_nbuf_queue_add(&bf->bf_skbhead, skb);
2115 bar->i_fc[1] = IEEE80211_FC1_DIR_NODS;
2116 bar->i_fc[0] = IEEE80211_FC0_VERSION_0 |
2117 IEEE80211_FC0_TYPE_CTL |
2118 IEEE80211_FC0_SUBTYPE_BAR;
2119 bar->i_ctl = tid->tidno << IEEE80211_BAR_CTL_TID_S |
2120 IEEE80211_BAR_CTL_COMBA;
2121 bar->i_seq = adf_os_cpu_to_le16(tid->seq_start << IEEE80211_SEQ_SEQ_SHIFT);
2123 bf->bf_seqno = tid->seq_start << IEEE80211_SEQ_SEQ_SHIFT;
2125 adf_nbuf_put_tail(skb, sizeof(struct ieee80211_frame_bar));
2127 bf->bf_comp = ath_bar_tx_comp;
2128 bf->bf_tidno = tid->tidno;
2129 bf->bf_node = &tid->an->ni;
2130 ath_dma_map(sc, bf);
2131 adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info);
2134 ah->ah_setupTxDesc(ds
2135 , adf_nbuf_len(skb) + IEEE80211_CRC_LEN
2137 , HAL_PKT_TYPE_NORMAL
2143 | HAL_TXDESC_CLRDMASK
2146 skbhead = bf->bf_skbhead;
2150 for (ds0 = ds, i=0; i < bf->bf_dmamap_info.nsegs; ds0++, i++) {
2151 ah->ah_clr11nAggr(ds0);
2154 ath_filltxdesc(sc, bf);
2156 for (i = 0 ; i < 4; i++) {
2157 series[i].Tries = ATH_TXMAXTRY;
2158 series[i].Rate = min_rate;
2159 series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
2162 ah->ah_set11nRateScenario(bf->bf_desc, 0, 0, series, 4, 4);
2163 ath_tgt_txq_add_ucast(sc, bf);