2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <adf_os_types.h>
37 #include <adf_os_dma.h>
38 #include <adf_os_timer.h>
39 #include <adf_os_lock.h>
40 #include <adf_os_io.h>
41 #include <adf_os_mem.h>
42 #include <adf_os_util.h>
43 #include <adf_os_stdtypes.h>
44 #include <adf_os_defer.h>
45 #include <adf_os_atomic.h>
48 #include <adf_net_wcmd.h>
52 #ifdef USE_HEADERLEN_RESV
56 #include <ieee80211_var.h>
57 #include "if_athrate.h"
58 #include "if_athvar.h"
61 #define ath_tgt_free_skb adf_nbuf_free
63 #define OFDM_PLCP_BITS 22
64 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
65 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
71 #define HT_LTF(_ns) (4 * (_ns))
72 #define SYMBOL_TIME(_ns) ((_ns) << 2) // ns * 4 us
73 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) // ns * 3.6 us
75 static a_uint16_t bits_per_symbol[][2] = {
77 { 26, 54 }, // 0: BPSK
78 { 52, 108 }, // 1: QPSK 1/2
79 { 78, 162 }, // 2: QPSK 3/4
80 { 104, 216 }, // 3: 16-QAM 1/2
81 { 156, 324 }, // 4: 16-QAM 3/4
82 { 208, 432 }, // 5: 64-QAM 2/3
83 { 234, 486 }, // 6: 64-QAM 3/4
84 { 260, 540 }, // 7: 64-QAM 5/6
85 { 52, 108 }, // 8: BPSK
86 { 104, 216 }, // 9: QPSK 1/2
87 { 156, 324 }, // 10: QPSK 3/4
88 { 208, 432 }, // 11: 16-QAM 1/2
89 { 312, 648 }, // 12: 16-QAM 3/4
90 { 416, 864 }, // 13: 64-QAM 2/3
91 { 468, 972 }, // 14: 64-QAM 3/4
92 { 520, 1080 }, // 15: 64-QAM 5/6
95 void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,
96 owl_txq_state_t txqstate);
97 static void ath_tgt_txqaddbuf(struct ath_softc_tgt *sc, struct ath_txq *txq,
98 struct ath_tx_buf *bf, struct ath_tx_desc *lastds);
99 void ath_rate_findrate_11n_Hardcoded(struct ath_softc_tgt *sc,
100 struct ath_rc_series series[]);
101 void ath_buf_set_rate_Hardcoded(struct ath_softc_tgt *sc,
102 struct ath_tx_buf *bf) ;
103 static a_int32_t ath_tgt_txbuf_setup(struct ath_softc_tgt *sc,
104 struct ath_tx_buf *bf, ath_data_hdr_t *dh);
105 static void ath_tx_freebuf(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
106 static void ath_tx_uc_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
107 static void ath_update_stats(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
108 void adf_print_buf(adf_nbuf_t buf);
109 static void ath_tgt_tx_enqueue(struct ath_txq *txq, struct ath_atx_tid *tid);
111 void ath_tgt_tx_comp_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
112 struct ieee80211_frame *ATH_SKB_2_WH(adf_nbuf_t skb);
114 void ath_tgt_tx_send_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
116 static void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
117 static void ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
119 extern a_int32_t ath_chainmask_sel_logic(void *);
120 static a_int32_t ath_get_pktlen(struct ath_tx_buf *bf, a_int32_t hdrlen);
121 static void ath_tgt_txq_schedule(struct ath_softc_tgt *sc, struct ath_txq *txq);
123 typedef void (*ath_ft_set_atype_t)(struct ath_softc_tgt *sc, struct ath_buf *bf);
126 ath_tx_set_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
129 ath_bar_tx(struct ath_softc_tgt *sc, ath_atx_tid_t *tid, struct ath_tx_buf *bf);
131 ath_tx_update_baw(ath_atx_tid_t *tid, int seqno);
133 ath_tx_retry_subframe(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
134 ath_tx_bufhead *bf_q, struct ath_tx_buf **bar);
137 ath_tx_comp_aggr_error(struct ath_softc_tgt *sc, struct ath_tx_buf *bf, ath_atx_tid_t *tid);
139 void ath_tx_addto_baw(ath_atx_tid_t *tid, struct ath_tx_buf *bf);
140 static inline void ath_tx_retry_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
141 static void ath_tx_comp_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
142 static void ath_update_aggr_stats(struct ath_softc_tgt *sc, struct ath_tx_desc *ds,
143 int nframes, int nbad);
144 static inline void ath_aggr_resume_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
145 static void ath_tx_comp_cleanup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
147 int ath_tgt_tx_add_to_aggr(struct ath_softc_tgt *sc,
148 struct ath_buf *bf,int datatype,
149 ath_atx_tid_t *tid, int is_burst);
151 struct ieee80211_frame *ATH_SKB_2_WH(adf_nbuf_t skb)
156 adf_nbuf_peek_header(skb, &anbdata, &anblen);
158 return((struct ieee80211_frame *)anbdata);
161 #undef adf_os_cpu_to_le16
163 static a_uint16_t adf_os_cpu_to_le16(a_uint16_t x)
165 return ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8));
169 ath_aggr_resume_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
173 txq = TID_TO_ACTXQ(tid->tidno);
176 if (asf_tailq_empty(&tid->buf_q))
179 ath_tgt_tx_enqueue(txq, tid);
180 ath_tgt_txq_schedule(sc, txq);
184 ath_aggr_pause_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
189 static a_uint32_t ath_pkt_duration(struct ath_softc_tgt *sc,
190 a_uint8_t rix, struct ath_tx_buf *bf,
191 a_int32_t width, a_int32_t half_gi)
193 const HAL_RATE_TABLE *rt = sc->sc_currates;
194 a_uint32_t nbits, nsymbits, duration, nsymbols;
199 pktlen = bf->bf_isaggr ? bf->bf_al : bf->bf_pktlen;
200 rc = rt->info[rix].rateCode;
203 return ath_hal_computetxtime(sc->sc_ah, rt, pktlen, rix,
206 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
207 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
208 nsymbols = (nbits + nsymbits - 1) / nsymbits;
211 duration = SYMBOL_TIME(nsymbols);
213 duration = SYMBOL_TIME_HALFGI(nsymbols);
215 streams = HT_RC_2_STREAMS(rc);
216 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
221 static void ath_dma_map(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
223 adf_nbuf_t skb = bf->bf_skb;
225 skb = adf_nbuf_queue_first(&bf->bf_skbhead);
226 adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, skb, ADF_OS_DMA_TO_DEVICE);
229 static void ath_dma_unmap(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
231 adf_nbuf_t skb = bf->bf_skb;
233 skb = adf_nbuf_queue_first(&bf->bf_skbhead);
234 adf_nbuf_unmap( sc->sc_dev, bf->bf_dmamap, ADF_OS_DMA_TO_DEVICE);
237 static void ath_filltxdesc(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
239 struct ath_tx_desc *ds0, *ds = bf->bf_desc;
240 struct ath_hal *ah = sc->sc_ah;
244 adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info);
246 for (i = 0; i < bf->bf_dmamap_info.nsegs; i++, ds++) {
248 ds->ds_data = bf->bf_dmamap_info.dma_segs[i].paddr;
250 if (i == (bf->bf_dmamap_info.nsegs - 1)) {
254 ds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, i+1);
256 ah->ah_fillTxDesc(ah, ds
257 , bf->bf_dmamap_info.dma_segs[i].len
259 , i == (bf->bf_dmamap_info.nsegs - 1)
264 static void ath_tx_tgt_setds(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
266 struct ath_tx_desc *ds = bf->bf_desc;
267 struct ath_hal *ah = sc->sc_ah;
269 switch (bf->bf_protmode) {
270 case IEEE80211_PROT_RTSCTS:
271 bf->bf_flags |= HAL_TXDESC_RTSENA;
273 case IEEE80211_PROT_CTSONLY:
274 bf->bf_flags |= HAL_TXDESC_CTSENA;
280 ah->ah_set11nTxDesc(ah, ds
286 , bf->bf_flags | HAL_TXDESC_INTREQ);
288 ath_filltxdesc(sc, bf);
291 static struct ath_tx_buf *ath_buf_toggle(struct ath_softc_tgt *sc,
292 struct ath_tx_buf *bf,
295 struct ath_tx_buf *tmp = NULL;
296 adf_nbuf_t buf = NULL;
298 adf_os_assert(sc->sc_txbuf_held != NULL);
300 tmp = sc->sc_txbuf_held;
303 ath_dma_unmap(sc, bf);
304 adf_nbuf_queue_init(&tmp->bf_skbhead);
305 buf = adf_nbuf_queue_remove(&bf->bf_skbhead);
307 adf_nbuf_queue_add(&tmp->bf_skbhead, buf);
309 adf_os_assert(adf_nbuf_queue_len(&bf->bf_skbhead) == 0);
311 tmp->bf_next = bf->bf_next;
312 tmp->bf_endpt = bf->bf_endpt;
313 tmp->bf_tidno = bf->bf_tidno;
314 tmp->bf_skb = bf->bf_skb;
315 tmp->bf_node = bf->bf_node;
316 tmp->bf_isaggr = bf->bf_isaggr;
317 tmp->bf_flags = bf->bf_flags;
318 tmp->bf_state = bf->bf_state;
319 tmp->bf_retries = bf->bf_retries;
320 tmp->bf_comp = bf->bf_comp;
321 tmp->bf_nframes = bf->bf_nframes;
322 tmp->bf_cookie = bf->bf_cookie;
334 ath_dma_map(sc, tmp);
335 ath_tx_tgt_setds(sc, tmp);
338 sc->sc_txbuf_held = bf;
343 static void ath_tgt_skb_free(struct ath_softc_tgt *sc,
344 adf_nbuf_queue_t *head,
345 HTC_ENDPOINT_ID endpt)
349 while (adf_nbuf_queue_len(head) != 0) {
350 tskb = adf_nbuf_queue_remove(head);
351 ath_free_tx_skb(sc->tgt_htc_handle,endpt,tskb);
355 static void ath_buf_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
357 ath_dma_unmap(sc, bf);
358 ath_tgt_skb_free(sc, &bf->bf_skbhead,bf->bf_endpt);
361 bf = ath_buf_toggle(sc, bf, 0);
363 asf_tailq_insert_tail(&sc->sc_txbuf, bf, bf_list);
367 static void ath_buf_set_rate(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
369 struct ath_hal *ah = sc->sc_ah;
370 const HAL_RATE_TABLE *rt;
371 struct ath_tx_desc *ds = bf->bf_desc;
372 HAL_11N_RATE_SERIES series[4];
374 a_uint8_t rix, cix, rtsctsrate;
375 a_uint32_t ctsduration = 0;
376 a_int32_t prot_mode = AH_FALSE;
378 rt = sc->sc_currates;
379 rix = bf->bf_rcs[0].rix;
380 flags = (bf->bf_flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA));
381 cix = rt->info[sc->sc_protrix].controlRate;
383 if (bf->bf_protmode != IEEE80211_PROT_NONE &&
384 (rt->info[rix].phy == IEEE80211_T_OFDM ||
385 rt->info[rix].phy == IEEE80211_T_HT) &&
386 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
387 cix = rt->info[sc->sc_protrix].controlRate;
390 if (ath_hal_htsupported(ah) && (!bf->bf_ismcast))
391 flags = HAL_TXDESC_RTSENA;
394 if (bf->bf_rcs[i].tries) {
395 cix = rt->info[bf->bf_rcs[i].rix].controlRate;
402 adf_os_mem_set(series, 0, sizeof(HAL_11N_RATE_SERIES) * 4);
404 for (i = 0; i < 4; i++) {
405 if (!bf->bf_rcs[i].tries)
408 rix = bf->bf_rcs[i].rix;
410 series[i].Rate = rt->info[rix].rateCode |
411 (bf->bf_shpream ? rt->info[rix].shortPreamble : 0);
413 series[i].Tries = bf->bf_rcs[i].tries;
415 series[i].RateFlags = ((bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
416 HAL_RATESERIES_RTS_CTS : 0 ) |
417 ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
418 HAL_RATESERIES_2040 : 0 ) |
419 ((bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG) ?
420 HAL_RATESERIES_HALFGI : 0 ) |
421 ((bf->bf_rcs[i].flags & ATH_RC_TX_STBC_FLAG) ?
422 HAL_RATESERIES_STBC: 0);
424 series[i].RateFlags = ((bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
425 HAL_RATESERIES_RTS_CTS : 0 ) |
426 ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
427 HAL_RATESERIES_2040 : 0 ) |
428 ((bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG) ?
429 HAL_RATESERIES_HALFGI : 0 );
431 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
432 (bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) != 0,
433 (bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG));
435 series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
438 series[i].RateFlags |= HAL_RATESERIES_RTS_CTS;
440 if (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG)
441 series[i].RateFlags |= HAL_RATESERIES_RTS_CTS;
444 rtsctsrate = rt->info[cix].rateCode |
445 (bf->bf_shpream ? rt->info[cix].shortPreamble : 0);
447 ah->ah_set11nRateScenario(ah, ds, 1,
448 rtsctsrate, ctsduration,
453 static void ath_tgt_rate_findrate(struct ath_softc_tgt *sc,
454 struct ath_node_target *an,
455 a_int32_t shortPreamble,
461 struct ath_rc_series series[],
464 ath_rate_findrate(sc, an, 1, frameLen, 10, 4, 1,
465 ATH_RC_PROBE_ALLOWED, series, isProbe);
468 static void owl_tgt_tid_init(struct ath_atx_tid *tid)
472 tid->seq_start = tid->seq_next = 0;
473 tid->baw_size = WME_MAX_BA;
474 tid->baw_head = tid->baw_tail = 0;
477 tid->sched = AH_FALSE;
479 asf_tailq_init(&tid->buf_q);
481 for (i = 0; i < ATH_TID_MAX_BUFS; i++) {
482 TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, i);
486 static void owl_tgt_tid_cleanup(struct ath_softc_tgt *sc,
487 struct ath_atx_tid *tid)
494 tid->flag &= ~TID_CLEANUP_INPROGRES;
496 if (tid->flag & TID_REINITIALIZE) {
497 adf_os_print("TID REINIT DONE for tid %p\n", tid);
498 tid->flag &= ~TID_REINITIALIZE;
499 owl_tgt_tid_init(tid);
501 ath_aggr_resume_tid(sc, tid);
505 void owl_tgt_node_init(struct ath_node_target * an)
507 struct ath_atx_tid *tid;
510 for (tidno = 0, tid = &an->tid[tidno]; tidno < WME_NUM_TID;tidno++, tid++) {
514 if ( tid->flag & TID_CLEANUP_INPROGRES ) {
515 tid->flag |= TID_REINITIALIZE;
516 adf_os_print("tid[%p]->incomp is not 0: %d\n",
519 owl_tgt_tid_init(tid);
524 void ath_tx_status_clear(struct ath_softc_tgt *sc)
528 for (i = 0; i < 2; i++) {
529 sc->tx_status[i].cnt = 0;
533 static WMI_TXSTATUS_EVENT *ath_tx_status_get(struct ath_softc_tgt *sc)
535 WMI_TXSTATUS_EVENT *txs = NULL;
538 for (i = 0; i < 2; i++) {
539 if (sc->tx_status[i].cnt < HTC_MAX_TX_STATUS) {
540 txs = &sc->tx_status[i];
548 void ath_tx_status_update(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
550 struct ath_tx_desc *ds = bf->bf_lastds;
551 WMI_TXSTATUS_EVENT *txs;
553 if (sc->sc_tx_draining)
556 txs = ath_tx_status_get(sc);
560 txs->txstatus[txs->cnt].cookie = bf->bf_cookie;
561 txs->txstatus[txs->cnt].ts_rate = SM(bf->bf_endpt, ATH9K_HTC_TXSTAT_EPID);
563 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
564 txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_FILT;
566 if (!(ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) &&
567 !(ds->ds_txstat.ts_status & HAL_TXERR_FIFO) &&
568 !(ds->ds_txstat.ts_status & HAL_TXERR_TIMER_EXPIRED) &&
569 !(ds->ds_txstat.ts_status & HAL_TXERR_FILT))
570 txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_ACK;
572 ath_tx_status_update_rate(sc, bf->bf_rcs, ds->ds_txstat.ts_rate, txs);
577 void ath_tx_status_update_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
578 struct ath_tx_desc *ds, struct ath_rc_series rcs[],
581 WMI_TXSTATUS_EVENT *txs;
583 if (sc->sc_tx_draining)
586 txs = ath_tx_status_get(sc);
590 txs->txstatus[txs->cnt].cookie = bf->bf_cookie;
591 txs->txstatus[txs->cnt].ts_rate = SM(bf->bf_endpt, ATH9K_HTC_TXSTAT_EPID);
594 txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_ACK;
597 ath_tx_status_update_rate(sc, rcs, ds->ds_txstat.ts_rate, txs);
602 void ath_tx_status_send(struct ath_softc_tgt *sc)
606 if (sc->sc_tx_draining)
609 for (i = 0; i < 2; i++) {
610 if (sc->tx_status[i].cnt) {
611 wmi_event(sc->tgt_wmi_handle, WMI_TXSTATUS_EVENTID,
612 &sc->tx_status[i], sizeof(WMI_TXSTATUS_EVENT));
613 /* FIXME: Handle failures. */
614 sc->tx_status[i].cnt = 0;
619 static void owltgt_tx_process_cabq(struct ath_softc_tgt *sc, struct ath_txq *txq)
621 struct ath_hal *ah = sc->sc_ah;
622 ah->ah_setInterrupts(ah, sc->sc_imask & ~HAL_INT_SWBA);
623 owltgt_tx_processq(sc, txq, OWL_TXQ_ACTIVE);
624 ah->ah_setInterrupts(ah, sc->sc_imask);
627 void owl_tgt_tx_tasklet(TQUEUE_ARG data)
629 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
633 ath_tx_status_clear(sc);
635 for (i = 0; i < (HAL_NUM_TX_QUEUES - 6); i++) {
636 txq = ATH_TXQ(sc, i);
638 if (ATH_TXQ_SETUP(sc, i)) {
639 if (txq == sc->sc_cabq)
640 owltgt_tx_process_cabq(sc, txq);
642 owltgt_tx_processq(sc, txq, OWL_TXQ_ACTIVE);
646 ath_tx_status_send(sc);
649 void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,
650 owl_txq_state_t txqstate)
652 struct ath_tx_buf *bf;
653 struct ath_tx_desc *ds;
657 if (asf_tailq_empty(&txq->axq_q)) {
658 txq->axq_link = NULL;
659 txq->axq_linkbuf = NULL;
663 bf = asf_tailq_first(&txq->axq_q);
666 status = ath_hal_txprocdesc(sc->sc_ah, ds);
668 if (status == HAL_EINPROGRESS) {
669 if (txqstate == OWL_TXQ_ACTIVE)
671 else if (txqstate == OWL_TXQ_STOPPED) {
672 __stats(sc, tx_stopfiltered);
673 ds->ds_txstat.ts_flags = 0;
674 ds->ds_txstat.ts_status = HAL_OK;
676 ds->ds_txstat.ts_flags = HAL_TX_SW_FILTERED;
680 ATH_TXQ_REMOVE_HEAD(txq, bf, bf_list);
681 if ((asf_tailq_empty(&txq->axq_q))) {
682 __stats(sc, tx_qnull);
683 txq->axq_link = NULL;
684 txq->axq_linkbuf = NULL;
690 ath_tx_status_update(sc, bf);
691 ath_buf_comp(sc, bf);
694 if (txqstate == OWL_TXQ_ACTIVE) {
695 ath_tgt_txq_schedule(sc, txq);
700 static struct ieee80211_frame* ATH_SKB2_WH(adf_nbuf_t skb)
705 adf_nbuf_peek_header(skb, &anbdata, &anblen);
706 return((struct ieee80211_frame *)anbdata);
710 ath_tgt_tid_drain(struct ath_softc_tgt *sc, struct ath_atx_tid *tid)
712 struct ath_tx_buf *bf;
714 while (!asf_tailq_empty(&tid->buf_q)) {
715 TAILQ_DEQ(&tid->buf_q, bf, bf_list);
716 ath_tx_freebuf(sc, bf);
719 tid->seq_next = tid->seq_start;
720 tid->baw_tail = tid->baw_head;
723 static void ath_tgt_tx_comp_normal(struct ath_softc_tgt *sc,
724 struct ath_tx_buf *bf)
726 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
727 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
729 if (tid->flag & TID_CLEANUP_INPROGRES) {
730 owl_tgt_tid_cleanup(sc, tid);
734 ath_tx_uc_comp(sc, bf);
737 ath_tx_freebuf(sc, bf);
740 static struct ieee80211_node_target * ath_tgt_find_node(struct ath_softc_tgt *sc,
741 a_int32_t node_index)
743 struct ath_node_target *an;
744 struct ieee80211_node_target *ni;
746 if (node_index > TARGET_NODE_MAX)
749 an = &sc->sc_sta[node_index];
753 if (ni->ni_vap == NULL) {
762 static struct ath_tx_buf* ath_tx_buf_alloc(struct ath_softc_tgt *sc)
764 struct ath_tx_buf *bf = NULL;
766 bf = asf_tailq_first(&sc->sc_txbuf);
768 adf_os_mem_set(&bf->bf_state, 0, sizeof(struct ath_buf_state));
769 asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
777 struct ath_tx_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc,
778 adf_nbuf_t skb, ath_data_hdr_t *dh)
780 struct ath_tx_buf *bf;
781 struct ieee80211_node_target *ni;
782 struct ath_atx_tid *tid;
784 ni = ath_tgt_find_node(sc, dh->ni_index);
788 tid = ATH_AN_2_TID(ATH_NODE_TARGET(ni), dh->tidno);
789 if (tid->flag & TID_REINITIALIZE) {
790 adf_os_print("drop frame due to TID reinit\n");
794 bf = ath_tx_buf_alloc(sc);
796 __stats(sc, tx_nobufs);
800 bf->bf_tidno = dh->tidno;
801 bf->bf_txq = TID_TO_ACTXQ(bf->bf_tidno);
802 bf->bf_keytype = dh->keytype;
803 bf->bf_keyix = dh->keyix;
804 bf->bf_protmode = dh->flags & (IEEE80211_PROT_RTSCTS | IEEE80211_PROT_CTSONLY);
807 adf_nbuf_queue_add(&bf->bf_skbhead, skb);
808 skb = adf_nbuf_queue_first(&(bf->bf_skbhead));
810 if (adf_nbuf_queue_len(&(bf->bf_skbhead)) == 0) {
811 __stats(sc, tx_noskbs);
819 ath_tgt_txbuf_setup(sc, bf, dh);
821 ath_tx_tgt_setds(sc, bf);
826 static void ath_tgt_tx_seqno_normal(struct ath_tx_buf *bf)
828 struct ieee80211_node_target *ni = bf->bf_node;
829 struct ath_node_target *an = ATH_NODE_TARGET(ni);
830 struct ieee80211_frame *wh = ATH_SKB_2_WH(bf->bf_skb);
831 struct ath_atx_tid *tid = ATH_AN_2_TID(an, bf->bf_tidno);
833 u_int8_t fragno = (wh->i_seq[0] & 0xf);
835 INCR(ni->ni_txseqmgmt, IEEE80211_SEQ_MAX);
837 bf->bf_seqno = (tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
839 *(u_int16_t *)wh->i_seq = adf_os_cpu_to_le16(bf->bf_seqno);
840 wh->i_seq[0] |= fragno;
842 if (!(wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG))
843 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
846 static a_int32_t ath_key_setup(struct ieee80211_node_target *ni,
847 struct ath_tx_buf *bf)
849 struct ieee80211_frame *wh = ATH_SKB_2_WH(bf->bf_skb);
851 if (!(wh->i_fc[1] & IEEE80211_FC1_WEP)) {
852 bf->bf_keytype = HAL_KEY_TYPE_CLEAR;
853 bf->bf_keyix = HAL_TXKEYIX_INVALID;
857 switch (bf->bf_keytype) {
858 case HAL_KEY_TYPE_WEP:
859 bf->bf_pktlen += IEEE80211_WEP_ICVLEN;
861 case HAL_KEY_TYPE_AES:
862 bf->bf_pktlen += IEEE80211_WEP_MICLEN;
864 case HAL_KEY_TYPE_TKIP:
865 bf->bf_pktlen += IEEE80211_WEP_ICVLEN;
871 if (bf->bf_keytype == HAL_KEY_TYPE_AES ||
872 bf->bf_keytype == HAL_KEY_TYPE_TKIP)
873 ieee80211_tgt_crypto_encap(wh, ni, bf->bf_keytype);
878 static void ath_tgt_txq_add_ucast(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
880 struct ath_hal *ah = sc->sc_ah;
883 volatile a_int32_t txe_val;
889 status = ath_hal_txprocdesc(sc->sc_ah, bf->bf_lastds);
891 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
893 if (txq->axq_link == NULL) {
894 ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
896 *txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
898 txe_val = OS_REG_READ(ah, 0x840);
899 if (!(txe_val & (1<< txq->axq_qnum)))
900 ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
903 txq->axq_link = &bf->bf_lastds->ds_link;
904 ah->ah_startTxDma(ah, txq->axq_qnum);
907 static a_int32_t ath_tgt_txbuf_setup(struct ath_softc_tgt *sc,
908 struct ath_tx_buf *bf,
912 struct ieee80211_frame *wh = ATH_SKB2_WH(bf->bf_skb);
914 a_uint32_t flags = adf_os_ntohl(dh->flags);
916 ath_tgt_tx_seqno_normal(bf);
918 bf->bf_txq_add = ath_tgt_txq_add_ucast;
919 bf->bf_hdrlen = ieee80211_anyhdrsize(wh);
920 bf->bf_pktlen = ath_get_pktlen(bf, bf->bf_hdrlen);
921 bf->bf_ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
923 if ((retval = ath_key_setup(bf->bf_node, bf)) < 0)
926 if (flags & ATH_SHORT_PREAMBLE)
927 bf->bf_shpream = AH_TRUE;
929 bf->bf_shpream = AH_FALSE;
931 bf->bf_flags = HAL_TXDESC_CLRDMASK;
932 bf->bf_atype = HAL_PKT_TYPE_NORMAL;
938 ath_get_pktlen(struct ath_tx_buf *bf, a_int32_t hdrlen)
940 adf_nbuf_t skb = bf->bf_skb;
943 skb = adf_nbuf_queue_first(&bf->bf_skbhead);
944 pktlen = adf_nbuf_len(skb);
946 pktlen -= (hdrlen & 3);
947 pktlen += IEEE80211_CRC_LEN;
953 ath_tgt_tx_send_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
955 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
956 struct ath_rc_series rcs[4];
957 struct ath_rc_series mrcs[4];
958 a_int32_t shortPreamble = 0;
959 a_int32_t isProbe = 0;
961 adf_os_mem_set(rcs, 0, sizeof(struct ath_rc_series)*4 );
962 adf_os_mem_set(mrcs, 0, sizeof(struct ath_rc_series)*4 );
964 if (!bf->bf_ismcast) {
965 ath_tgt_rate_findrate(sc, an, shortPreamble,
968 ath_hal_memcpy(bf->bf_rcs, rcs, sizeof(rcs));
970 mrcs[1].tries = mrcs[2].tries = mrcs[3].tries = 0;
971 mrcs[1].rix = mrcs[2].rix = mrcs[3].rix = 0;
975 ath_hal_memcpy(bf->bf_rcs, mrcs, sizeof(mrcs));
978 ath_buf_set_rate(sc, bf);
979 bf->bf_txq_add(sc, bf);
983 ath_tx_freebuf(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
986 struct ath_tx_desc *bfd = NULL;
987 struct ath_hal *ah = sc->sc_ah;
989 for (bfd = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; bfd++, i++) {
990 ah->ah_clr11nAggr(ah, bfd);
991 ah->ah_set11nBurstDuration(ah, bfd, 0);
992 ath_hal_set11n_virtualmorefrag(sc->sc_ah, bfd, 0);
995 ath_dma_unmap(sc, bf);
997 ath_tgt_skb_free(sc, &bf->bf_skbhead,bf->bf_endpt);
1003 bf = ath_buf_toggle(sc, bf, 0);
1005 bf->bf_isretried = 0;
1008 asf_tailq_insert_tail(&sc->sc_txbuf, bf, bf_list);
1012 ath_tx_uc_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1014 ath_tx_status_update(sc, bf);
1015 ath_update_stats(sc, bf);
1016 ath_rate_tx_complete(sc, ATH_NODE_TARGET(bf->bf_node),
1017 bf->bf_lastds, bf->bf_rcs, 1, 0);
1021 ath_update_stats(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1023 struct ath_tx_desc *ds = bf->bf_desc;
1026 if (ds->ds_txstat.ts_status == 0) {
1027 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE)
1028 sc->sc_tx_stats.ast_tx_altrate++;
1030 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY)
1031 sc->sc_tx_stats.ast_tx_xretries++;
1032 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO)
1033 sc->sc_tx_stats.ast_tx_fifoerr++;
1034 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
1035 sc->sc_tx_stats.ast_tx_filtered++;
1036 if (ds->ds_txstat.ts_status & HAL_TXERR_TIMER_EXPIRED)
1037 sc->sc_tx_stats.ast_tx_timer_exp++;
1039 sr = ds->ds_txstat.ts_shortretry;
1040 lr = ds->ds_txstat.ts_longretry;
1041 sc->sc_tx_stats.ast_tx_shortretry += sr;
1042 sc->sc_tx_stats.ast_tx_longretry += lr;
1046 ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t hdr_buf, adf_nbuf_t skb,
1047 HTC_ENDPOINT_ID endpt)
1049 struct ieee80211_node_target *ni;
1050 struct ieee80211vap_target *vap;
1051 struct ath_vap_target *avp;
1052 struct ath_hal *ah = sc->sc_ah;
1053 a_uint8_t rix, txrate, ctsrate, cix = 0xff, *data;
1054 a_uint32_t ivlen = 0, icvlen = 0, subtype, flags, ctsduration;
1055 a_int32_t i, iswep, ismcast, hdrlen, pktlen, try0, len;
1056 struct ath_tx_desc *ds=NULL;
1057 struct ath_txq *txq=NULL;
1058 struct ath_tx_buf *bf;
1060 const HAL_RATE_TABLE *rt;
1061 HAL_BOOL shortPreamble;
1062 struct ieee80211_frame *wh;
1063 struct ath_rc_series rcs[4];
1064 HAL_11N_RATE_SERIES series[4];
1069 adf_nbuf_peek_header(skb, &data, &len);
1070 adf_nbuf_pull_head(skb, sizeof(ath_mgt_hdr_t));
1072 adf_nbuf_peek_header(hdr_buf, &data, &len);
1075 adf_os_assert(len >= sizeof(ath_mgt_hdr_t));
1077 mh = (ath_mgt_hdr_t *)data;
1078 adf_nbuf_peek_header(skb, &data, &len);
1079 wh = (struct ieee80211_frame *)data;
1081 adf_os_mem_set(rcs, 0, sizeof(struct ath_rc_series)*4);
1082 adf_os_mem_set(series, 0, sizeof(HAL_11N_RATE_SERIES)*4);
1084 bf = asf_tailq_first(&sc->sc_txbuf);
1088 asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
1090 ni = ath_tgt_find_node(sc, mh->ni_index);
1094 bf->bf_endpt = endpt;
1095 bf->bf_cookie = mh->cookie;
1096 bf->bf_protmode = mh->flags & (IEEE80211_PROT_RTSCTS | IEEE80211_PROT_CTSONLY);
1097 txq = &sc->sc_txq[1];
1098 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
1099 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
1100 hdrlen = ieee80211_anyhdrsize(wh);
1102 keyix = HAL_TXKEYIX_INVALID;
1103 pktlen -= (hdrlen & 3);
1104 pktlen += IEEE80211_CRC_LEN;
1109 adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, skb, ADF_OS_DMA_TO_DEVICE);
1112 adf_nbuf_queue_add(&bf->bf_skbhead, skb);
1115 rt = sc->sc_currates;
1116 adf_os_assert(rt != NULL);
1118 if (mh->flags == ATH_SHORT_PREAMBLE)
1119 shortPreamble = AH_TRUE;
1121 shortPreamble = AH_FALSE;
1123 flags = HAL_TXDESC_CLRDMASK;
1125 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
1126 case IEEE80211_FC0_TYPE_MGT:
1127 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
1129 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
1130 atype = HAL_PKT_TYPE_PROBE_RESP;
1131 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM)
1132 atype = HAL_PKT_TYPE_ATIM;
1134 atype = HAL_PKT_TYPE_NORMAL;
1138 atype = HAL_PKT_TYPE_NORMAL;
1142 avp = &sc->sc_vap[mh->vap_index];
1144 rcs[0].rix = ath_get_minrateidx(sc, avp);
1145 rcs[0].tries = ATH_TXMAXTRY;
1148 adf_os_mem_copy(bf->bf_rcs, rcs, sizeof(rcs));
1150 try0 = rcs[0].tries;
1151 txrate = rt->info[rix].rateCode;
1154 txrate |= rt->info[rix].shortPreamble;
1161 flags |= HAL_TXDESC_NOACK;
1163 } else if (pktlen > vap->iv_rtsthreshold) {
1164 flags |= HAL_TXDESC_RTSENA;
1165 cix = rt->info[rix].controlRate;
1168 if ((bf->bf_protmode != IEEE80211_PROT_NONE) &&
1169 rt->info[rix].phy == IEEE80211_T_OFDM &&
1170 (flags & HAL_TXDESC_NOACK) == 0) {
1171 cix = rt->info[sc->sc_protrix].controlRate;
1172 sc->sc_tx_stats.ast_tx_protect++;
1175 *(a_uint16_t *)&wh->i_seq[0] = adf_os_cpu_to_le16(ni->ni_txseqmgmt <<
1176 IEEE80211_SEQ_SEQ_SHIFT);
1177 INCR(ni->ni_txseqmgmt, IEEE80211_SEQ_MAX);
1180 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) {
1181 adf_os_assert(cix != 0xff);
1182 ctsrate = rt->info[cix].rateCode;
1183 if (shortPreamble) {
1184 ctsrate |= rt->info[cix].shortPreamble;
1185 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
1186 ctsduration += rt->info[cix].spAckDuration;
1187 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
1188 ctsduration += rt->info[cix].spAckDuration;
1190 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
1191 ctsduration += rt->info[cix].lpAckDuration;
1192 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
1193 ctsduration += rt->info[cix].lpAckDuration;
1195 ctsduration += ath_hal_computetxtime(ah,
1196 rt, pktlen, rix, shortPreamble);
1201 flags |= HAL_TXDESC_INTREQ;
1203 ah->ah_setupTxDesc(ah, ds
1216 , ATH_COMP_PROC_NO_COMP_NO_CCS);
1218 bf->bf_flags = flags;
1221 * Set key type in tx desc while sending the encrypted challenge to AP
1222 * in Auth frame 3 of Shared Authentication, owl needs this.
1224 if (iswep && (keyix != HAL_TXKEYIX_INVALID) &&
1225 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == IEEE80211_FC0_SUBTYPE_AUTH)
1226 ah->ah_fillKeyTxDesc(ah, ds, mh->keytype);
1228 ath_filltxdesc(sc, bf);
1230 for (i=0; i<4; i++) {
1231 series[i].Tries = 2;
1232 series[i].Rate = txrate;
1233 series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
1234 series[i].RateFlags = 0;
1236 ah->ah_set11nRateScenario(ah, ds, 0, ctsrate, ctsduration, series, 4, 0);
1237 ath_tgt_txqaddbuf(sc, txq, bf, bf->bf_lastds);
1241 HTC_ReturnBuffers(sc->tgt_htc_handle, endpt, skb);
1246 ath_tgt_txqaddbuf(struct ath_softc_tgt *sc,
1247 struct ath_txq *txq, struct ath_tx_buf *bf,
1248 struct ath_tx_desc *lastds)
1250 struct ath_hal *ah = sc->sc_ah;
1252 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
1254 if (txq->axq_link == NULL) {
1255 ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
1257 *txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
1260 txq->axq_link = &lastds->ds_link;
1261 ah->ah_startTxDma(ah, txq->axq_qnum);
1264 void ath_tgt_handle_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1267 struct ath_node_target *an;
1269 an = (struct ath_node_target *)bf->bf_node;
1272 tid = &an->tid[bf->bf_tidno];
1275 bf->bf_comp = ath_tgt_tx_comp_normal;
1276 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1277 ath_tgt_tx_send_normal(sc, bf);
1281 ath_tgt_tx_enqueue(struct ath_txq *txq, struct ath_atx_tid *tid)
1289 tid->sched = AH_TRUE;
1290 asf_tailq_insert_tail(&txq->axq_tidq, tid, tid_qelem);
1294 ath_tgt_txq_schedule(struct ath_softc_tgt *sc, struct ath_txq *txq)
1296 struct ath_atx_tid *tid;
1302 TAILQ_DEQ(&txq->axq_tidq, tid, tid_qelem);
1307 tid->sched = AH_FALSE;
1312 if (!(tid->flag & TID_AGGR_ENABLED))
1313 ath_tgt_tx_sched_normal(sc,tid);
1315 ath_tgt_tx_sched_aggr(sc,tid);
1319 if (!asf_tailq_empty(&tid->buf_q)) {
1320 ath_tgt_tx_enqueue(txq, tid);
1323 } while (!asf_tailq_empty(&txq->axq_tidq) && !bdone);
1327 ath_tgt_handle_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1330 struct ath_node_target *an;
1331 struct ath_txq *txq = bf->bf_txq;
1332 a_bool_t queue_frame, within_baw;
1334 an = (struct ath_node_target *)bf->bf_node;
1337 tid = &an->tid[bf->bf_tidno];
1340 bf->bf_comp = ath_tgt_tx_comp_aggr;
1342 within_baw = BAW_WITHIN(tid->seq_start, tid->baw_size,
1343 SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1345 queue_frame = ( (txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) ||
1346 (!asf_tailq_empty(&tid->buf_q)) ||
1347 (tid->paused) || (!within_baw) );
1350 asf_tailq_insert_tail(&tid->buf_q, bf, bf_list);
1351 ath_tgt_tx_enqueue(txq, tid);
1353 ath_tx_addto_baw(tid, bf);
1354 __stats(sc, txaggr_nframes);
1355 ath_tgt_tx_send_normal(sc, bf);
1360 ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
1362 struct ath_tx_buf *bf;
1363 struct ath_txq *txq =TID_TO_ACTXQ(tid->tidno);;
1366 if (asf_tailq_empty(&tid->buf_q))
1369 bf = asf_tailq_first(&tid->buf_q);
1370 asf_tailq_remove(&tid->buf_q, bf, bf_list);
1371 ath_tgt_tx_send_normal(sc, bf);
1373 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH);
1377 ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
1379 struct ath_tx_buf *bf, *bf_last;
1380 ATH_AGGR_STATUS status;
1381 ath_tx_bufhead bf_q;
1382 struct ath_txq *txq = TID_TO_ACTXQ(tid->tidno);
1383 struct ath_tx_desc *ds = NULL;
1384 struct ath_hal *ah = sc->sc_ah;
1388 if (asf_tailq_empty(&tid->buf_q))
1392 if (asf_tailq_empty(&tid->buf_q))
1395 asf_tailq_init(&bf_q);
1397 status = ath_tgt_tx_form_aggr(sc, tid, &bf_q);
1399 if (asf_tailq_empty(&bf_q))
1402 bf = asf_tailq_first(&bf_q);
1403 bf_last = asf_tailq_last(&bf_q, ath_tx_bufhead_s);
1405 if (bf->bf_nframes == 1) {
1407 if(bf->bf_retries == 0)
1408 __stats(sc, txaggr_single);
1410 bf->bf_lastds = &(bf->bf_descarr[bf->bf_dmamap_info.nsegs -1]);
1411 bf->bf_lastds->ds_link = 0;
1414 for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
1415 ah->ah_clr11nAggr(ah, ds);
1417 ath_buf_set_rate(sc, bf);
1418 bf->bf_txq_add(sc, bf);
1423 bf_last->bf_next = NULL;
1424 bf_last->bf_lastds->ds_link = 0;
1425 bf_last->bf_ndelim = 0;
1428 ath_buf_set_rate(sc, bf);
1429 ah->ah_set11nAggrFirst(ah, bf->bf_desc, bf->bf_al,
1431 bf->bf_lastds = bf_last->bf_lastds;
1433 for (i = 0; i < bf_last->bf_dmamap_info.nsegs; i++)
1434 ah->ah_set11nAggrLast(ah, &bf_last->bf_descarr[i]);
1436 if (status == ATH_AGGR_8K_LIMITED) {
1441 bf->bf_txq_add(sc, bf);
1442 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
1443 status != ATH_TGT_AGGR_BAW_CLOSED);
1446 static u_int32_t ath_lookup_rate(struct ath_softc_tgt *sc,
1447 struct ath_node_target *an,
1448 struct ath_tx_buf *bf)
1451 u_int32_t max4msframelen, frame_length;
1452 u_int16_t aggr_limit, legacy=0;
1453 const HAL_RATE_TABLE *rt = sc->sc_currates;
1454 struct ieee80211_node_target *ieee_node = (struct ieee80211_node_target *)an;
1456 if (bf->bf_ismcast) {
1457 bf->bf_rcs[1].tries = bf->bf_rcs[2].tries = bf->bf_rcs[3].tries = 0;
1458 bf->bf_rcs[0].rix = 0xb;
1459 bf->bf_rcs[0].tries = ATH_TXMAXTRY - 1;
1460 bf->bf_rcs[0].flags = 0;
1462 ath_tgt_rate_findrate(sc, an, AH_TRUE, 0, ATH_TXMAXTRY-1, 4, 1,
1463 ATH_RC_PROBE_ALLOWED, bf->bf_rcs, &prate);
1466 max4msframelen = IEEE80211_AMPDU_LIMIT_MAX;
1468 for (i = 0; i < 4; i++) {
1469 if (bf->bf_rcs[i].tries) {
1470 frame_length = bf->bf_rcs[i].max4msframelen;
1472 if (rt->info[bf->bf_rcs[i].rix].phy != IEEE80211_T_HT) {
1477 max4msframelen = ATH_MIN(max4msframelen, frame_length);
1481 if (prate || legacy)
1484 if (sc->sc_ic.ic_enable_coex)
1485 aggr_limit = ATH_MIN((max4msframelen*3)/8, sc->sc_ic.ic_ampdu_limit);
1487 aggr_limit = ATH_MIN(max4msframelen, sc->sc_ic.ic_ampdu_limit);
1489 if (ieee_node->ni_maxampdu)
1490 aggr_limit = ATH_MIN(aggr_limit, ieee_node->ni_maxampdu);
1495 int ath_tgt_tx_form_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid,
1496 ath_tx_bufhead *bf_q)
1498 struct ath_tx_buf *bf_first ,*bf_prev = NULL;
1499 int nframes = 0, rl = 0;;
1500 struct ath_tx_desc *ds = NULL;
1501 struct ath_tx_buf *bf;
1502 struct ath_hal *ah = sc->sc_ah;
1503 u_int16_t aggr_limit = (64*1024 -1), al = 0, bpad = 0, al_delta;
1504 u_int16_t h_baw = tid->baw_size/2, prev_al = 0, prev_frames = 0;
1506 bf_first = asf_tailq_first(&tid->buf_q);
1509 bf = asf_tailq_first(&tid->buf_q);
1512 if (!BAW_WITHIN(tid->seq_start, tid->baw_size,
1513 SEQNO_FROM_BF_SEQNO(bf->bf_seqno))) {
1515 bf_first->bf_al= al;
1516 bf_first->bf_nframes = nframes;
1517 return ATH_TGT_AGGR_BAW_CLOSED;
1521 aggr_limit = ath_lookup_rate(sc, tid->an, bf);
1525 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_pktlen;
1527 if (nframes && (aggr_limit < (al + bpad + al_delta + prev_al))) {
1528 bf_first->bf_al= al;
1529 bf_first->bf_nframes = nframes;
1530 return ATH_TGT_AGGR_LIMITED;
1534 if ((nframes + prev_frames) >= ATH_MIN((h_baw), 17)) {
1536 if ((nframes + prev_frames) >= ATH_MIN((h_baw), 22)) {
1538 bf_first->bf_al= al;
1539 bf_first->bf_nframes = nframes;
1540 return ATH_TGT_AGGR_LIMITED;
1543 ath_tx_addto_baw(tid, bf);
1544 asf_tailq_remove(&tid->buf_q, bf, bf_list);
1545 asf_tailq_insert_tail(bf_q, bf, bf_list);
1550 adf_os_assert(bf->bf_comp == ath_tgt_tx_comp_aggr);
1552 al += bpad + al_delta;
1553 bf->bf_ndelim = ATH_AGGR_GET_NDELIM(bf->bf_pktlen);
1555 switch (bf->bf_keytype) {
1556 case HAL_KEY_TYPE_AES:
1557 bf->bf_ndelim += ATH_AGGR_ENCRYPTDELIM;
1559 case HAL_KEY_TYPE_WEP:
1560 case HAL_KEY_TYPE_TKIP:
1561 bf->bf_ndelim += 64;
1563 case HAL_KEY_TYPE_WAPI:
1564 bf->bf_ndelim += 12;
1570 bpad = PADBYTES(al_delta) + (bf->bf_ndelim << 2);
1573 bf_prev->bf_next = bf;
1574 bf_prev->bf_lastds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
1578 for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
1579 ah->ah_set11nAggrMiddle(ah, ds, bf->bf_ndelim);
1581 } while (!asf_tailq_empty(&tid->buf_q));
1583 bf_first->bf_al= al;
1584 bf_first->bf_nframes = nframes;
1586 return ATH_TGT_AGGR_DONE;
1589 void ath_tx_addto_baw(ath_atx_tid_t *tid, struct ath_tx_buf *bf)
1593 if (bf->bf_isretried) {
1597 index = ATH_BA_INDEX(tid->seq_start, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1598 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1600 TX_BUF_BITMAP_SET(tid->tx_buf_bitmap, cindex);
1602 if (index >= ((tid->baw_tail - tid->baw_head) & (ATH_TID_MAX_BUFS - 1))) {
1603 tid->baw_tail = cindex;
1604 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
1608 void ath_tgt_tx_comp_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1610 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1611 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1612 struct ath_tx_desc lastds;
1613 struct ath_tx_desc *ds = &lastds;
1614 struct ath_rc_series rcs[4];
1619 int nframes = bf->bf_nframes;
1620 struct ath_tx_buf *bf_next;
1621 ath_tx_bufhead bf_q;
1623 struct ath_tx_buf *bar = NULL;
1624 struct ath_txq *txq;
1628 if (tid->flag & TID_CLEANUP_INPROGRES) {
1629 ath_tx_comp_cleanup(sc, bf);
1633 adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
1634 adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
1636 if (ds->ds_txstat.ts_flags == HAL_TX_SW_FILTERED) {
1641 if (!bf->bf_isaggr) {
1642 ath_tx_comp_unaggr(sc, bf);
1646 __stats(sc, tx_compaggr);
1648 asf_tailq_init(&bf_q);
1650 seq_st = ATH_DS_BA_SEQ(ds);
1651 ba = ATH_DS_BA_BITMAP(ds);
1652 tx_ok = (ATH_DS_TX_STATUS(ds) == HAL_OK);
1654 if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
1655 ath_tx_comp_aggr_error(sc, bf, tid);
1659 if (tx_ok && !ATH_DS_TX_BA(ds)) {
1660 __stats(sc, txaggr_babug);
1661 adf_os_print("BA Bug?\n");
1662 ath_tx_comp_aggr_error(sc, bf, tid);
1667 ba_index = ATH_BA_INDEX(seq_st, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1668 bf_next = bf->bf_next;
1670 if (tx_ok && ATH_BA_ISSET(ba, ba_index)) {
1671 __stats(sc, txaggr_compgood);
1672 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1673 ath_tx_status_update_aggr(sc, bf, ds, rcs, 1);
1674 ath_tx_freebuf(sc, bf);
1676 ath_tx_retry_subframe(sc, bf, &bf_q, &bar);
1682 ath_update_aggr_stats(sc, ds, nframes, nbad);
1683 ath_rate_tx_complete(sc, an, ds, rcs, nframes, nbad);
1686 ath_bar_tx(sc, tid, bar);
1689 if (!asf_tailq_empty(&bf_q)) {
1690 __stats(sc, txaggr_prepends);
1691 TAILQ_INSERTQ_HEAD(&tid->buf_q, &bf_q, bf_list);
1692 ath_tgt_tx_enqueue(txq, tid);
1697 ath_tx_comp_aggr_error(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
1702 struct ath_tx_desc lastds;
1703 struct ath_tx_desc *ds = &lastds;
1704 struct ath_rc_series rcs[4];
1705 struct ath_tx_buf *bar = NULL;
1706 struct ath_tx_buf *bf_next;
1707 int nframes = bf->bf_nframes;
1708 ath_tx_bufhead bf_q;
1709 struct ath_txq *txq;
1711 asf_tailq_init(&bf_q);
1714 adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
1715 adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
1718 bf_next = bf->bf_next;
1719 ath_tx_retry_subframe(sc, bf, &bf_q, &bar);
1723 ath_update_aggr_stats(sc, ds, nframes, nframes);
1724 ath_rate_tx_complete(sc, tid->an, ds, rcs, nframes, nframes);
1727 ath_bar_tx(sc, tid, bar);
1730 if (!asf_tailq_empty(&bf_q)) {
1731 __stats(sc, txaggr_prepends);
1732 TAILQ_INSERTQ_HEAD(&tid->buf_q, &bf_q, bf_list);
1733 ath_tgt_tx_enqueue(txq, tid);
1738 ath_tx_comp_cleanup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1741 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1742 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1743 struct ath_tx_desc lastds;
1744 struct ath_tx_desc *ds = &lastds;
1745 struct ath_rc_series rcs[4];
1750 int nframes = bf->bf_nframes;
1751 struct ath_tx_buf *bf_next;
1754 adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
1755 adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
1757 seq_st = ATH_DS_BA_SEQ(ds);
1758 ba = ATH_DS_BA_BITMAP(ds);
1759 tx_ok = (ATH_DS_TX_STATUS(ds) == HAL_OK);
1761 if (!bf->bf_isaggr) {
1762 ath_update_stats(sc, bf);
1764 __stats(sc, tx_compunaggr);
1766 ath_tx_status_update(sc, bf);
1768 ath_tx_freebuf(sc, bf);
1770 if (tid->flag & TID_CLEANUP_INPROGRES) {
1771 owl_tgt_tid_cleanup(sc, tid);
1779 ba_index = ATH_BA_INDEX(seq_st, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1780 bf_next = bf->bf_next;
1782 ath_tx_status_update_aggr(sc, bf, ds, rcs, 0);
1784 ath_tx_freebuf(sc, bf);
1788 tid->flag &= ~TID_CLEANUP_INPROGRES;
1789 ath_aggr_resume_tid(sc, tid);
1796 ath_update_aggr_stats(sc, ds, nframes, nbad);
1797 ath_rate_tx_complete(sc, an, ds, rcs, nframes, nbad);
1801 ath_tx_retry_subframe(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
1802 ath_tx_bufhead *bf_q, struct ath_tx_buf **bar)
1805 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1806 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1807 struct ath_tx_desc *ds = NULL;
1808 struct ath_hal *ah = sc->sc_ah;
1811 __stats(sc, txaggr_compretries);
1813 for(ds = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; ds++, i++) {
1814 ah->ah_clr11nAggr(ah, ds);
1815 ah->ah_set11nBurstDuration(ah, ds, 0);
1816 ath_hal_set11n_virtualmorefrag(sc->sc_ah, ds, 0);
1819 if (bf->bf_retries >= OWLMAX_RETRIES) {
1820 __stats(sc, txaggr_xretries);
1821 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1822 ath_tx_status_update_aggr(sc, bf, bf->bf_lastds, NULL, 0);
1827 ath_tx_freebuf(sc, bf);
1832 __stats(sc, txaggr_errlast);
1833 bf = ath_buf_toggle(sc, bf, 1);
1835 bf->bf_lastds = &(bf->bf_descarr[bf->bf_dmamap_info.nsegs - 1]);
1837 ath_tx_set_retry(sc, bf);
1838 asf_tailq_insert_tail(bf_q, bf, bf_list);
1842 ath_update_aggr_stats(struct ath_softc_tgt *sc,
1843 struct ath_tx_desc *ds, int nframes,
1847 u_int8_t status = ATH_DS_TX_STATUS(ds);
1848 u_int8_t txflags = ATH_DS_TX_FLAGS(ds);
1850 __statsn(sc, txaggr_longretries, ds->ds_txstat.ts_longretry);
1851 __statsn(sc, txaggr_shortretries, ds->ds_txstat.ts_shortretry);
1853 if (txflags & HAL_TX_DESC_CFG_ERR)
1854 __stats(sc, txaggr_desc_cfgerr);
1856 if (txflags & HAL_TX_DATA_UNDERRUN)
1857 __stats(sc, txaggr_data_urun);
1859 if (txflags & HAL_TX_DELIM_UNDERRUN)
1860 __stats(sc, txaggr_delim_urun);
1866 if (status & HAL_TXERR_XRETRY)
1867 __stats(sc, txaggr_compxretry);
1869 if (status & HAL_TXERR_FILT)
1870 __stats(sc, txaggr_filtered);
1872 if (status & HAL_TXERR_FIFO)
1873 __stats(sc, txaggr_fifo);
1875 if (status & HAL_TXERR_XTXOP)
1876 __stats(sc, txaggr_xtxop);
1878 if (status & HAL_TXERR_TIMER_EXPIRED)
1879 __stats(sc, txaggr_timer_exp);
1883 ath_tx_comp_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1885 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1886 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1887 struct ath_tx_desc *ds = bf->bf_lastds;
1889 ath_update_stats(sc, bf);
1890 ath_rate_tx_complete(sc, an, ds, bf->bf_rcs, 1, 0);
1892 if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
1893 ath_tx_retry_unaggr(sc, bf);
1896 __stats(sc, tx_compunaggr);
1898 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1899 ath_tx_status_update(sc, bf);
1900 ath_tx_freebuf(sc, bf);
1904 ath_tx_retry_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1906 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1907 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1908 struct ath_txq *txq;
1912 if (bf->bf_retries >= OWLMAX_RETRIES) {
1913 __stats(sc, txunaggr_xretry);
1914 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1915 ath_tx_status_update(sc, bf);
1916 ath_bar_tx(sc, tid, bf);
1920 __stats(sc, txunaggr_compretries);
1921 if (!bf->bf_lastds->ds_link) {
1922 __stats(sc, txunaggr_errlast);
1923 bf = ath_buf_toggle(sc, bf, 1);
1926 ath_tx_set_retry(sc, bf);
1927 asf_tailq_insert_head(&tid->buf_q, bf, bf_list);
1928 ath_tgt_tx_enqueue(txq, tid);
1932 ath_tx_update_baw(ath_atx_tid_t *tid, int seqno)
1937 index = ATH_BA_INDEX(tid->seq_start, seqno);
1938 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1940 TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, cindex);
1942 while (tid->baw_head != tid->baw_tail &&
1943 (!TX_BUF_BITMAP_IS_SET(tid->tx_buf_bitmap, tid->baw_head))) {
1944 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1945 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
1949 static void ath_tx_set_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1951 struct ieee80211_frame *wh;
1953 __stats(sc, txaggr_retries);
1955 bf->bf_isretried = 1;
1957 wh = ATH_SKB_2_WH(bf->bf_skb);
1958 wh->i_fc[1] |= IEEE80211_FC1_RETRY;
1961 void ath_tgt_tx_cleanup(struct ath_softc_tgt *sc, struct ath_node_target *an,
1962 ath_atx_tid_t *tid, a_uint8_t discard_all)
1964 struct ath_tx_buf *bf;
1965 struct ath_tx_buf *bf_next;
1966 struct ath_txq *txq;
1968 txq = TID_TO_ACTXQ(tid->tidno);
1970 bf = asf_tailq_first(&tid->buf_q);
1973 if (discard_all || bf->bf_isretried) {
1974 bf_next = asf_tailq_next(bf, bf_list);
1975 TAILQ_DEQ(&tid->buf_q, bf, bf_list);
1976 if (bf->bf_isretried)
1977 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1978 ath_tx_freebuf(sc, bf);
1982 bf->bf_comp = ath_tgt_tx_comp_normal;
1983 bf = asf_tailq_next(bf, bf_list);
1986 ath_aggr_pause_tid(sc, tid);
1988 while (tid->baw_head != tid->baw_tail) {
1989 if (TX_BUF_BITMAP_IS_SET(tid->tx_buf_bitmap, tid->baw_head)) {
1991 tid->flag |= TID_CLEANUP_INPROGRES;
1992 TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, tid->baw_head);
1994 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
1995 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1998 if (!(tid->flag & TID_CLEANUP_INPROGRES)) {
1999 ath_aggr_resume_tid(sc, tid);
2003 /******************/
2004 /* BAR Management */
2005 /******************/
2007 static void ath_tgt_delba_send(struct ath_softc_tgt *sc,
2008 struct ieee80211_node_target *ni,
2009 a_uint8_t tidno, a_uint8_t initiator,
2010 a_uint16_t reasoncode)
2012 struct ath_node_target *an = ATH_NODE_TARGET(ni);
2013 ath_atx_tid_t *tid = ATH_AN_2_TID(an, tidno);
2014 struct wmi_data_delba wmi_delba;
2016 tid->flag &= ~TID_AGGR_ENABLED;
2018 ath_tgt_tx_cleanup(sc, an, tid, 1);
2020 wmi_delba.ni_nodeindex = ni->ni_nodeindex;
2021 wmi_delba.tidno = tid->tidno;
2022 wmi_delba.initiator = 1;
2023 wmi_delba.reasoncode = IEEE80211_REASON_UNSPECIFIED;
2025 __stats(sc, txbar_xretry);
2026 wmi_event(sc->tgt_wmi_handle,
2032 static void ath_bar_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
2034 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
2035 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
2037 if (bf->bf_retries >= OWLMAX_BAR_RETRIES) {
2038 ath_tgt_delba_send(sc, bf->bf_node, tid->tidno, 1,
2039 IEEE80211_REASON_UNSPECIFIED);
2040 ath_tgt_tid_drain(sc, tid);
2043 ath_buf_comp(sc, bf);
2047 __stats(sc, txbar_compretries);
2049 if (!bf->bf_lastds->ds_link) {
2050 __stats(sc, txbar_errlast);
2051 bf = ath_buf_toggle(sc, bf, 1);
2054 bf->bf_lastds->ds_link = 0;
2056 ath_tx_set_retry(sc, bf);
2057 ath_tgt_txq_add_ucast(sc, bf);
2060 static void ath_bar_tx_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
2062 struct ath_tx_desc *ds = bf->bf_lastds;
2063 struct ath_node_target *an;
2065 struct ath_txq *txq;
2067 an = (struct ath_node_target *)bf->bf_node;
2068 tid = &an->tid[bf->bf_tidno];
2069 txq = TID_TO_ACTXQ(tid->tidno);
2071 if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
2072 ath_bar_retry(sc, bf);
2076 ath_aggr_resume_tid(sc, tid);
2079 ath_buf_comp(sc, bf);
2082 static void ath_bar_tx(struct ath_softc_tgt *sc,
2083 ath_atx_tid_t *tid, struct ath_tx_buf *bf)
2086 struct ieee80211_frame_bar *bar;
2088 struct ath_tx_desc *ds, *ds0;
2089 struct ath_hal *ah = sc->sc_ah;
2090 HAL_11N_RATE_SERIES series[4];
2092 adf_nbuf_queue_t skbhead;
2096 __stats(sc, tx_bars);
2098 adf_os_mem_set(&series, 0, sizeof(series));
2100 ath_aggr_pause_tid(sc, tid);
2102 skb = adf_nbuf_queue_remove(&bf->bf_skbhead);
2103 adf_nbuf_peek_header(skb, &anbdata, &anblen);
2104 adf_nbuf_trim_tail(skb, anblen);
2105 bar = (struct ieee80211_frame_bar *) anbdata;
2109 ath_dma_unmap(sc, bf);
2110 adf_nbuf_queue_add(&bf->bf_skbhead, skb);
2112 bar->i_fc[1] = IEEE80211_FC1_DIR_NODS;
2113 bar->i_fc[0] = IEEE80211_FC0_VERSION_0 |
2114 IEEE80211_FC0_TYPE_CTL |
2115 IEEE80211_FC0_SUBTYPE_BAR;
2116 bar->i_ctl = tid->tidno << IEEE80211_BAR_CTL_TID_S |
2117 IEEE80211_BAR_CTL_COMBA;
2118 bar->i_seq = adf_os_cpu_to_le16(tid->seq_start << IEEE80211_SEQ_SEQ_SHIFT);
2120 bf->bf_seqno = tid->seq_start << IEEE80211_SEQ_SEQ_SHIFT;
2122 adf_nbuf_put_tail(skb, sizeof(struct ieee80211_frame_bar));
2124 bf->bf_comp = ath_bar_tx_comp;
2125 bf->bf_tidno = tid->tidno;
2126 bf->bf_node = &tid->an->ni;
2127 ath_dma_map(sc, bf);
2128 adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info);
2131 ah->ah_setupTxDesc(ah, ds
2132 , adf_nbuf_len(skb) + IEEE80211_CRC_LEN
2134 , HAL_PKT_TYPE_NORMAL
2141 | HAL_TXDESC_CLRDMASK
2143 , ATH_COMP_PROC_NO_COMP_NO_CCS);
2145 skbhead = bf->bf_skbhead;
2149 for (ds0 = ds, i=0; i < bf->bf_dmamap_info.nsegs; ds0++, i++) {
2150 ah->ah_clr11nAggr(ah, ds0);
2153 ath_filltxdesc(sc, bf);
2155 for (i = 0 ; i < 4; i++) {
2156 series[i].Tries = ATH_TXMAXTRY;
2157 series[i].Rate = min_rate;
2158 series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
2161 ah->ah_set11nRateScenario(ah, bf->bf_desc, 0, 0, 0, series, 4, 4);
2162 ath_tgt_txq_add_ucast(sc, bf);