2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <adf_os_types.h>
37 #include <adf_os_pci.h>
38 #include <adf_os_dma.h>
39 #include <adf_os_timer.h>
40 #include <adf_os_lock.h>
41 #include <adf_os_io.h>
42 #include <adf_os_mem.h>
43 #include <adf_os_util.h>
44 #include <adf_os_stdtypes.h>
45 #include <adf_os_defer.h>
46 #include <adf_os_atomic.h>
49 #include <adf_net_wcmd.h>
50 #include <adf_os_irq.h>
52 #include <if_ath_pci.h>
54 #include "ieee80211_var.h"
55 #include "if_athrate.h"
56 #include "if_athvar.h"
60 #include "ah_internal.h"
62 static a_int32_t ath_numrxbufs = -1;
63 static a_int32_t ath_numrxdescs = -1;
65 #if defined(PROJECT_MAGPIE)
66 uint32_t *init_htc_handle = 0;
69 #define RX_ENDPOINT_ID 3
70 #define ATH_CABQ_HANDLING_THRESHOLD 9000
74 void owl_tgt_tx_tasklet(TQUEUE_ARG data);
75 static void ath_tgt_send_beacon(struct ath_softc_tgt *sc,adf_nbuf_t bc_hdr,adf_nbuf_t nbuf,HTC_ENDPOINT_ID EndPt);
76 static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen);
77 static void ath_hal_reg_rmw_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen);
78 extern struct ath_tx_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc, adf_nbuf_t skb, ath_data_hdr_t *dh);
79 extern void ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t mgt_hdr, adf_nbuf_t skb,HTC_ENDPOINT_ID EndPt);
80 extern HAL_BOOL ath_hal_wait(struct ath_hal *ah, a_uint32_t reg, a_uint32_t mask, a_uint32_t val);
81 extern void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq, owl_txq_state_t txqstate);
82 void owl_tgt_node_init(struct ath_node_target * an);
83 void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, struct ath_buf *bf);
84 void ath_tgt_tx_sched_nonaggr(struct ath_softc_tgt *sc,struct ath_buf * bf_host);
87 * Extend a 32 bit TSF to nearest 64 bit TSF value.
88 * When the adapter is a STATION, its local TSF is periodically modified by
89 * the hardware to match the BSS TSF (as received in beacon packets), and
90 * rstamp may appear to be from the future or from the past (with reference
91 * to the current local TSF) because of jitter. This is mostly noticable in
92 * highly congested channels. The code uses signed modulo arithmetic to
93 * handle both past/future cases and signed-extension to avoid branches.
95 * extend(0x0000001200000004, 0x00000006) == 0x0000001200000006
96 * extend(0x0000001200000004, 0x00000002) == 0x0000001200000002
97 * extend(0x0000001200000004, 0xfffffffe) == 0x00000011fffffffe ! tsfhigh--
98 * extend(0x000000127ffffffe, 0x80000002) == 0x0000001280000002
99 * extend(0x0000001280000002, 0x7ffffffe) == 0x000000127ffffffe
100 * extend(0x00000012fffffffc, 0xfffffffe) == 0x00000012fffffffe
101 * extend(0x00000012fffffffc, 0xfffffffa) == 0x00000012fffffffa
102 * extend(0x00000012fffffffc, 0x00000002) == 0x0000001300000002 ! tsfhigh++
104 static u_int64_t ath_extend_tsf(struct ath_softc_tgt *sc, u_int32_t rstamp)
106 struct ath_hal *ah = sc->sc_ah;
109 a_int64_t tsf_delta; /* signed int64 */
111 tsf = ah->ah_getTsf64(ah);
112 tsf_low = tsf & 0xffffffffUL;
114 tsf_delta = (a_int32_t)((rstamp - tsf_low) & 0xffffffffUL);
116 return (tsf + (u_int64_t)tsf_delta);
119 static a_int32_t ath_rate_setup(struct ath_softc_tgt *sc, a_uint32_t mode)
121 struct ath_hal *ah = sc->sc_ah;
122 const HAL_RATE_TABLE *rt;
125 case IEEE80211_MODE_11NA:
126 sc->sc_rates[mode] = ah->ah_getRateTable(ah, HAL_MODE_11NA);
128 case IEEE80211_MODE_11NG:
129 sc->sc_rates[mode] = ah->ah_getRateTable(ah, HAL_MODE_11NG);
134 rt = sc->sc_rates[mode];
141 static void ath_setcurmode(struct ath_softc_tgt *sc,
142 enum ieee80211_phymode mode)
144 const HAL_RATE_TABLE *rt;
147 adf_os_mem_set(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
149 rt = sc->sc_rates[mode];
150 adf_os_assert(rt != NULL);
152 for (i = 0; i < rt->rateCount; i++) {
153 sc->sc_rixmap[rt->info[i].rateCode] = i;
156 sc->sc_currates = rt;
157 sc->sc_curmode = mode;
158 sc->sc_protrix = ((mode == IEEE80211_MODE_11NG) ? 3 : 0);
162 void wmi_event(wmi_handle_t handle, WMI_EVENT_ID evt_id,
163 void *buffer, a_int32_t Length)
165 adf_nbuf_t netbuf = ADF_NBUF_NULL;
168 netbuf = WMI_AllocEvent(handle, WMI_EVT_CLASS_CMD_EVENT,
169 sizeof(WMI_CMD_HDR) + Length);
171 if (netbuf == ADF_NBUF_NULL) {
172 adf_os_print("Buf null\n");
176 if (buffer != NULL && Length != 0 && Length < WMI_SVC_MAX_BUFFERED_EVENT_SIZE) {
177 pData = adf_nbuf_put_tail(netbuf, Length);
178 adf_os_mem_copy(pData, buffer, Length);
181 WMI_SendEvent(handle, netbuf, evt_id, 0, Length);
184 void wmi_cmd_rsp(void *pContext, WMI_COMMAND_ID cmd_id, A_UINT16 SeqNo,
185 void *buffer, a_int32_t Length)
187 adf_nbuf_t netbuf = ADF_NBUF_NULL;
190 netbuf = WMI_AllocEvent(pContext, WMI_EVT_CLASS_CMD_REPLY,
191 sizeof(WMI_CMD_HDR) + Length);
193 if (netbuf == ADF_NBUF_NULL) {
198 if (Length != 0 && buffer != NULL) {
199 pData = (A_UINT8 *)adf_nbuf_put_tail(netbuf, Length);
200 adf_os_mem_copy(pData, buffer, Length);
203 WMI_SendEvent(pContext, netbuf, cmd_id, SeqNo, Length);
206 static void ath_node_vdelete_tgt(struct ath_softc_tgt *sc, a_uint8_t vap_index)
210 for (i = 0; i < TARGET_NODE_MAX; i++) {
211 if(sc->sc_sta[i].ni.ni_vapindex == vap_index)
212 sc->sc_sta[i].an_valid = 0;
216 a_uint8_t ath_get_minrateidx(struct ath_softc_tgt *sc, struct ath_vap_target *avp)
218 if (sc->sc_curmode == IEEE80211_MODE_11NG)
219 return avp->av_minrateidx[0];
220 else if (sc->sc_curmode == IEEE80211_MODE_11NA)
221 return avp->av_minrateidx[1];
230 static adf_nbuf_t ath_alloc_skb_align(struct ath_softc_tgt *sc,
231 a_uint32_t size, a_uint32_t align)
235 skb = BUF_Pool_alloc_buf_align(sc->pool_handle, POOL_ID_WLAN_RX_BUF,
236 RX_HEADER_SPACE, align);
240 static a_int32_t ath_rxdesc_init(struct ath_softc_tgt *sc, struct ath_rx_desc *ds)
242 struct ath_hal *ah = sc->sc_ah;
243 struct ath_rx_desc *ds_held;
247 if (!sc->sc_rxdesc_held) {
248 sc->sc_rxdesc_held = ds;
252 ds_held = sc->sc_rxdesc_held;
253 sc->sc_rxdesc_held = ds;
256 if (ds->ds_nbuf == ADF_NBUF_NULL) {
257 ds->ds_nbuf = ath_alloc_skb_align(sc, sc->sc_rxbufsize, sc->sc_cachelsz);
258 if (ds->ds_nbuf == ADF_NBUF_NULL) {
259 sc->sc_rxdesc_held = ds;
260 sc->sc_rx_stats.ast_rx_nobuf++;
263 adf_nbuf_map(sc->sc_dev, ds->ds_dmap, ds->ds_nbuf, ADF_OS_DMA_FROM_DEVICE);
264 adf_nbuf_dmamap_info(ds->ds_dmap, &ds->ds_dmap_info);
265 ds->ds_data = ds->ds_dmap_info.dma_segs[0].paddr;
269 adf_nbuf_peek_header(ds->ds_nbuf, &anbdata, &anblen);
271 ah->ah_setupRxDesc(ds, adf_nbuf_tailroom(ds->ds_nbuf), 0);
273 if (sc->sc_rxlink == NULL) {
274 ah->ah_setRxDP(ah, ds->ds_daddr);
277 *sc->sc_rxlink = ds->ds_daddr;
279 sc->sc_rxlink = &ds->ds_link;
280 ah->ah_enableReceive(ah);
285 static void ath_rx_complete(struct ath_softc_tgt *sc, adf_nbuf_t buf)
287 struct ath_rx_desc *ds;
289 adf_nbuf_queue_t nbuf_head;
291 adf_nbuf_split_to_frag(buf, &nbuf_head);
292 ds = asf_tailq_first(&sc->sc_rxdesc_idle);
295 struct ath_rx_desc *ds_tmp;
296 buf_tmp = adf_nbuf_queue_remove(&nbuf_head);
298 if (buf_tmp == NULL) {
302 BUF_Pool_free_buf(sc->pool_handle, POOL_ID_WLAN_RX_BUF, buf_tmp);
305 ds = asf_tailq_next(ds, ds_list);
307 ath_rxdesc_init(sc, ds_tmp);
309 asf_tailq_remove(&sc->sc_rxdesc_idle, ds_tmp, ds_list);
310 asf_tailq_insert_tail(&sc->sc_rxdesc, ds_tmp, ds_list);
314 static void tgt_HTCSendCompleteHandler(HTC_ENDPOINT_ID Endpt, adf_nbuf_t buf, void *ServiceCtx)
316 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
318 if (Endpt == RX_ENDPOINT_ID) {
319 sc->sc_rx_stats.ast_rx_done++;
320 ath_rx_complete(sc, buf);
324 static void ath_uapsd_processtriggers(struct ath_softc_tgt *sc)
326 struct ath_hal *ah = sc->sc_ah;
327 struct ath_rx_buf *bf = NULL;
328 struct ath_rx_desc *ds, *ds_head, *ds_tail, *ds_tmp;
331 a_uint16_t frame_len = 0;
333 #define PA2DESC(_sc, _pa) \
334 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
335 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
337 bf = asf_tailq_first(&sc->sc_rxbuf);
339 ds = asf_tailq_first(&sc->sc_rxdesc);
345 if (cnt == ath_numrxbufs - 1) {
346 adf_os_print("VERY LONG PACKET!!!!!\n");
350 struct ath_rx_desc *ds_rmv;
351 adf_nbuf_unmap(sc->sc_dev, ds_tmp->ds_dmap, ADF_OS_DMA_FROM_DEVICE);
353 ds_tmp = asf_tailq_next(ds_tmp, ds_list);
355 if (ds_tmp == NULL) {
356 adf_os_print("ds_tmp is NULL\n");
360 BUF_Pool_free_buf(sc->pool_handle, POOL_ID_WLAN_RX_BUF, ds_rmv->ds_nbuf);
361 ds_rmv->ds_nbuf = ADF_NBUF_NULL;
363 if (ath_rxdesc_init(sc, ds_rmv) == 0) {
364 asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
365 asf_tailq_insert_tail(&sc->sc_rxdesc, ds_rmv, ds_list);
368 asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
369 asf_tailq_insert_tail(&sc->sc_rxdesc_idle, ds_rmv, ds_list);
372 if (ds_rmv == ds_tail) {
379 if (ds->ds_link == 0) {
383 if (bf->bf_status & ATH_BUFSTATUS_DONE) {
387 retval = ah->ah_procRxDescFast(ah, ds, ds->ds_daddr,
388 PA2DESC(sc, ds->ds_link), &bf->bf_rx_status);
389 if (HAL_EINPROGRESS == retval) {
393 if (adf_nbuf_len(ds->ds_nbuf) == 0) {
394 adf_nbuf_put_tail(ds->ds_nbuf, bf->bf_rx_status.rs_datalen);
397 frame_len += bf->bf_rx_status.rs_datalen;
399 if (bf->bf_rx_status.rs_more == 0) {
400 adf_nbuf_queue_t nbuf_head;
401 adf_nbuf_queue_init(&nbuf_head);
406 ds = asf_tailq_next(ds, ds_list);
409 ds_head = asf_tailq_next(ds_tail, ds_list);
412 struct ath_rx_desc *ds_rmv;
414 adf_nbuf_unmap(sc->sc_dev, ds_tmp->ds_dmap, ADF_OS_DMA_FROM_DEVICE);
415 adf_nbuf_queue_add(&nbuf_head, ds_tmp->ds_nbuf);
416 ds_tmp->ds_nbuf = ADF_NBUF_NULL;
419 ds_tmp = asf_tailq_next(ds_tmp, ds_list);
420 if (ds_tmp == NULL) {
424 if (ath_rxdesc_init(sc, ds_rmv) == 0) {
425 asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
426 asf_tailq_insert_tail(&sc->sc_rxdesc, ds_rmv, ds_list);
428 asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
429 asf_tailq_insert_tail(&sc->sc_rxdesc_idle, ds_rmv, ds_list);
432 if (ds_rmv == ds_tail) {
438 bf->bf_rx_status.rs_datalen = frame_len;
441 bf->bf_skb = adf_nbuf_create_frm_frag(&nbuf_head);
443 bf->bf_status |= ATH_BUFSTATUS_DONE;
445 bf = (struct ath_rx_buf *)asf_tailq_next(bf, bf_list);
448 ds = asf_tailq_next(ds, ds_list);
455 static a_int32_t ath_startrecv(struct ath_softc_tgt *sc)
457 struct ath_hal *ah = sc->sc_ah;
458 struct ath_rx_desc *ds;
460 sc->sc_rxbufsize = 1024+512+128;
461 sc->sc_rxlink = NULL;
463 sc->sc_rxdesc_held = NULL;
465 asf_tailq_foreach(ds, &sc->sc_rxdesc, ds_list) {
466 a_int32_t error = ath_rxdesc_init(sc, ds);
472 ds = asf_tailq_first(&sc->sc_rxdesc);
473 ah->ah_setRxDP(ah, ds->ds_daddr);
478 static void ath_tgt_rx_tasklet(TQUEUE_ARG data)
480 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
481 struct ath_rx_buf *bf = NULL;
482 struct ath_hal *ah = sc->sc_ah;
483 struct rx_frame_header *rxhdr;
484 struct ath_rx_status *rxstats;
485 adf_nbuf_t skb = ADF_NBUF_NULL;
488 bf = asf_tailq_first(&sc->sc_rxbuf);
493 if (!(bf->bf_status & ATH_BUFSTATUS_DONE)) {
502 asf_tailq_remove(&sc->sc_rxbuf, bf, bf_list);
506 rxhdr = (struct rx_frame_header *)adf_nbuf_push_head(skb,
507 sizeof(struct rx_frame_header));
508 rxstats = (struct ath_rx_status *)(&rxhdr->rx_stats[0]);
509 adf_os_mem_copy(rxstats, &(bf->bf_rx_status),
510 sizeof(struct ath_rx_status));
512 rxstats->rs_tstamp = ath_extend_tsf(sc, (u_int32_t)rxstats->rs_tstamp);
514 HTC_SendMsg(sc->tgt_htc_handle, RX_ENDPOINT_ID, skb);
515 sc->sc_rx_stats.ast_rx_send++;
517 bf->bf_status &= ~ATH_BUFSTATUS_DONE;
518 asf_tailq_insert_tail(&sc->sc_rxbuf, bf, bf_list);
522 sc->sc_imask |= HAL_INT_RX;
523 ah->ah_setInterrupts(ah, sc->sc_imask);
526 /*******************/
527 /* Beacon Handling */
528 /*******************/
531 * Setup the beacon frame for transmit.
532 * FIXME: Short Preamble.
534 static void ath_beacon_setup(struct ath_softc_tgt *sc,
535 struct ath_tx_buf *bf,
536 struct ath_vap_target *avp)
538 adf_nbuf_t skb = bf->bf_skb;
539 struct ath_hal *ah = sc->sc_ah;
540 struct ath_tx_desc *ds;
542 const HAL_RATE_TABLE *rt;
544 HAL_11N_RATE_SERIES series[4] = {{ 0 }};
546 flags = HAL_TXDESC_NOACK;
550 ds->ds_data = bf->bf_dmamap_info.dma_segs[0].paddr;
552 rix = ath_get_minrateidx(sc, avp);
553 rt = sc->sc_currates;
554 rate = rt->info[rix].rateCode;
556 ah->ah_setupTxDesc(ds
557 , adf_nbuf_len(skb) + IEEE80211_CRC_LEN
558 , sizeof(struct ieee80211_frame)
559 , HAL_PKT_TYPE_BEACON
562 , HAL_TXKEYIX_INVALID
568 , asf_roundup(adf_nbuf_len(skb), 4)
574 series[0].Rate = rate;
575 series[0].ChSel = sc->sc_ic.ic_tx_chainmask;
576 series[0].RateFlags = 0;
577 ah->ah_set11nRateScenario(ds, 0, 0, series, 4, 0);
580 static void ath_tgt_send_beacon(struct ath_softc_tgt *sc, adf_nbuf_t bc_hdr,
581 adf_nbuf_t nbuf, HTC_ENDPOINT_ID EndPt)
583 struct ath_hal *ah = sc->sc_ah;
584 struct ath_tx_buf *bf;
585 a_uint8_t vap_index, *anbdata;
586 ath_beacon_hdr_t *bhdr;
590 adf_nbuf_peek_header(nbuf, &anbdata, &anblen);
591 bhdr = (ath_beacon_hdr_t *)anbdata;
593 adf_os_print("found bc_hdr! 0x%x\n", bc_hdr);
596 vap_index = bhdr->vap_index;
597 adf_os_assert(vap_index < TARGET_VAP_MAX);
599 adf_nbuf_pull_head(nbuf, sizeof(ath_beacon_hdr_t));
601 bf = sc->sc_vap[vap_index].av_bcbuf;
603 bf->bf_endpt = EndPt;
606 adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, ADF_OS_DMA_TO_DEVICE);
607 adf_nbuf_push_head(bf->bf_skb, sizeof(ath_beacon_hdr_t));
608 ath_free_tx_skb(sc->tgt_htc_handle, bf->bf_endpt, bf->bf_skb);
613 adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, nbuf, ADF_OS_DMA_TO_DEVICE);
614 adf_nbuf_dmamap_info(bf->bf_dmamap,&bf->bf_dmamap_info);
616 ath_beacon_setup(sc, bf, &sc->sc_vap[vap_index]);
617 ah->ah_stopTxDma(ah, sc->sc_bhalq);
618 ah->ah_setTxDP(ah, sc->sc_bhalq, ATH_BUF_GET_DESC_PHY_ADDR(bf));
619 ah->ah_startTxDma(ah, sc->sc_bhalq);
626 static void ath_tx_stopdma(struct ath_softc_tgt *sc, struct ath_txq *txq)
628 struct ath_hal *ah = sc->sc_ah;
630 ah->ah_stopTxDma(ah, txq->axq_qnum);
633 static void owltgt_txq_drain(struct ath_softc_tgt *sc, struct ath_txq *txq)
635 owltgt_tx_processq(sc, txq, OWL_TXQ_STOPPED);
638 static void ath_tx_draintxq(struct ath_softc_tgt *sc, struct ath_txq *txq)
640 owltgt_txq_drain(sc, txq);
643 static void ath_draintxq(struct ath_softc_tgt *sc, HAL_BOOL drain_softq)
645 struct ath_hal *ah = sc->sc_ah;
647 struct ath_txq *txq = NULL;
648 struct ath_atx_tid *tid = NULL;
650 ath_tx_status_clear(sc);
651 sc->sc_tx_draining = 1;
653 ah->ah_stopTxDma(ah, sc->sc_bhalq);
655 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
656 if (ATH_TXQ_SETUP(sc, i))
657 ath_tx_stopdma(sc, ATH_TXQ(sc, i));
659 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
660 if (ATH_TXQ_SETUP(sc, i)) {
661 owltgt_tx_processq(sc, ATH_TXQ(sc,i), OWL_TXQ_STOPPED);
664 while (!asf_tailq_empty(&txq->axq_tidq)){
665 TAILQ_DEQ(&txq->axq_tidq, tid, tid_qelem);
668 tid->sched = AH_FALSE;
669 ath_tgt_tid_drain(sc,tid);
673 sc->sc_tx_draining = 0;
676 static void ath_tgt_txq_setup(struct ath_softc_tgt *sc)
683 for (qnum=0;qnum<HAL_NUM_TX_QUEUES;qnum++) {
684 txq= &sc->sc_txq[qnum];
685 txq->axq_qnum = qnum;
686 txq->axq_link = NULL;
687 asf_tailq_init(&txq->axq_q);
689 txq->axq_linkbuf = NULL;
690 asf_tailq_init(&txq->axq_tidq);
691 sc->sc_txqsetup |= 1<<qnum;
694 sc->sc_uapsdq = &sc->sc_txq[UAPSDQ_NUM];
695 sc->sc_cabq = &sc->sc_txq[CABQ_NUM];
697 sc->sc_ac2q[WME_AC_BE] = &sc->sc_txq[0];
698 sc->sc_ac2q[WME_AC_BK] = &sc->sc_txq[1];
699 sc->sc_ac2q[WME_AC_VI] = &sc->sc_txq[2];
700 sc->sc_ac2q[WME_AC_VO] = &sc->sc_txq[3];
706 static void tgt_HTCRecv_beaconhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
707 adf_nbuf_t buf, void *ServiceCtx)
709 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
711 ath_tgt_send_beacon(sc, hdr_buf, buf, EndPt);
714 static void tgt_HTCRecv_uapsdhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
715 adf_nbuf_t buf, void *ServiceCtx)
719 static void tgt_HTCRecv_mgmthandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
720 adf_nbuf_t buf, void *ServiceCtx)
722 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
724 ath_tgt_send_mgt(sc,hdr_buf,buf,EndPt);
727 static void tgt_HTCRecvMessageHandler(HTC_ENDPOINT_ID EndPt,
728 adf_nbuf_t hdr_buf, adf_nbuf_t buf,
731 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
732 struct ath_tx_buf *bf;
736 struct ath_node_target *an;
737 struct ath_atx_tid *tid;
740 adf_nbuf_peek_header(buf, &data, &len);
741 adf_nbuf_pull_head(buf, sizeof(ath_data_hdr_t));
743 adf_nbuf_peek_header(hdr_buf, &data, &len);
746 adf_os_assert(len >= sizeof(ath_data_hdr_t));
747 dh = (ath_data_hdr_t *)data;
749 an = &sc->sc_sta[dh->ni_index];
750 tid = ATH_AN_2_TID(an, dh->tidno);
752 sc->sc_tx_stats.tx_tgt++;
754 bf = ath_tgt_tx_prepare(sc, buf, dh);
756 ath_free_tx_skb(sc->tgt_htc_handle,EndPt,buf);
760 bf->bf_endpt = EndPt;
761 bf->bf_cookie = dh->cookie;
763 if (tid->flag & TID_AGGR_ENABLED)
764 ath_tgt_handle_aggr(sc, bf);
766 ath_tgt_handle_normal(sc, bf);
769 static void tgt_HTCRecv_cabhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
770 adf_nbuf_t buf, void *ServiceCtx)
772 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
773 struct ath_hal *ah = sc->sc_ah;
777 #ifdef ATH_ENABLE_CABQ
778 tsf = ah->ah_getTsf64(ah);
779 tmp = tsf - sc->sc_swba_tsf;
781 if ( tmp > ATH_CABQ_HANDLING_THRESHOLD ) {
782 HTC_ReturnBuffers(sc->tgt_htc_handle, EndPt, buf);
786 tgt_HTCRecvMessageHandler(EndPt, hdr_buf, buf, ServiceCtx);
790 /***********************/
791 /* Descriptor Handling */
792 /***********************/
794 static a_int32_t ath_descdma_setup(struct ath_softc_tgt *sc,
795 struct ath_descdma *dd, ath_bufhead *head,
796 const char *name, a_int32_t nbuf, a_int32_t ndesc,
797 a_uint32_t bfSize, a_uint32_t descSize)
799 #define DS2PHYS(_dd, _ds) \
800 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
804 a_int32_t i, bsize, error;
809 dd->dd_desc_len = descSize * nbuf * ndesc;
811 dd->dd_desc = adf_os_dmamem_alloc(sc->sc_dev,
812 dd->dd_desc_len, 1, &dd->dd_desc_dmamap);
813 dd->dd_desc_paddr = adf_os_dmamem_map2addr(dd->dd_desc_dmamap);
814 if (dd->dd_desc == NULL) {
820 bsize = bfSize * nbuf;
821 bf = adf_os_mem_alloc(bsize);
826 adf_os_mem_set(bf, 0, bsize);
829 bf_addr = (a_uint8_t *)bf;
830 ds_addr = (a_uint8_t *)ds;
832 asf_tailq_init(head);
834 for (i = 0; i < nbuf; i++) {
837 if (adf_nbuf_dmamap_create( sc->sc_dev, &bf->bf_dmamap) != A_STATUS_OK) {
841 bf->bf_desc = bf->bf_descarr = bf->bf_lastds = ds;
842 for (j = 0; j < ndesc; j++)
843 ATH_BUF_SET_DESC_PHY_ADDR_WITH_IDX(bf, j, (ds_addr + (j*descSize)));
845 ATH_BUF_SET_DESC_PHY_ADDR(bf, ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, 0));
847 adf_nbuf_queue_init(&bf->bf_skbhead);
848 asf_tailq_insert_tail(head, bf, bf_list);
851 ds_addr += (ndesc * descSize);
852 bf = (struct ath_buf *)bf_addr;
853 ds = (struct ath_desc *)ds_addr;
858 adf_os_dmamem_free(sc->sc_dev, dd->dd_desc_len,
859 1, dd->dd_desc, dd->dd_desc_dmamap);
861 adf_os_mem_set(dd, 0, sizeof(*dd));
868 static void ath_descdma_cleanup(struct ath_softc_tgt *sc,
869 struct ath_descdma *dd,
870 ath_bufhead *head, a_int32_t dir)
874 asf_tailq_foreach(bf, head, bf_list) {
875 if (adf_nbuf_queue_len(&bf->bf_skbhead) != 0) {
876 adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, dir);
877 while(adf_nbuf_queue_len(&bf->bf_skbhead) != 0) {
879 adf_nbuf_queue_remove(&bf->bf_skbhead));
882 } else if (bf->bf_skb != NULL) {
883 adf_nbuf_unmap(sc->sc_dev,bf->bf_dmamap, dir);
884 ath_free_rx_skb(sc, bf->bf_skb);
888 adf_nbuf_dmamap_destroy(sc->sc_dev, bf->bf_dmamap);
893 adf_os_dmamem_free(sc->sc_dev, dd->dd_desc_len,
894 1, dd->dd_desc, dd->dd_desc_dmamap);
896 asf_tailq_init(head);
897 adf_os_mem_free(dd->dd_bufptr);
898 adf_os_mem_set(dd, 0, sizeof(*dd));
901 static a_int32_t ath_desc_alloc(struct ath_softc_tgt *sc)
903 #define DS2PHYS(_dd, _ds) \
904 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
907 struct ath_tx_buf *bf;
909 if(ath_numrxbufs == -1)
910 ath_numrxbufs = ATH_RXBUF;
912 if (ath_numrxdescs == -1)
913 ath_numrxdescs = ATH_RXDESC;
915 error = ath_descdma_setup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
916 "rx", ath_numrxdescs, 1,
917 sizeof(struct ath_rx_buf),
918 sizeof(struct ath_rx_desc));
923 struct ath_descdma *dd = &sc->sc_rxdma;
924 struct ath_rx_desc *ds = (struct ath_rx_desc *)dd->dd_desc;
925 struct ath_rx_desc *ds_prev = NULL;
927 asf_tailq_init(&sc->sc_rxdesc);
928 asf_tailq_init(&sc->sc_rxdesc_idle);
930 for (i = 0; i < ath_numrxdescs; i++, ds++) {
932 if (ds->ds_nbuf != ADF_NBUF_NULL) {
933 ds->ds_nbuf = ADF_NBUF_NULL;
936 if (adf_nbuf_dmamap_create(sc->sc_dev, &ds->ds_dmap) != A_STATUS_OK) {
940 ds->ds_daddr = DS2PHYS(&sc->sc_rxdma, ds);
943 ds_prev->ds_link = ds->ds_daddr;
949 asf_tailq_insert_tail(&sc->sc_rxdesc, ds, ds_list);
952 error = ath_descdma_setup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
953 "tx", ATH_TXBUF + 1, ATH_TXDESC,
954 sizeof(struct ath_tx_buf),
955 sizeof(struct ath_tx_desc));
957 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
958 ADF_OS_DMA_FROM_DEVICE);
962 error = ath_descdma_setup(sc, &sc->sc_bdma, (ath_bufhead *)&sc->sc_bbuf,
963 "beacon", ATH_BCBUF, 1,
964 sizeof(struct ath_tx_buf),
965 sizeof(struct ath_tx_desc));
967 ath_descdma_cleanup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
968 ADF_OS_DMA_TO_DEVICE);
969 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
970 ADF_OS_DMA_FROM_DEVICE);
974 bf = asf_tailq_first(&sc->sc_txbuf);
975 bf->bf_isaggr = bf->bf_isretried = bf->bf_retries = 0;
976 asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
978 sc->sc_txbuf_held = bf;
985 static void ath_desc_free(struct ath_softc_tgt *sc)
987 asf_tailq_insert_tail(&sc->sc_txbuf, sc->sc_txbuf_held, bf_list);
989 sc->sc_txbuf_held = NULL;
991 if (sc->sc_txdma.dd_desc_len != 0)
992 ath_descdma_cleanup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
993 ADF_OS_DMA_TO_DEVICE);
994 if (sc->sc_rxdma.dd_desc_len != 0)
995 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
996 ADF_OS_DMA_FROM_DEVICE);
999 /**********************/
1000 /* Interrupt Handling */
1001 /**********************/
1003 adf_os_irq_resp_t ath_intr(adf_drv_handle_t hdl)
1005 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)hdl;
1006 struct ath_hal *ah = sc->sc_ah;
1010 return ADF_OS_IRQ_NONE;
1012 if (!ah->ah_isInterruptPending(ah))
1013 return ADF_OS_IRQ_NONE;
1015 ah->ah_getPendingInterrupts(ah, &status);
1017 status &= sc->sc_imask;
1019 if (status & HAL_INT_FATAL) {
1020 ah->ah_setInterrupts(ah, 0);
1021 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_fataltq);
1023 if (status & HAL_INT_SWBA) {
1024 WMI_SWBA_EVENT swbaEvt;
1025 struct ath_txq *txq = ATH_TXQ(sc, 8);
1027 swbaEvt.tsf = ah->ah_getTsf64(ah);
1028 swbaEvt.beaconPendingCount = ah->ah_numTxPending(ah, sc->sc_bhalq);
1029 sc->sc_swba_tsf = ah->ah_getTsf64(ah);
1031 wmi_event(sc->tgt_wmi_handle,
1034 sizeof(WMI_SWBA_EVENT));
1036 ath_tx_draintxq(sc, txq);
1039 if (status & HAL_INT_RXORN)
1040 sc->sc_int_stats.ast_rxorn++;
1042 if (status & HAL_INT_RXEOL)
1043 sc->sc_int_stats.ast_rxeol++;
1045 if (status & (HAL_INT_RX | HAL_INT_RXEOL | HAL_INT_RXORN)) {
1046 if (status & HAL_INT_RX)
1047 sc->sc_int_stats.ast_rx++;
1049 ath_uapsd_processtriggers(sc);
1051 sc->sc_imask &= ~HAL_INT_RX;
1052 ah->ah_setInterrupts(ah, sc->sc_imask);
1054 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_rxtq);
1057 if (status & HAL_INT_TXURN) {
1058 sc->sc_int_stats.ast_txurn++;
1059 ah->ah_updateTxTrigLevel(ah, AH_TRUE);
1062 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_txtq);
1064 if (status & HAL_INT_BMISS) {
1065 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_bmisstq);
1068 if (status & HAL_INT_GTT)
1069 sc->sc_int_stats.ast_txto++;
1071 if (status & HAL_INT_CST)
1072 sc->sc_int_stats.ast_cst++;
1075 return ADF_OS_IRQ_HANDLED;
1078 static void ath_fatal_tasklet(TQUEUE_ARG data )
1080 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
1082 wmi_event(sc->tgt_wmi_handle, WMI_FATAL_EVENTID, NULL, 0);
1085 static void ath_bmiss_tasklet(TQUEUE_ARG data)
1087 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
1089 wmi_event(sc->tgt_wmi_handle, WMI_BMISS_EVENTID, NULL, 0);
1096 static void ath_enable_intr_tgt(void *Context, A_UINT16 Command,
1097 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1099 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1100 struct ath_hal *ah = sc->sc_ah;
1104 intr = (*(a_uint32_t *)data);
1106 intr = adf_os_ntohl(intr);
1108 if (intr & HAL_INT_SWBA) {
1109 sc->sc_imask |= HAL_INT_SWBA;
1111 sc->sc_imask &= ~HAL_INT_SWBA;
1114 if (intr & HAL_INT_BMISS) {
1115 sc->sc_imask |= HAL_INT_BMISS;
1118 ah->ah_setInterrupts(ah, sc->sc_imask);
1119 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
1122 static void ath_init_tgt(void *Context, A_UINT16 Command,
1123 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1125 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1126 struct ath_hal *ah = sc->sc_ah;
1128 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
1129 | HAL_INT_RXEOL | HAL_INT_RXORN
1130 | HAL_INT_FATAL | HAL_INT_GLOBAL;
1132 sc->sc_imask |= HAL_INT_GTT;
1134 if (ath_hal_getcapability(ah, HAL_CAP_HT))
1135 sc->sc_imask |= HAL_INT_CST;
1137 adf_os_setup_intr(sc->sc_dev, ath_intr);
1138 ah->ah_setInterrupts(ah, sc->sc_imask);
1140 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1143 static void ath_int_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1144 A_UINT8 *data, a_int32_t datalen)
1146 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1148 struct fusion_stats {
1150 a_uint32_t ast_rxorn;
1151 a_uint32_t ast_rxeol;
1152 a_uint32_t ast_txurn;
1153 a_uint32_t ast_txto;
1157 struct fusion_stats stats;
1159 stats.ast_rx = sc->sc_int_stats.ast_rx;
1160 stats.ast_rxorn = sc->sc_int_stats.ast_rxorn;
1161 stats.ast_rxeol = sc->sc_int_stats.ast_rxeol;
1162 stats.ast_txurn = sc->sc_int_stats.ast_txurn;
1163 stats.ast_txto = sc->sc_int_stats.ast_txto;
1164 stats.ast_cst = sc->sc_int_stats.ast_cst;
1166 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1169 static void ath_tx_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1170 A_UINT8 *data, a_int32_t datalen)
1172 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1174 struct fusion_stats {
1175 a_uint32_t ast_tx_xretries;
1176 a_uint32_t ast_tx_fifoerr;
1177 a_uint32_t ast_tx_filtered;
1178 a_uint32_t ast_tx_timer_exp;
1179 a_uint32_t ast_tx_shortretry;
1180 a_uint32_t ast_tx_longretry;
1182 a_uint32_t tx_qnull;
1183 a_uint32_t tx_noskbs;
1184 a_uint32_t tx_nobufs;
1187 struct fusion_stats stats;
1189 stats.ast_tx_xretries = sc->sc_tx_stats.ast_tx_xretries;
1190 stats.ast_tx_fifoerr = sc->sc_tx_stats.ast_tx_fifoerr;
1191 stats.ast_tx_filtered = sc->sc_tx_stats.ast_tx_filtered;
1192 stats.ast_tx_timer_exp = sc->sc_tx_stats.ast_tx_timer_exp;
1193 stats.ast_tx_shortretry = sc->sc_tx_stats.ast_tx_shortretry;
1194 stats.ast_tx_longretry = sc->sc_tx_stats.ast_tx_longretry;
1195 stats.tx_qnull = sc->sc_tx_stats.tx_qnull;
1196 stats.tx_noskbs = sc->sc_tx_stats.tx_noskbs;
1197 stats.tx_nobufs = sc->sc_tx_stats.tx_nobufs;
1199 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1202 static void ath_rx_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1203 A_UINT8 *data, a_int32_t datalen)
1205 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1207 struct fusion_stats {
1208 a_uint32_t ast_rx_nobuf;
1209 a_uint32_t ast_rx_send;
1210 a_uint32_t ast_rx_done;
1213 struct fusion_stats stats;
1215 stats.ast_rx_nobuf = sc->sc_rx_stats.ast_rx_nobuf;
1216 stats.ast_rx_send = sc->sc_rx_stats.ast_rx_send;
1217 stats.ast_rx_done = sc->sc_rx_stats.ast_rx_done;
1219 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1222 static void ath_get_tgt_version(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1223 A_UINT8 *data, a_int32_t datalen)
1225 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1226 struct wmi_fw_version ver;
1228 ver.major = ATH_VERSION_MAJOR;
1229 ver.minor = ATH_VERSION_MINOR;
1231 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &ver, sizeof(ver));
1234 static void ath_enable_aggr_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1235 A_UINT8 *data, a_int32_t datalen)
1237 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1238 struct ath_aggr_info *aggr = (struct ath_aggr_info *)data;
1239 a_uint8_t nodeindex = aggr->nodeindex;
1240 a_uint8_t tidno = aggr->tidno;
1241 struct ath_node_target *an = NULL ;
1242 struct ath_atx_tid *tid = NULL;
1244 if (nodeindex >= TARGET_NODE_MAX) {
1248 an = &sc->sc_sta[nodeindex];
1249 if (!an->an_valid) {
1253 if (tidno >= WME_NUM_TID) {
1254 adf_os_print("[%s] enable_aggr with invalid tid %d(node = %d)\n",
1255 __FUNCTION__, tidno, nodeindex);
1259 tid = ATH_AN_2_TID(an, tidno);
1261 if (aggr->aggr_enable) {
1262 tid->flag |= TID_AGGR_ENABLED;
1263 } else if ( tid->flag & TID_AGGR_ENABLED ) {
1264 tid->flag &= ~TID_AGGR_ENABLED;
1265 ath_tgt_tx_cleanup(sc, an, tid, 1);
1268 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1271 static void ath_ic_update_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1272 A_UINT8 *data, a_int32_t datalen)
1274 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1275 struct ieee80211com_target *ic = (struct ieee80211com_target * )data;
1276 struct ieee80211com_target *ictgt = &sc->sc_ic ;
1278 adf_os_mem_copy(ictgt, ic, sizeof(struct ieee80211com_target));
1280 ictgt->ic_ampdu_limit = adf_os_ntohl(ic->ic_ampdu_limit);
1282 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1285 static void ath_vap_create_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1286 A_UINT8 *data, a_int32_t datalen)
1288 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1289 struct ieee80211vap_target *vap;
1290 a_uint8_t vap_index;
1292 vap = (struct ieee80211vap_target *)data;
1294 vap->iv_rtsthreshold = adf_os_ntohs(vap->iv_rtsthreshold);
1295 vap->iv_opmode = adf_os_ntohl(vap->iv_opmode);
1297 vap_index = vap->iv_vapindex;
1299 adf_os_assert(sc->sc_vap[vap_index].av_valid == 0);
1301 adf_os_mem_copy(&(sc->sc_vap[vap_index].av_vap), vap,
1304 sc->sc_vap[vap_index].av_bcbuf = asf_tailq_first(&(sc->sc_bbuf));
1305 sc->sc_vap[vap_index].av_valid = 1;
1307 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1310 static void ath_node_create_tgt(void *Context, A_UINT16 Command,
1311 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1313 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1314 struct ieee80211_node_target *node;
1315 a_uint8_t vap_index;
1316 a_uint8_t node_index;
1318 node = (struct ieee80211_node_target *)data;
1320 node_index = node->ni_nodeindex;
1322 node->ni_htcap = adf_os_ntohs(node->ni_htcap);
1323 node->ni_flags = adf_os_ntohs(node->ni_flags);
1324 node->ni_maxampdu = adf_os_ntohs(node->ni_maxampdu);
1326 adf_os_mem_copy(&(sc->sc_sta[node_index].ni), node,
1329 vap_index = sc->sc_sta[node_index].ni.ni_vapindex;
1330 sc->sc_sta[node_index].ni.ni_vap = &(sc->sc_vap[vap_index].av_vap);
1331 if(sc->sc_sta[node_index].ni.ni_is_vapnode == 1)
1332 sc->sc_vap[vap_index].av_vap.iv_nodeindex = node_index;
1334 sc->sc_sta[node_index].an_valid = 1;
1335 sc->sc_sta[node_index].ni.ni_txseqmgmt = 0;
1336 sc->sc_sta[node_index].ni.ni_iv16 = 0;
1337 sc->sc_sta[node_index].ni.ni_iv32 = 0;
1339 owl_tgt_node_init(&sc->sc_sta[node_index]);
1341 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1344 static void ath_node_cleanup_tgt(void *Context, A_UINT16 Command,
1345 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1347 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1348 a_uint8_t node_index;
1349 a_uint8_t *nodedata;
1351 nodedata = (a_uint8_t *)data;
1352 node_index = *nodedata;
1353 sc->sc_sta[node_index].an_valid = 0;
1355 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1358 static void ath_node_update_tgt(void *Context, A_UINT16 Command,
1359 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1361 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1362 struct ieee80211_node_target *node;
1363 a_uint8_t vap_index;
1364 a_uint8_t node_index;
1366 node = (struct ieee80211_node_target *)data;
1368 node_index = node->ni_nodeindex;
1370 node->ni_htcap = adf_os_ntohs(node->ni_htcap);
1371 node->ni_flags = adf_os_ntohs(node->ni_flags);
1372 node->ni_maxampdu = adf_os_ntohs(node->ni_maxampdu);
1374 adf_os_mem_copy(&(sc->sc_sta[node_index].ni), node,
1377 vap_index = sc->sc_sta[node_index].ni.ni_vapindex;
1378 sc->sc_sta[node_index].ni.ni_vap = &(sc->sc_vap[vap_index].av_vap);
1380 sc->sc_sta[node_index].ni.ni_txseqmgmt = 0;
1381 sc->sc_sta[node_index].ni.ni_iv16 = 0;
1382 sc->sc_sta[node_index].ni.ni_iv32 = 0;
1384 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1387 static a_int32_t ath_reg_read_filter(struct ath_hal *ah, a_int32_t addr)
1389 if ((addr & 0xffffe000) == 0x2000) {
1390 /* SEEPROM registers */
1392 if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0))
1393 adf_os_print("SEEPROM Read fail: 0x%08x\n", addr);
1395 return ioread32_mac(0x407c) & 0x0000ffff;
1396 } else if (addr > 0xffff)
1398 return ioread32(addr);
1401 return ioread32_mac(addr);
1404 static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command,
1405 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1407 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1408 struct ath_hal *ah = sc->sc_ah;
1413 for (i = 0; i < datalen; i += sizeof(a_int32_t)) {
1414 addr = *(a_uint32_t *)(data + i);
1415 addr = adf_os_ntohl(addr);
1417 val[i/sizeof(a_int32_t)] =
1418 adf_os_ntohl(ath_reg_read_filter(ah, addr));
1421 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &val[0], datalen);
1424 static void ath_pll_reset_ones(struct ath_hal *ah)
1426 static uint8_t reset_pll = 0;
1428 if(reset_pll == 0) {
1429 #if defined(PROJECT_K2)
1430 /* here we write to core register */
1431 iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
1432 /* and here to mac register */
1433 iowrite32_mac(0x786c,
1434 ioread32_mac(0x786c) | 0x6000000);
1435 iowrite32_mac(0x786c,
1436 ioread32_mac(0x786c) & (~0x6000000));
1438 iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20);
1440 #elif defined(PROJECT_MAGPIE) && !defined (FPGA)
1441 iowrite32_mac(0x7890,
1442 ioread32_mac(0x7890) | 0x1800000);
1443 iowrite32_mac(0x7890,
1444 ioread32_mac(0x7890) & (~0x1800000));
1450 static void ath_hal_reg_write_filter(struct ath_hal *ah,
1451 a_uint32_t reg, a_uint32_t val)
1454 iowrite32(reg, val);
1455 #if defined(PROJECT_K2)
1456 if(reg == 0x50040) {
1457 static uint8_t flg=0;
1460 /* reinit clock and uart.
1461 * TODO: Independent on what host will
1462 * here set. We do our own decision. Why? */
1464 A_UART_HWINIT(117*1000*1000, 19200);
1471 ath_pll_reset_ones(ah);
1473 iowrite32_mac(reg, val);
1477 static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command,
1478 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1480 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1481 struct ath_hal *ah = sc->sc_ah;
1483 struct registerWrite {
1488 for (i = 0; i < datalen; i += sizeof(struct registerWrite)) {
1489 t = (struct registerWrite *)(data+i);
1491 ath_hal_reg_write_filter(ah, t->reg, t->val);
1494 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1497 static void ath_hal_reg_rmw_tgt(void *Context, A_UINT16 Command,
1498 A_UINT16 SeqNo, A_UINT8 *data,
1501 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1502 struct ath_hal *ah = sc->sc_ah;
1503 struct register_rmw *buf = (struct register_rmw *)data;
1506 for (i = 0; i < datalen;
1507 i += sizeof(struct register_rmw)) {
1509 buf = (struct register_rmw *)(data + i);
1511 val = ath_reg_read_filter(ah, buf->reg);
1514 ath_hal_reg_write_filter(ah, buf->reg, val);
1516 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1519 static void ath_vap_delete_tgt(void *Context, A_UINT16 Command,
1520 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1522 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1523 a_uint8_t vap_index;
1525 vap_index = *(a_uint8_t *)data;
1527 sc->sc_vap[vap_index].av_valid = 0;
1528 sc->sc_vap[vap_index].av_bcbuf = NULL;
1529 ath_node_vdelete_tgt(sc, vap_index);
1530 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1533 static void ath_disable_intr_tgt(void *Context, A_UINT16 Command,
1534 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1536 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1537 struct ath_hal *ah = sc->sc_ah;
1539 ah->ah_setInterrupts(ah, 0);
1540 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
1543 static void ath_flushrecv_tgt(void *Context, A_UINT16 Command,
1544 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1546 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1547 struct ath_rx_buf *bf;
1549 asf_tailq_foreach(bf, &sc->sc_rxbuf, bf_list)
1550 if (bf->bf_skb != NULL) {
1551 adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap,
1552 ADF_OS_DMA_FROM_DEVICE);
1553 ath_free_rx_skb(sc, adf_nbuf_queue_remove(&bf->bf_skbhead));
1557 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1560 static void ath_tx_draintxq_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1561 A_UINT8 *data, a_int32_t datalen)
1563 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1564 a_uint32_t q = *(a_uint32_t *)data;
1565 struct ath_txq *txq = NULL;
1567 q = adf_os_ntohl(q);
1568 txq = ATH_TXQ(sc, q);
1570 ath_tx_draintxq(sc, txq);
1571 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1574 static void ath_draintxq_tgt(void *Context, A_UINT16 Command,
1575 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1577 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1578 HAL_BOOL b = (HAL_BOOL) *(a_int32_t *)data;
1580 ath_draintxq(Context, b);
1581 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1584 static void ath_aborttx_dma_tgt(void *Context, A_UINT16 Command,
1585 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1587 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1588 struct ath_hal *ah = sc->sc_ah;
1590 ah->ah_abortTxDma(sc->sc_ah);
1591 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1594 static void ath_aborttxq_tgt(void *Context, A_UINT16 Command,
1595 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1598 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1601 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
1602 if (ATH_TXQ_SETUP(sc, i))
1603 ath_tx_draintxq(sc, ATH_TXQ(sc,i));
1606 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1609 static void ath_stop_tx_dma_tgt(void *Context, A_UINT16 Command,
1610 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1612 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1613 struct ath_hal *ah = sc->sc_ah;
1617 q = *(a_uint32_t *)data;
1619 q = adf_os_ntohl(q);
1620 ah->ah_stopTxDma(ah, q);
1621 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1624 static void ath_startrecv_tgt(void *Context, A_UINT16 Command,
1625 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1628 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1631 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1634 static void ath_stoprecv_tgt(void *Context, A_UINT16 Command,
1635 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1637 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1638 struct ath_hal *ah = sc->sc_ah;
1640 ah->ah_stopPcuReceive(ah);
1641 ah->ah_setRxFilter(ah, 0);
1642 ah->ah_stopDmaReceive(ah);
1644 sc->sc_rxlink = NULL;
1645 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1648 static void ath_setcurmode_tgt(void *Context, A_UINT16 Command,
1649 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1651 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1654 mode= *((a_uint16_t *)data);
1655 mode = adf_os_ntohs(mode);
1657 ath_setcurmode(sc, mode);
1659 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1662 static void ath_detach_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1663 A_UINT8 *data, a_int32_t datalen)
1665 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1666 struct ath_hal *ah = sc->sc_ah;
1670 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1671 adf_os_mem_free(sc);
1674 static void handle_echo_command(void *pContext, A_UINT16 Command,
1675 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1677 wmi_cmd_rsp(pContext, WMI_ECHO_CMDID, SeqNo, buffer, Length);
1680 static void handle_rc_state_change_cmd(void *Context, A_UINT16 Command,
1681 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1684 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1685 struct wmi_rc_state_change_cmd *wmi_data = (struct wmi_rc_state_change_cmd *)buffer;
1687 a_uint32_t capflag = adf_os_ntohl(wmi_data->capflag);
1689 ath_rate_newstate(sc, &sc->sc_vap[wmi_data->vap_index].av_vap,
1690 wmi_data->vap_state,
1694 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1697 static void handle_rc_rate_update_cmd(void *Context, A_UINT16 Command,
1698 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1700 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1701 struct wmi_rc_rate_update_cmd *wmi_data = (struct wmi_rc_rate_update_cmd *)buffer;
1703 a_uint32_t capflag = adf_os_ntohl(wmi_data->capflag);
1705 ath_rate_node_update(sc, &sc->sc_sta[wmi_data->node_index],
1710 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1713 static void dispatch_magpie_sys_cmds(void *pContext, A_UINT16 Command,
1714 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1719 static void ath_rc_mask_tgt(void *Context, A_UINT16 Command,
1720 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1722 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1723 struct wmi_rc_rate_mask_cmd *wmi_data = (struct wmi_rc_rate_mask_cmd *)buffer;
1726 idx = wmi_data->vap_index;
1727 band = wmi_data->band;
1729 sc->sc_vap[idx].av_rate_mask[band] = adf_os_ntohl(wmi_data->mask);
1731 if (sc->sc_vap[idx].av_rate_mask[band]) {
1732 for (i = 0; i < RATE_TABLE_SIZE; i++) {
1733 if ((1 << i) & sc->sc_vap[idx].av_rate_mask[band]) {
1734 sc->sc_vap[idx].av_minrateidx[band] = i;
1739 sc->sc_vap[idx].av_minrateidx[band] = 0;
1742 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1745 static WMI_DISPATCH_ENTRY Magpie_Sys_DispatchEntries[] =
1747 {handle_echo_command, WMI_ECHO_CMDID, 0},
1748 {dispatch_magpie_sys_cmds, WMI_ACCESS_MEMORY_CMDID, 0},
1749 {ath_get_tgt_version, WMI_GET_FW_VERSION, 0},
1750 {ath_disable_intr_tgt, WMI_DISABLE_INTR_CMDID, 0},
1751 {ath_enable_intr_tgt, WMI_ENABLE_INTR_CMDID, 0},
1752 {ath_init_tgt, WMI_ATH_INIT_CMDID, 0},
1753 {ath_aborttxq_tgt, WMI_ABORT_TXQ_CMDID, 0},
1754 {ath_stop_tx_dma_tgt, WMI_STOP_TX_DMA_CMDID, 0},
1755 {ath_aborttx_dma_tgt, WMI_ABORT_TX_DMA_CMDID, 0},
1756 {ath_tx_draintxq_tgt, WMI_DRAIN_TXQ_CMDID, 0},
1757 {ath_draintxq_tgt, WMI_DRAIN_TXQ_ALL_CMDID, 0},
1758 {ath_startrecv_tgt, WMI_START_RECV_CMDID, 0},
1759 {ath_stoprecv_tgt, WMI_STOP_RECV_CMDID, 0},
1760 {ath_flushrecv_tgt, WMI_FLUSH_RECV_CMDID, 0},
1761 {ath_setcurmode_tgt, WMI_SET_MODE_CMDID, 0},
1762 {ath_node_create_tgt, WMI_NODE_CREATE_CMDID, 0},
1763 {ath_node_cleanup_tgt, WMI_NODE_REMOVE_CMDID, 0},
1764 {ath_vap_delete_tgt, WMI_VAP_REMOVE_CMDID, 0},
1765 {ath_vap_create_tgt, WMI_VAP_CREATE_CMDID, 0},
1766 {ath_hal_reg_read_tgt, WMI_REG_READ_CMDID, 0},
1767 {ath_hal_reg_write_tgt, WMI_REG_WRITE_CMDID, 0},
1768 {handle_rc_state_change_cmd, WMI_RC_STATE_CHANGE_CMDID, 0},
1769 {handle_rc_rate_update_cmd, WMI_RC_RATE_UPDATE_CMDID, 0},
1770 {ath_ic_update_tgt, WMI_TARGET_IC_UPDATE_CMDID, 0},
1771 {ath_enable_aggr_tgt, WMI_TX_AGGR_ENABLE_CMDID, 0},
1772 {ath_detach_tgt, WMI_TGT_DETACH_CMDID, 0},
1773 {ath_node_update_tgt, WMI_NODE_UPDATE_CMDID, 0},
1774 {ath_int_stats_tgt, WMI_INT_STATS_CMDID, 0},
1775 {ath_tx_stats_tgt, WMI_TX_STATS_CMDID, 0},
1776 {ath_rx_stats_tgt, WMI_RX_STATS_CMDID, 0},
1777 {ath_rc_mask_tgt, WMI_BITRATE_MASK_CMDID, 0},
1778 {ath_hal_reg_rmw_tgt, WMI_REG_RMW_CMDID, 0},
1785 static void htc_setup_comp(void)
1789 static A_UINT8 tgt_ServiceConnect(HTC_SERVICE *pService,
1790 HTC_ENDPOINT_ID eid,
1794 a_int32_t *pLengthOut)
1796 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)pService->ServiceCtx;
1798 switch(pService->ServiceID) {
1799 case WMI_CONTROL_SVC:
1800 sc->wmi_command_ep= eid;
1802 case WMI_BEACON_SVC:
1814 case WMI_DATA_VO_SVC:
1815 sc->data_VO_ep = eid;
1817 case WMI_DATA_VI_SVC:
1818 sc->data_VI_ep = eid;
1820 case WMI_DATA_BE_SVC:
1821 sc->data_BE_ep = eid;
1823 case WMI_DATA_BK_SVC:
1824 sc->data_BK_ep = eid;
1830 return HTC_SERVICE_SUCCESS;
1833 static void tgt_reg_service(struct ath_softc_tgt *sc, HTC_SERVICE *svc,
1834 int svcId, HTC_SERVICE_ProcessRecvMsg recvMsg)
1836 svc->ProcessRecvMsg = recvMsg;
1837 svc->ProcessSendBufferComplete = tgt_HTCSendCompleteHandler;
1838 svc->ProcessConnect = tgt_ServiceConnect;
1839 svc->MaxSvcMsgSize = 1600;
1840 svc->TrailerSpcCheckLimit = 0;
1841 svc->ServiceID = svcId;
1842 svc->ServiceCtx = sc;
1843 HTC_RegisterService(sc->tgt_htc_handle, svc);
1846 static void tgt_hif_htc_wmi_init(struct ath_softc_tgt *sc)
1848 HTC_CONFIG htc_conf;
1849 WMI_SVC_CONFIG wmiConfig;
1850 WMI_DISPATCH_TABLE *Magpie_Sys_Commands_Tbl;
1852 /* Init dynamic buf pool */
1853 sc->pool_handle = BUF_Pool_init(sc->sc_hdl);
1855 /* Init target-side HIF */
1856 sc->tgt_hif_handle = HIF_init(0);
1858 /* Init target-side HTC */
1859 htc_conf.HIFHandle = sc->tgt_hif_handle;
1860 htc_conf.CreditSize = 320;
1861 htc_conf.CreditNumber = ATH_TXBUF;
1862 htc_conf.OSHandle = sc->sc_hdl;
1863 htc_conf.PoolHandle = sc->pool_handle;
1864 sc->tgt_htc_handle = HTC_init(htc_setup_comp, &htc_conf);
1865 #if defined(PROJECT_MAGPIE)
1866 init_htc_handle = sc->tgt_htc_handle;
1869 tgt_reg_service(sc, &sc->htc_beacon_service, WMI_BEACON_SVC, tgt_HTCRecv_beaconhandler);
1870 tgt_reg_service(sc, &sc->htc_cab_service, WMI_CAB_SVC, tgt_HTCRecv_cabhandler);
1871 tgt_reg_service(sc, &sc->htc_uapsd_service, WMI_UAPSD_SVC, tgt_HTCRecv_uapsdhandler);
1872 tgt_reg_service(sc, &sc->htc_mgmt_service, WMI_MGMT_SVC, tgt_HTCRecv_mgmthandler);
1873 tgt_reg_service(sc, &sc->htc_data_BE_service, WMI_DATA_BE_SVC, tgt_HTCRecvMessageHandler);
1874 tgt_reg_service(sc, &sc->htc_data_BK_service, WMI_DATA_BK_SVC, tgt_HTCRecvMessageHandler);
1875 tgt_reg_service(sc, &sc->htc_data_VI_service, WMI_DATA_VI_SVC, tgt_HTCRecvMessageHandler);
1876 tgt_reg_service(sc, &sc->htc_data_VO_service, WMI_DATA_VO_SVC, tgt_HTCRecvMessageHandler);
1878 /* Init target-side WMI */
1879 Magpie_Sys_Commands_Tbl = (WMI_DISPATCH_TABLE *)adf_os_mem_alloc(sizeof(WMI_DISPATCH_TABLE));
1880 adf_os_mem_zero(Magpie_Sys_Commands_Tbl, sizeof(WMI_DISPATCH_TABLE));
1881 Magpie_Sys_Commands_Tbl->NumberOfEntries = WMI_DISPATCH_ENTRY_COUNT(Magpie_Sys_DispatchEntries);
1882 Magpie_Sys_Commands_Tbl->pTable = Magpie_Sys_DispatchEntries;
1884 adf_os_mem_zero(&wmiConfig, sizeof(WMI_SVC_CONFIG));
1885 wmiConfig.HtcHandle = sc->tgt_htc_handle;
1886 wmiConfig.PoolHandle = sc->pool_handle;
1887 wmiConfig.MaxCmdReplyEvts = ATH_WMI_MAX_CMD_REPLY;
1888 wmiConfig.MaxEventEvts = ATH_WMI_MAX_EVENTS;
1890 sc->tgt_wmi_handle = WMI_Init(&wmiConfig);
1891 Magpie_Sys_Commands_Tbl->pContext = sc;
1892 WMI_RegisterDispatchTable(sc->tgt_wmi_handle, Magpie_Sys_Commands_Tbl);
1894 HTC_NotifyTargetInserted(sc->tgt_htc_handle);
1896 /* Start HTC messages exchange */
1897 HTC_Ready(sc->tgt_htc_handle);
1900 a_int32_t ath_tgt_attach(a_uint32_t devid, struct ath_softc_tgt *sc, adf_os_device_t osdev)
1904 a_int32_t error = 0, i, flags = 0;
1907 adf_os_pci_config_read8(osdev, ATH_PCI_CACHE_LINE_SIZE, &csz);
1911 sc->sc_cachelsz = csz << 2;
1916 ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_rxtq, ath_tgt_rx_tasklet, sc);
1917 ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_txtq, owl_tgt_tx_tasklet, sc);
1918 ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_bmisstq, ath_bmiss_tasklet, sc);
1919 ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_fataltq, ath_fatal_tasklet, sc);
1921 flags |= AH_USE_EEPROM;
1922 ah = _ath_hal_attach_tgt(devid, sc, sc->sc_dev, flags, &status);
1929 tgt_hif_htc_wmi_init(sc);
1931 sc->sc_bhalq = HAL_NUM_TX_QUEUES - 1;
1933 ath_rate_setup(sc, IEEE80211_MODE_11NA);
1934 ath_rate_setup(sc, IEEE80211_MODE_11NG);
1936 sc->sc_rc = ath_rate_attach(sc);
1937 if (sc->sc_rc == NULL) {
1942 for (i=0; i < TARGET_NODE_MAX; i++) {
1943 sc->sc_sta[i].an_rcnode = adf_os_mem_alloc(sc->sc_rc->arc_space);
1946 error = ath_desc_alloc(sc);
1951 BUF_Pool_create_pool(sc->pool_handle, POOL_ID_WLAN_RX_BUF, ath_numrxdescs, 1664);
1953 ath_tgt_txq_setup(sc);
1955 ah->ah_setInterrupts(ah, 0);
1965 static void tgt_hif_htc_wmi_shutdown(struct ath_softc_tgt *sc)
1967 HTC_NotifyTargetDetached(sc->tgt_htc_handle);
1969 WMI_Shutdown(sc->tgt_wmi_handle);
1970 HTC_Shutdown(sc->tgt_htc_handle);
1971 HIF_shutdown(sc->tgt_hif_handle);
1972 BUF_Pool_shutdown(sc->pool_handle);
1975 a_int32_t ath_detach(struct ath_softc_tgt *sc)
1977 tgt_hif_htc_wmi_shutdown(sc);