2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
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36 #ifndef _DEV_ATH_AR5416REG_H
37 #define _DEV_ATH_AR5416REG_H
39 /* DMA Control and Interrupt Registers */
40 #define AR_CR 0x0008 // MAC Control Register - only write values of 1 have effect
41 #define AR_CR_RXE 0x00000004 // Receive enable
42 #define AR_CR_RXD 0x00000020 // Receive disable
43 #define AR_CR_SWI 0x00000040 // One-shot software interrupt
45 #define AR_RXDP 0x000C // MAC receive queue descriptor pointer
47 #define AR_CFG 0x0014 // MAC configuration and status register
48 #define AR_CFG_SWTD 0x00000001 // byteswap tx descriptor words
49 #define AR_CFG_SWTB 0x00000002 // byteswap tx data buffer words
50 #define AR_CFG_SWRD 0x00000004 // byteswap rx descriptor words
51 #define AR_CFG_SWRB 0x00000008 // byteswap rx data buffer words
52 #define AR_CFG_SWRG 0x00000010 // byteswap register access data words
53 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 // AP/adhoc indication (0-AP 1-Adhoc)
54 #define AR_CFG_PHOK 0x00000100 // PHY OK status
55 #define AR_CFG_CLK_GATE_DIS 0x00000400 // Clock gating disable
56 #define AR_CFG_EEBS 0x00000200 // EEPROM busy
57 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000 // Mask of PCI core master request queue full threshold
58 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17 // Shift for PCI core master request queue full threshold
60 #define AR_MIRT 0x0020 // Mac Interrupt rate threshold register
61 #define AR_MIRT_VAL 0x0000ffff // in uS
62 #define AR_MIRT_VAL_S 16
64 #define AR_IER 0x0024 // MAC Interrupt enable register
65 #define AR_IER_ENABLE 0x00000001 // Global interrupt enable
66 #define AR_IER_DISABLE 0x00000000 // Global interrupt disable
68 #define AR_TIMT 0x0028 // Mac Tx Interrupt mitigation threshold
69 #define AR_TIMT_LAST 0x0000ffff // Last packet threshold
70 #define AR_TIMT_LAST_S 0
71 #define AR_TIMT_FIRST 0xffff0000 // First packet threshold
72 #define AR_TIMT_FIRST_S 16
74 #define AR_RIMT 0x002C // Mac Rx Interrupt mitigation threshold
75 #define AR_RIMT_LAST 0x0000ffff // Last packet threshold
76 #define AR_RIMT_LAST_S 0
77 #define AR_RIMT_FIRST 0xffff0000 // First packet threshold
78 #define AR_RIMT_FIRST_S 16
80 #define AR_DMASIZE_4B 0x00000000 // DMA size 4 bytes (TXCFG + RXCFG)
81 #define AR_DMASIZE_8B 0x00000001 // DMA size 8 bytes
82 #define AR_DMASIZE_16B 0x00000002 // DMA size 16 bytes
83 #define AR_DMASIZE_32B 0x00000003 // DMA size 32 bytes
84 #define AR_DMASIZE_64B 0x00000004 // DMA size 64 bytes
85 #define AR_DMASIZE_128B 0x00000005 // DMA size 128 bytes
86 #define AR_DMASIZE_256B 0x00000006 // DMA size 256 bytes
87 #define AR_DMASIZE_512B 0x00000007 // DMA size 512 bytes
89 #define AR_TXCFG 0x0030 // MAC tx DMA size config register
90 #define AR_TXCFG_DMASZ_MASK 0x00000003
91 #define AR_TXCFG_DMASZ_4B 0
92 #define AR_TXCFG_DMASZ_8B 1
93 #define AR_TXCFG_DMASZ_16B 2
94 #define AR_TXCFG_DMASZ_32B 3
95 #define AR_TXCFG_DMASZ_64B 4
96 #define AR_TXCFG_DMASZ_128B 5
97 #define AR_TXCFG_DMASZ_256B 6
98 #define AR_TXCFG_DMASZ_512B 7
99 #define AR_FTRIG 0x000003F0 // Mask for Frame trigger level
100 #define AR_FTRIG_S 4 // Shift for Frame trigger level
101 #define AR_FTRIG_IMMED 0x00000000 // bytes in PCU TX FIFO before air
102 #define AR_FTRIG_64B 0x00000010 // default
103 #define AR_FTRIG_128B 0x00000020
104 #define AR_FTRIG_192B 0x00000030
105 #define AR_FTRIG_256B 0x00000040 // 5 bits total
106 #define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800
108 #define AR_RXCFG 0x0034 // MAC rx DMA size config register
109 #define AR_RXCFG_CHIRP 0x00000008 // Only double chirps
110 #define AR_RXCFG_ZLFDMA 0x00000010 // Enable DMA of zero-length frame
111 #define AR_RXCFG_DMASZ_MASK 0x00000007
112 #define AR_RXCFG_DMASZ_4B 0
113 #define AR_RXCFG_DMASZ_8B 1
114 #define AR_RXCFG_DMASZ_16B 2
115 #define AR_RXCFG_DMASZ_32B 3
116 #define AR_RXCFG_DMASZ_64B 4
117 #define AR_RXCFG_DMASZ_128B 5
118 #define AR_RXCFG_DMASZ_256B 6
119 #define AR_RXCFG_DMASZ_512B 7
121 #define AR_MIBC 0x0040 // MAC MIB control register
122 #define AR_MIBC_COW 0x00000001 // counter overflow warning
123 #define AR_MIBC_FMC 0x00000002 // freeze MIB counters
124 #define AR_MIBC_CMC 0x00000004 // clear MIB counters
125 #define AR_MIBC_MCS 0x00000008 // MIB counter strobe increment all
127 #define AR_TOPS 0x0044 // MAC timeout prescale count
128 #define AR_TOPS_MASK 0x0000FFFF // Mask for timeout prescale
130 #define AR_RXNPTO 0x0048 // MAC no frame received timeout
131 #define AR_RXNPTO_MASK 0x000003FF // Mask for no frame received timeout
133 #define AR_TXNPTO 0x004C // MAC no frame trasmitted timeout
134 #define AR_TXNPTO_MASK 0x000003FF // Mask for no frame transmitted timeout
135 #define AR_TXNPTO_QCU_MASK 0x000FFC00 // Mask indicating the set of QCUs
136 // for which frame completions will cause
137 // a reset of the no frame transmitted timeout
139 #define AR_RPGTO 0x0050 // MAC receive frame gap timeout
140 #define AR_RPGTO_MASK 0x000003FF // Mask for receive frame gap timeout
142 #define AR_RPCNT 0x0054 // MAC receive frame count limit
143 #define AR_RPCNT_MASK 0x0000001F // Mask for receive frame count limit
145 #define AR_MACMISC 0x0058 // MAC miscellaneous control/status register
146 #define AR_MACMISC_PCI_EXT_FORCE 0x00000010 //force msb to 10 to ahb
147 #define AR_MACMISC_DMA_OBS 0x000001E0 // Mask for DMA observation bus mux select
148 #define AR_MACMISC_DMA_OBS_S 5 // Shift for DMA observation bus mux select
149 #define AR_MACMISC_MISC_OBS 0x00000E00 // Mask for MISC observation bus mux select
150 #define AR_MACMISC_MISC_OBS_S 9 // Shift for MISC observation bus mux select
151 #define AR_MACMISC_MISC_OBS_BUS_LSB 0x00007000 // Mask for MAC observation bus mux select (lsb)
152 #define AR_MACMISC_MISC_OBS_BUS_LSB_S 12 // Shift for MAC observation bus mux select (lsb)
153 #define AR_MACMISC_MISC_OBS_BUS_MSB 0x00038000 // Mask for MAC observation bus mux select (msb)
154 #define AR_MACMISC_MISC_OBS_BUS_MSB_S 15 // Shift for MAC observation bus mux select (msb)
156 #define AR_GTXTO 0x0064 // MAC global transmit timeout
157 #define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs)
158 #define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs)
159 #define AR_GTXTO_TIMEOUT_LIMIT_S 16 // Shift for timeout limit
161 #define AR_GTTM 0x0068 // MAC global transmit timeout mode
162 #define AR_GTTM_USEC 0x00000001 // usec strobe
163 #define AR_GTTM_IGNORE_IDLE 0x00000002 // ignore channel idle
164 #define AR_GTTM_RESET_IDLE 0x00000004 // reset counter on channel idle low
165 #define AR_GTTM_CST_USEC 0x00000008 // CST usec strobe
167 #define AR_CST 0x006C // MAC carrier sense timeout
168 #define AR_CST_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs)
169 #define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs)
170 #define AR_CST_TIMEOUT_LIMIT_S 16 // Shift for timeout limit
172 #define AR_SREV_VERSION_HOWL 0x014
174 #define AR_SREV_5416_V20_OR_LATER(_ah) (AR_SREV_HOWL((_ah)) || AR_SREV_OWL_20_OR_LATER(_ah))
175 #define AR_SREV_5416_V22_OR_LATER(_ah) (AR_SREV_HOWL((_ah)) || AR_SREV_OWL_22_OR_LATER(_ah))
177 #ifdef AR5416_EMULATION
178 /* XXX - AR5416 Emulation only
179 * XXX - TODO - remove when emulation complete
181 #define AR_EMU 0x0070 // MAC - special emulation only register
182 #define AR_EMU_RATETHROT 0x00000001 // rate throttling (enabled = 1)
183 #define AR_EMU_CTL 0x00000002 // ctl channel busy (busy = 1)
184 #define AR_EMU_EXT 0x00000004 // ext channel busy (busy = 1)
185 #define AR_EMU_HALF_RATE 0x00000080 // run at half-rate for encryption
186 #define AR_EMU_VERSION 0xFFFFFF00 // Mask for version (read only)
187 #define AR_EMU_VERSION_S 8 // Shift for timeout limit
189 #endif //AR5416_EMULATION
191 /* Interrupt Status Registers */
192 #define AR_ISR 0x0080 // MAC Primary interrupt status register
193 #define AR_ISR_RXOK 0x00000001 // At least one frame received sans errors
194 #define AR_ISR_RXDESC 0x00000002 // Receive interrupt request
195 #define AR_ISR_RXERR 0x00000004 // Receive error interrupt
196 #define AR_ISR_RXNOPKT 0x00000008 // No frame received within timeout clock
197 #define AR_ISR_RXEOL 0x00000010 // Received descriptor empty interrupt
198 #define AR_ISR_RXORN 0x00000020 // Receive FIFO overrun interrupt
199 #define AR_ISR_TXOK 0x00000040 // Transmit okay interrupt
200 #define AR_ISR_TXDESC 0x00000080 // Transmit interrupt request
201 #define AR_ISR_TXERR 0x00000100 // Transmit error interrupt
202 #define AR_ISR_TXNOPKT 0x00000200 // No frame transmitted interrupt
203 #define AR_ISR_TXEOL 0x00000400 // Transmit descriptor empty interrupt
204 #define AR_ISR_TXURN 0x00000800 // Transmit FIFO underrun interrupt
205 #define AR_ISR_MIB 0x00001000 // MIB interrupt - see MIBC
206 #define AR_ISR_SWI 0x00002000 // Software interrupt
207 #define AR_ISR_RXPHY 0x00004000 // PHY receive error interrupt
208 #define AR_ISR_RXKCM 0x00008000 // Key-cache miss interrupt
209 #define AR_ISR_SWBA 0x00010000 // Software beacon alert interrupt
210 #define AR_ISR_BRSSI 0x00020000 // Beacon threshold interrupt
211 #define AR_ISR_BMISS 0x00040000 // Beacon missed interrupt
212 #define AR_ISR_BNR 0x00100000 // Beacon not ready interrupt
213 #define AR_ISR_RXCHIRP 0x00200000 // Phy received a 'chirp'
214 #define AR_ISR_BCNMISC 0x00800000 // In venice 'or' of TIM CABEND DTIMSYNC BCNTO CABTO DTIM bits from ISR_S2
215 #define AR_ISR_TIM 0x00800000 // TIM interrupt
216 #define AR_ISR_QCBROVF 0x02000000 // QCU CBR overflow interrupt
217 #define AR_ISR_QCBRURN 0x04000000 // QCU CBR underrun interrupt
218 #define AR_ISR_QTRIG 0x08000000 // QCU scheduling trigger interrupt
219 #define AR_ISR_GENTMR 0x10000000 // OR of generic timer bits in ISR 5
221 #ifdef AR5416_INT_MITIGATION
222 #define AR_ISR_TXMINTR 0x00080000 // Maximum interrupt transmit rate
223 #define AR_ISR_RXMINTR 0x01000000 // Maximum interrupt receive rate
224 #define AR_ISR_TXINTM 0x40000000 // Tx interrupt after mitigation
225 #define AR_ISR_RXINTM 0x80000000 // Rx interrupt after mitigation
228 #define AR_ISR_S0 0x0084 // MAC Secondary interrupt status register 0
229 #define AR_ISR_S0_QCU_TXOK 0x000003FF // Mask for TXOK (QCU 0-9)
230 #define AR_ISR_S0_QCU_TXOK_S 0 // Shift for TXOK (QCU 0-9)
231 #define AR_ISR_S0_QCU_TXDESC 0x03FF0000 // Mask for TXDESC (QCU 0-9)
232 #define AR_ISR_S0_QCU_TXDESC_S 16 // Shift for TXDESC (QCU 0-9)
234 #define AR_ISR_S1 0x0088 // MAC Secondary interrupt status register 1
235 #define AR_ISR_S1_QCU_TXERR 0x000003FF // Mask for TXERR (QCU 0-9)
236 #define AR_ISR_S1_QCU_TXERR_S 0 // Shift for TXERR (QCU 0-9)
237 #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 // Mask for TXEOL (QCU 0-9)
238 #define AR_ISR_S1_QCU_TXEOL_S 16 // Shift for TXEOL (QCU 0-9)
240 #define AR_ISR_S2 0x008c // MAC Secondary interrupt status register 2
241 #define AR_ISR_S2_QCU_TXURN 0x000003FF // Mask for TXURN (QCU 0-9)
242 #define AR_ISR_S2_CST 0x00400000 // Carrier sense timeout
243 #define AR_ISR_S2_GTT 0x00800000 // Global transmit timeout
244 #define AR_ISR_S2_TIM 0x01000000 // TIM
245 #define AR_ISR_S2_CABEND 0x02000000 // CABEND
246 #define AR_ISR_S2_DTIMSYNC 0x04000000 // DTIMSYNC
247 #define AR_ISR_S2_BCNTO 0x08000000 // BCNTO
248 #define AR_ISR_S2_CABTO 0x10000000 // CABTO
249 #define AR_ISR_S2_DTIM 0x20000000 // DTIM
250 #define AR_ISR_S2_TSFOOR 0x40000000 // Rx TSF out of range
251 #define AR_ISR_S2_TBTT_TIME 0x80000000 // TBTT-referenced timer
253 #define AR_ISR_S3 0x0090 // MAC Secondary interrupt status register 3
254 #define AR_ISR_S3_QCU_QCBROVF 0x000003FF // Mask for QCBROVF (QCU 0-9)
255 #define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 // Mask for QCBRURN (QCU 0-9)
257 #define AR_ISR_S4 0x0094 // MAC Secondary interrupt status register 4
258 #define AR_ISR_S4_QCU_QTRIG 0x000003FF // Mask for QTRIG (QCU 0-9)
259 #define AR_ISR_S4_RESV0 0xFFFFFC00 // Reserved
261 #define AR_ISR_S5 0x0098 // MAC Secondary interrupt status register 5
262 #define AR_ISR_S5_TIMER_TRIG 0x000000FF // Mask for timer trigger (0-7)
263 #define AR_ISR_S5_TIMER_THRESH 0x0007FE00 // Mask for timer threshold(0-7)
264 #define AR_ISR_S5_GENTIMER7 0x80 //Timer 7 does not have a dedicated function
266 /* Interrupt Mask Registers */
267 #define AR_IMR 0x00a0 // MAC Primary interrupt mask register
268 #define AR_IMR_RXOK 0x00000001 // At least one frame received sans errors
269 #define AR_IMR_RXDESC 0x00000002 // Receive interrupt request
270 #define AR_IMR_RXERR 0x00000004 // Receive error interrupt
271 #define AR_IMR_RXNOPKT 0x00000008 // No frame received within timeout clock
272 #define AR_IMR_RXEOL 0x00000010 // Received descriptor empty interrupt
273 #define AR_IMR_RXORN 0x00000020 // Receive FIFO overrun interrupt
274 #define AR_IMR_TXOK 0x00000040 // Transmit okay interrupt
275 #define AR_IMR_TXDESC 0x00000080 // Transmit interrupt request
276 #define AR_IMR_TXERR 0x00000100 // Transmit error interrupt
277 #define AR_IMR_TXNOPKT 0x00000200 // No frame transmitted interrupt
278 #define AR_IMR_TXEOL 0x00000400 // Transmit descriptor empty interrupt
279 #define AR_IMR_TXURN 0x00000800 // Transmit FIFO underrun interrupt
280 #define AR_IMR_MIB 0x00001000 // MIB interrupt - see MIBC
281 #define AR_IMR_SWI 0x00002000 // Software interrupt
282 #define AR_IMR_RXPHY 0x00004000 // PHY receive error interrupt
283 #define AR_IMR_RXKCM 0x00008000 // Key-cache miss interrupt
284 #define AR_IMR_SWBA 0x00010000 // Software beacon alert interrupt
285 #define AR_IMR_BRSSI 0x00020000 // Beacon threshold interrupt
286 #define AR_IMR_BMISS 0x00040000 // Beacon missed interrupt
287 #define AR_IMR_BNR 0x00100000 // BNR interrupt
288 #define AR_IMR_RXCHIRP 0x00200000 // RXCHIRP interrupt
289 #define AR_IMR_BCNMISC 0x00800000 // Venice: BCNMISC
290 #define AR_IMR_TIM 0x00800000 // TIM interrupt
291 #define AR_IMR_QCBROVF 0x02000000 // QCU CBR overflow interrupt
292 #define AR_IMR_QCBRURN 0x04000000 // QCU CBR underrun interrupt
293 #define AR_IMR_QTRIG 0x08000000 // QCU scheduling trigger interrupt
294 #define AR_IMR_GENTMR 0x10000000 // Generic timer interrupt
296 #ifdef AR5416_INT_MITIGATION
297 #define AR_IMR_TXMINTR 0x00080000 // Maximum interrupt transmit rate
298 #define AR_IMR_RXMINTR 0x01000000 // Maximum interrupt receive rate
299 #define AR_IMR_TXINTM 0x40000000 // Tx interrupt after mitigation
300 #define AR_IMR_RXINTM 0x80000000 // Rx interrupt after mitigation
303 #define AR_IMR_S0 0x00a4 // MAC Secondary interrupt mask register 0
304 #define AR_IMR_S0_QCU_TXOK 0x000003FF // Mask for TXOK (QCU 0-9)
305 #define AR_IMR_S0_QCU_TXOK_S 0 // Shift for TXOK (QCU 0-9)
306 #define AR_IMR_S0_QCU_TXDESC 0x03FF0000 // Mask for TXDESC (QCU 0-9)
307 #define AR_IMR_S0_QCU_TXDESC_S 16 // Shift for TXDESC (QCU 0-9)
309 #define AR_IMR_S1 0x00a8 // MAC Secondary interrupt mask register 1
310 #define AR_IMR_S1_QCU_TXERR 0x000003FF // Mask for TXERR (QCU 0-9)
311 #define AR_IMR_S1_QCU_TXERR_S 0 // Shift for TXERR (QCU 0-9)
312 #define AR_IMR_S1_QCU_TXEOL 0x03FF0000 // Mask for TXEOL (QCU 0-9)
313 #define AR_IMR_S1_QCU_TXEOL_S 16 // Shift for TXEOL (QCU 0-9)
315 #define AR_IMR_S2 0x00ac // MAC Secondary interrupt mask register 2
316 #define AR_IMR_S2_QCU_TXURN 0x000003FF // Mask for TXURN (QCU 0-9)
317 #define AR_IMR_S2_QCU_TXURN_S 0 // Shift for TXURN (QCU 0-9)
318 #define AR_IMR_S2_CST 0x00400000 // Carrier sense timeout
319 #define AR_IMR_S2_GTT 0x00800000 // Global transmit timeout
320 #define AR_IMR_S2_TIM 0x01000000 // TIM
321 #define AR_IMR_S2_CABEND 0x02000000 // CABEND
322 #define AR_IMR_S2_DTIMSYNC 0x04000000 // DTIMSYNC
323 #define AR_IMR_S2_BCNTO 0x08000000 // BCNTO
324 #define AR_IMR_S2_CABTO 0x10000000 // CABTO
325 #define AR_IMR_S2_DTIM 0x20000000 // DTIM
326 #define AR_IMR_S2_TSFOOR 0x40000000 // TSF overrun
328 #define AR_IMR_S3 0x00b0 // MAC Secondary interrupt mask register 3
329 #define AR_IMR_S3_QCU_QCBROVF 0x000003FF // Mask for QCBROVF (QCU 0-9)
330 #define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 // Mask for QCBRURN (QCU 0-9)
331 #define AR_IMR_S3_QCU_QCBRURN_S 16 // Shift for QCBRURN (QCU 0-9)
333 #define AR_IMR_S4 0x00b4 // MAC Secondary interrupt mask register 4
334 #define AR_IMR_S4_QCU_QTRIG 0x000003FF // Mask for QTRIG (QCU 0-9)
335 #define AR_IMR_S4_RESV0 0xFFFFFC00 // Reserved
337 #define AR_IMR_S5 0x00b8 // MAC Secondary interrupt mask register 5
338 #define AR_IMR_S5_TIMER_TRIG 0x000000FF // Mask for timer trigger (0-7)
339 #define AR_IMR_S5_TIMER_THRESH 0x0000FF00 // Mask for timer threshold(0-7)
340 #define AR_IMR_S5_GENTIMER7 0x80 //Timer 7 does not have a dedicated function
342 /* Interrupt status registers (read-and-clear access secondary shadow copies) */
343 #define AR_ISR_RAC 0x00c0 // MAC Primary interrupt status register
344 // read-and-clear access
345 #define AR_ISR_S0_S 0x00c4 // MAC Secondary interrupt status register 0
347 /* Interrupt status registers (read-and-clear access secondary shadow copies) */
348 #define AR_ISR_RAC 0x00c0 // MAC Primary interrupt status register
349 // read-and-clear access
350 #define AR_ISR_S0_S 0x00c4 // MAC Secondary interrupt status register 0
352 #define AR_ISR_S0_QCU_TXOK 0x000003FF // Mask for TXOK (QCU 0-9)
353 #define AR_ISR_S0_QCU_TXOK_S 0 // Shift for TXOK (QCU 0-9)
354 #define AR_ISR_S0_QCU_TXDESC 0x03FF0000 // Mask for TXDESC (QCU 0-9)
355 #define AR_ISR_S0_QCU_TXDESC_S 16 // Shift for TXDESC (QCU 0-9)
357 #define AR_ISR_S1_S 0x00c8 // MAC Secondary interrupt status register 1
359 #define AR_ISR_S1_QCU_TXERR 0x000003FF // Mask for TXERR (QCU 0-9)
360 #define AR_ISR_S1_QCU_TXERR_S 0 // Shift for TXERR (QCU 0-9)
361 #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 // Mask for TXEOL (QCU 0-9)
362 #define AR_ISR_S1_QCU_TXEOL_S 16 // Shift for TXEOL (QCU 0-9)
364 #define AR_ISR_S2_S 0x00cc // MAC Secondary interrupt status register 2
366 #define AR_ISR_S3_S 0x00d0 // MAC Secondary interrupt status register 3
368 #define AR_ISR_S4_S 0x00d4 // MAC Secondary interrupt status register 4
370 #define AR_ISR_S5_S 0x00d8 // MAC Secondary interrupt status register 5
372 #define AR_DMADBG_0 0x00e0 // MAC DMA Debug Registers
373 #define AR_DMADBG_1 0x00e4
374 #define AR_DMADBG_2 0x00e8
375 #define AR_DMADBG_3 0x00ec
376 #define AR_DMADBG_4 0x00f0
377 #define AR_DMADBG_5 0x00f4
378 #define AR_DMADBG_6 0x00f8
379 #define AR_DMADBG_7 0x00fc
382 #define AR_NUM_QCU 10 // Only use QCU 0-9 for forward QCU compatibility
383 #define AR_QCU_0 0x0001
384 #define AR_QCU_1 0x0002
385 #define AR_QCU_2 0x0004
386 #define AR_QCU_3 0x0008
387 #define AR_QCU_4 0x0010
388 #define AR_QCU_5 0x0020
389 #define AR_QCU_6 0x0040
390 #define AR_QCU_7 0x0080
391 #define AR_QCU_8 0x0100
392 #define AR_QCU_9 0x0200
394 #define AR_Q0_TXDP 0x0800 // MAC Transmit Queue descriptor pointer
395 #define AR_Q1_TXDP 0x0804 // MAC Transmit Queue descriptor pointer
396 #define AR_Q2_TXDP 0x0808 // MAC Transmit Queue descriptor pointer
397 #define AR_Q3_TXDP 0x080c // MAC Transmit Queue descriptor pointer
398 #define AR_Q4_TXDP 0x0810 // MAC Transmit Queue descriptor pointer
399 #define AR_Q5_TXDP 0x0814 // MAC Transmit Queue descriptor pointer
400 #define AR_Q6_TXDP 0x0818 // MAC Transmit Queue descriptor pointer
401 #define AR_Q7_TXDP 0x081c // MAC Transmit Queue descriptor pointer
402 #define AR_Q8_TXDP 0x0820 // MAC Transmit Queue descriptor pointer
403 #define AR_Q9_TXDP 0x0824 // MAC Transmit Queue descriptor pointer
404 #define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2))
406 #define AR_Q_TXE 0x0840 // MAC Transmit Queue enable
407 #define AR_Q_TXE_M 0x000003FF // Mask for TXE (QCU 0-9)
409 #define AR_Q_TXD 0x0880 // MAC Transmit Queue disable
410 #define AR_Q_TXD_M 0x000003FF // Mask for TXD (QCU 0-9)
412 #define AR_Q0_CBRCFG 0x08c0 // MAC CBR configuration
413 #define AR_Q1_CBRCFG 0x08c4 // MAC CBR configuration
414 #define AR_Q2_CBRCFG 0x08c8 // MAC CBR configuration
415 #define AR_Q3_CBRCFG 0x08cc // MAC CBR configuration
416 #define AR_Q4_CBRCFG 0x08d0 // MAC CBR configuration
417 #define AR_Q5_CBRCFG 0x08d4 // MAC CBR configuration
418 #define AR_Q6_CBRCFG 0x08d8 // MAC CBR configuration
419 #define AR_Q7_CBRCFG 0x08dc // MAC CBR configuration
420 #define AR_Q8_CBRCFG 0x08e0 // MAC CBR configuration
421 #define AR_Q9_CBRCFG 0x08e4 // MAC CBR configuration
422 #define AR_QCBRCFG(_i) (AR_Q0_CBRCFG + ((_i)<<2))
423 #define AR_Q_CBRCFG_INTERVAL 0x00FFFFFF // Mask for CBR interval (us)
424 #define AR_Q_CBRCFG_INTERVAL_S 0 // Shift for CBR interval (us)
425 #define AR_Q_CBRCFG_OVF_THRESH 0xFF000000 // Mask for CBR overflow threshold
426 #define AR_Q_CBRCFG_OVF_THRESH_S 24 // Shift for CBR overflow threshold
428 #define AR_Q0_RDYTIMECFG 0x0900 // MAC ReadyTime configuration
429 #define AR_Q1_RDYTIMECFG 0x0904 // MAC ReadyTime configuration
430 #define AR_Q2_RDYTIMECFG 0x0908 // MAC ReadyTime configuration
431 #define AR_Q3_RDYTIMECFG 0x090c // MAC ReadyTime configuration
432 #define AR_Q4_RDYTIMECFG 0x0910 // MAC ReadyTime configuration
433 #define AR_Q5_RDYTIMECFG 0x0914 // MAC ReadyTime configuration
434 #define AR_Q6_RDYTIMECFG 0x0918 // MAC ReadyTime configuration
435 #define AR_Q7_RDYTIMECFG 0x091c // MAC ReadyTime configuration
436 #define AR_Q8_RDYTIMECFG 0x0920 // MAC ReadyTime configuration
437 #define AR_Q9_RDYTIMECFG 0x0924 // MAC ReadyTime configuration
438 #define AR_QRDYTIMECFG(_i) (AR_Q0_RDYTIMECFG + ((_i)<<2))
439 #define AR_Q_RDYTIMECFG_DURATION 0x00FFFFFF // Mask for ReadyTime duration (us)
440 #define AR_Q_RDYTIMECFG_DURATION_S 0 // Shift for ReadyTime duration (us)
441 #define AR_Q_RDYTIMECFG_EN 0x01000000 // ReadyTime enable
443 #define AR_Q_ONESHOTARM_SC 0x0940 // MAC OneShotArm set control
444 #define AR_Q_ONESHOTARM_SC_M 0x000003FF // Mask for #define AR_Q_ONESHOTARM_SC (QCU 0-9)
445 #define AR_Q_ONESHOTARM_SC_RESV0 0xFFFFFC00 // Reserved
447 #define AR_Q_ONESHOTARM_CC 0x0980 // MAC OneShotArm clear control
448 #define AR_Q_ONESHOTARM_CC_M 0x000003FF // Mask for #define AR_Q_ONESHOTARM_CC (QCU 0-9)
449 #define AR_Q_ONESHOTARM_CC_RESV0 0xFFFFFC00 // Reserved
451 #define AR_Q0_MISC 0x09c0 // MAC Miscellaneous QCU settings
452 #define AR_Q1_MISC 0x09c4 // MAC Miscellaneous QCU settings
453 #define AR_Q2_MISC 0x09c8 // MAC Miscellaneous QCU settings
454 #define AR_Q3_MISC 0x09cc // MAC Miscellaneous QCU settings
455 #define AR_Q4_MISC 0x09d0 // MAC Miscellaneous QCU settings
456 #define AR_Q5_MISC 0x09d4 // MAC Miscellaneous QCU settings
457 #define AR_Q6_MISC 0x09d8 // MAC Miscellaneous QCU settings
458 #define AR_Q7_MISC 0x09dc // MAC Miscellaneous QCU settings
459 #define AR_Q8_MISC 0x09e0 // MAC Miscellaneous QCU settings
460 #define AR_Q9_MISC 0x09e4 // MAC Miscellaneous QCU settings
461 #define AR_QMISC(_i) (AR_Q0_MISC + ((_i)<<2))
462 #define AR_Q_MISC_FSP 0x0000000F // Mask for Frame Scheduling Policy
463 #define AR_Q_MISC_FSP_ASAP 0 // ASAP
464 #define AR_Q_MISC_FSP_CBR 1 // CBR
465 #define AR_Q_MISC_FSP_DBA_GATED 2 // DMA Beacon Alert gated
466 #define AR_Q_MISC_FSP_TIM_GATED 3 // TIM gated
467 #define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 // Beacon-sent-gated
468 #define AR_Q_MISC_FSP_BEACON_RCVD_GATED 5 // Beacon-received-gated
469 #define AR_Q_MISC_ONE_SHOT_EN 0x00000010 // OneShot enable
470 #define AR_Q_MISC_CBR_INCR_DIS1 0x00000020 // Disable CBR expired counter incr (empty q)
471 #define AR_Q_MISC_CBR_INCR_DIS0 0x00000040 // Disable CBR expired counter incr (empty beacon q)
472 #define AR_Q_MISC_BEACON_USE 0x00000080 // Beacon use indication
473 #define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN 0x00000100 // CBR expired counter limit enable
474 #define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200 // Enable TXE cleared on ReadyTime expired or VEOL
475 #define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 // Reset CBR expired counter
476 #define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800 // DCU frame early termination request control
477 #define AR_Q_MISC_RESV0 0xFFFFF000 // Reserved
479 #define AR_Q0_STS 0x0a00 // MAC Miscellaneous QCU status
480 #define AR_Q1_STS 0x0a04 // MAC Miscellaneous QCU status
481 #define AR_Q2_STS 0x0a08 // MAC Miscellaneous QCU status
482 #define AR_Q3_STS 0x0a0c // MAC Miscellaneous QCU status
483 #define AR_Q4_STS 0x0a10 // MAC Miscellaneous QCU status
484 #define AR_Q5_STS 0x0a14 // MAC Miscellaneous QCU status
485 #define AR_Q6_STS 0x0a18 // MAC Miscellaneous QCU status
486 #define AR_Q7_STS 0x0a1c // MAC Miscellaneous QCU status
487 #define AR_Q8_STS 0x0a20 // MAC Miscellaneous QCU status
488 #define AR_Q9_STS 0x0a24 // MAC Miscellaneous QCU status
489 #define AR_QSTS(_i) (AR_Q0_STS + ((_i)<<2))
490 #define AR_Q_STS_PEND_FR_CNT 0x00000003 // Mask for Pending Frame Count
491 #define AR_Q_STS_RESV0 0x000000FC // Reserved
492 #define AR_Q_STS_CBR_EXP_CNT 0x0000FF00 // Mask for CBR expired counter
493 #define AR_Q_STS_RESV1 0xFFFF0000 // Reserved
495 #define AR_Q_RDYTIMESHDN 0x0a40 // MAC ReadyTimeShutdown status
496 #define AR_Q_RDYTIMESHDN_M 0x000003FF // Mask for ReadyTimeShutdown status (QCU 0-9)
499 #define AR_NUM_DCU 10 // Only use 10 DCU's for forward QCU/DCU compatibility
500 #define AR_DCU_0 0x0001
501 #define AR_DCU_1 0x0002
502 #define AR_DCU_2 0x0004
503 #define AR_DCU_3 0x0008
504 #define AR_DCU_4 0x0010
505 #define AR_DCU_5 0x0020
506 #define AR_DCU_6 0x0040
507 #define AR_DCU_7 0x0080
508 #define AR_DCU_8 0x0100
509 #define AR_DCU_9 0x0200
511 #define AR_D0_QCUMASK 0x1000 // MAC QCU Mask
512 #define AR_D1_QCUMASK 0x1004 // MAC QCU Mask
513 #define AR_D2_QCUMASK 0x1008 // MAC QCU Mask
514 #define AR_D3_QCUMASK 0x100c // MAC QCU Mask
515 #define AR_D4_QCUMASK 0x1010 // MAC QCU Mask
516 #define AR_D5_QCUMASK 0x1014 // MAC QCU Mask
517 #define AR_D6_QCUMASK 0x1018 // MAC QCU Mask
518 #define AR_D7_QCUMASK 0x101c // MAC QCU Mask
519 #define AR_D8_QCUMASK 0x1020 // MAC QCU Mask
520 #define AR_D9_QCUMASK 0x1024 // MAC QCU Mask
521 #define AR_DQCUMASK(_i) (AR_D0_QCUMASK + ((_i)<<2))
522 #define AR_D_QCUMASK 0x000003FF // Mask for QCU Mask (QCU 0-9)
523 #define AR_D_QCUMASK_RESV0 0xFFFFFC00 // Reserved
525 #define AR_D_TXBLK_CMD 0x1038 /* DCU transmit filter cmd (w/only) */
526 #define AR_D_TXBLK_DATA(i) (AR_D_TXBLK_CMD+(i)) /* DCU transmit filter data */
528 #define AR_D0_LCL_IFS 0x1040 // MAC DCU-specific IFS settings
529 #define AR_D1_LCL_IFS 0x1044 // MAC DCU-specific IFS settings
530 #define AR_D2_LCL_IFS 0x1048 // MAC DCU-specific IFS settings
531 #define AR_D3_LCL_IFS 0x104c // MAC DCU-specific IFS settings
532 #define AR_D4_LCL_IFS 0x1050 // MAC DCU-specific IFS settings
533 #define AR_D5_LCL_IFS 0x1054 // MAC DCU-specific IFS settings
534 #define AR_D6_LCL_IFS 0x1058 // MAC DCU-specific IFS settings
535 #define AR_D7_LCL_IFS 0x105c // MAC DCU-specific IFS settings
536 #define AR_D8_LCL_IFS 0x1060 // MAC DCU-specific IFS settings
537 #define AR_D9_LCL_IFS 0x1064 // MAC DCU-specific IFS settings
538 #define AR_DLCL_IFS(_i) (AR_D0_LCL_IFS + ((_i)<<2))
539 #define AR_D_LCL_IFS_CWMIN 0x000003FF // Mask for CW_MIN
540 #define AR_D_LCL_IFS_CWMIN_S 0 // Shift for CW_MIN
541 #define AR_D_LCL_IFS_CWMAX 0x000FFC00 // Mask for CW_MAX
542 #define AR_D_LCL_IFS_CWMAX_S 10 // Shift for CW_MAX
543 #define AR_D_LCL_IFS_AIFS 0x0FF00000 // Mask for AIFS
544 #define AR_D_LCL_IFS_AIFS_S 20 // Shift for AIFS
546 * Note: even though this field is 8 bits wide the
547 * maximum supported AIFS value is 0xfc. Setting the AIFS value
548 * to 0xfd 0xfe or 0xff will not work correctly and will cause
551 #define AR_D_LCL_IFS_RESV0 0xF0000000 // Reserved
553 #define AR_D0_RETRY_LIMIT 0x1080 // MAC Retry limits
554 #define AR_D1_RETRY_LIMIT 0x1084 // MAC Retry limits
555 #define AR_D2_RETRY_LIMIT 0x1088 // MAC Retry limits
556 #define AR_D3_RETRY_LIMIT 0x108c // MAC Retry limits
557 #define AR_D4_RETRY_LIMIT 0x1090 // MAC Retry limits
558 #define AR_D5_RETRY_LIMIT 0x1094 // MAC Retry limits
559 #define AR_D6_RETRY_LIMIT 0x1098 // MAC Retry limits
560 #define AR_D7_RETRY_LIMIT 0x109c // MAC Retry limits
561 #define AR_D8_RETRY_LIMIT 0x10a0 // MAC Retry limits
562 #define AR_D9_RETRY_LIMIT 0x10a4 // MAC Retry limits
563 #define AR_DRETRY_LIMIT(_i) (AR_D0_RETRY_LIMIT + ((_i)<<2))
564 #define AR_D_RETRY_LIMIT_FR_SH 0x0000000F // Mask for frame short retry limit
565 #define AR_D_RETRY_LIMIT_FR_SH_S 0 // Shift for frame short retry limit
566 #define AR_D_RETRY_LIMIT_STA_SH 0x00003F00 // Mask for station short retry limit
567 #define AR_D_RETRY_LIMIT_STA_SH_S 8 // Shift for station short retry limit
568 #define AR_D_RETRY_LIMIT_STA_LG 0x000FC000 // Mask for station short retry limit
569 #define AR_D_RETRY_LIMIT_STA_LG_S 14 // Shift for station short retry limit
570 #define AR_D_RETRY_LIMIT_RESV0 0xFFF00000 // Reserved
572 #define AR_D0_CHNTIME 0x10c0 // MAC ChannelTime settings
573 #define AR_D1_CHNTIME 0x10c4 // MAC ChannelTime settings
574 #define AR_D2_CHNTIME 0x10c8 // MAC ChannelTime settings
575 #define AR_D3_CHNTIME 0x10cc // MAC ChannelTime settings
576 #define AR_D4_CHNTIME 0x10d0 // MAC ChannelTime settings
577 #define AR_D5_CHNTIME 0x10d4 // MAC ChannelTime settings
578 #define AR_D6_CHNTIME 0x10d8 // MAC ChannelTime settings
579 #define AR_D7_CHNTIME 0x10dc // MAC ChannelTime settings
580 #define AR_D8_CHNTIME 0x10e0 // MAC ChannelTime settings
581 #define AR_D9_CHNTIME 0x10e4 // MAC ChannelTime settings
582 #define AR_DCHNTIME(_i) (AR_D0_CHNTIME + ((_i)<<2))
583 #define AR_D_CHNTIME_DUR 0x000FFFFF // Mask for ChannelTime duration (us)
584 #define AR_D_CHNTIME_DUR_S 0 // Shift for ChannelTime duration (us)
585 #define AR_D_CHNTIME_EN 0x00100000 // ChannelTime enable
586 #define AR_D_CHNTIME_RESV0 0xFFE00000 // Reserved
588 #define AR_D0_MISC 0x1100 // MAC Miscellaneous DCU-specific settings
589 #define AR_D1_MISC 0x1104 // MAC Miscellaneous DCU-specific settings
590 #define AR_D2_MISC 0x1108 // MAC Miscellaneous DCU-specific settings
591 #define AR_D3_MISC 0x110c // MAC Miscellaneous DCU-specific settings
592 #define AR_D4_MISC 0x1110 // MAC Miscellaneous DCU-specific settings
593 #define AR_D5_MISC 0x1114 // MAC Miscellaneous DCU-specific settings
594 #define AR_D6_MISC 0x1118 // MAC Miscellaneous DCU-specific settings
595 #define AR_D7_MISC 0x111c // MAC Miscellaneous DCU-specific settings
596 #define AR_D8_MISC 0x1120 // MAC Miscellaneous DCU-specific settings
597 #define AR_D9_MISC 0x1124 // MAC Miscellaneous DCU-specific settings
598 #define AR_DMISC(_i) (AR_D0_MISC + ((_i)<<2))
599 #define AR_D_MISC_BKOFF_THRESH 0x0000003F // Mask for Backoff threshold setting
600 #define AR_D_MISC_RETRY_CNT_RESET_EN 0x00000040 // End of tx series station RTS/data failure count reset policy
601 #define AR_D_MISC_CW_RESET_EN 0x00000080 // End of tx series CW reset enable
602 #define AR_D_MISC_FRAG_WAIT_EN 0x00000100 // Fragment Starvation Policy
603 #define AR_D_MISC_FRAG_BKOFF_EN 0x00000200 // Backoff during a frag burst
604 #define AR_D_MISC_CW_BKOFF_EN 0x00001000 // Use binary exponential CW backoff
605 #define AR_D_MISC_VIR_COL_HANDLING 0x0000C000 // Mask for Virtual collision handling policy
606 #define AR_D_MISC_VIR_COL_HANDLING_S 14 // Shift for Virtual collision handling policy
607 #define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0 // Normal
608 #define AR_D_MISC_VIR_COL_HANDLING_IGNORE 1 // Ignore
609 #define AR_D_MISC_BEACON_USE 0x00010000 // Beacon use indication
610 #define AR_D_MISC_ARB_LOCKOUT_CNTRL 0x00060000 // Mask for DCU arbiter lockout control
611 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17 // Shift for DCU arbiter lockout control
612 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 // No lockout
613 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 // Intra-frame
614 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 // Global
615 #define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000 // DCU arbiter lockout ignore control
616 #define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000 // Sequence number increment disable
617 #define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 // Post-frame backoff disable
618 #define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000 // Virtual coll. handling policy
619 #define AR_D_MISC_BLOWN_IFS_RETRY_EN 0x00800000 // Initiate Retry procedure on Blown IFS
620 #define AR_D_MISC_RESV0 0xFF000000 // Reserved
622 #define AR_D_SEQNUM 0x1140 // MAC Frame sequence number control/status
624 #define AR_D_GBL_IFS_SIFS 0x1030 // MAC DCU-global IFS settings: SIFS duration
625 #define AR_D_GBL_IFS_SIFS_M 0x0000FFFF // Mask for SIFS duration (core clocks)
626 #define AR_D_GBL_IFS_SIFS_RESV0 0xFFFFFFFF // Reserved
628 #define AR_D_TXBLK_BASE 0x1038 // MAC DCU-global transmit filter bits
629 #define AR_D_TXBLK_WRITE_BITMASK 0x0000FFFF // Mask for bitmask
630 #define AR_D_TXBLK_WRITE_BITMASK_S 0 // Shift for bitmask
631 #define AR_D_TXBLK_WRITE_SLICE 0x000F0000 // Mask for slice
632 #define AR_D_TXBLK_WRITE_SLICE_S 16 // Shift for slice
633 #define AR_D_TXBLK_WRITE_DCU 0x00F00000 // Mask for DCU number
634 #define AR_D_TXBLK_WRITE_DCU_S 20 // Shift for DCU number
635 #define AR_D_TXBLK_WRITE_COMMAND 0x0F000000 // Mask for command
636 #define AR_D_TXBLK_WRITE_COMMAND_S 24 // Shift for command
638 #define AR_D_GBL_IFS_SLOT 0x1070 // MAC DCU-global IFS settings: slot duration
639 #define AR_D_GBL_IFS_SLOT_M 0x0000FFFF // Mask for Slot duration (core clocks)
640 #define AR_D_GBL_IFS_SLOT_RESV0 0xFFFF0000 // Reserved
642 #define AR_D_GBL_IFS_EIFS 0x10b0 // MAC DCU-global IFS settings: EIFS duration
643 #define AR_D_GBL_IFS_EIFS_M 0x0000FFFF // Mask for Slot duration (core clocks)
644 #define AR_D_GBL_IFS_EIFS_RESV0 0xFFFF0000 // Reserved
646 #define AR_D_GBL_IFS_MISC 0x10f0 // MAC DCU-global IFS settings: Miscellaneous
647 #define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 // Mask forLFSR slice select
648 #define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008 // Turbo mode indication
649 #define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000FFC00 // Mask for microsecond duration
650 #define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000 // Mask for DCU arbiter delay
651 #define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000 // Random LSFR slice disable
652 #define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN 0x06000000 // Slot transmission window length mask
653 #define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000 // Force transmission on slot boundaries
654 #define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF 0x10000000 // Ignore backoff
656 #define AR_D_FPCTL 0x1230 // DCU frame prefetch settings
657 #define AR_D_FPCTL_DCU 0x0000000F // Mask for DCU for which prefetch is enabled
658 #define AR_D_FPCTL_DCU_S 0 // Shift for DCU for which prefetch is enabled
659 #define AR_D_FPCTL_PREFETCH_EN 0x00000010 // Enable prefetch for normal (non-burst) operation
660 #define AR_D_FPCTL_BURST_PREFETCH 0x00007FE0 // Mask for Burst frame prefetch per DCU
661 #define AR_D_FPCTL_BURST_PREFETCH_S 5 // Shift for Burst frame prefetch per DCU
663 #define AR_D_TXPSE 0x1270 // MAC DCU transmit pause control/status
664 #define AR_D_TXPSE_CTRL 0x000003FF // Mask of DCUs to pause (DCUs 0-9)
665 #define AR_D_TXPSE_RESV0 0x0000FC00 // Reserved
666 #define AR_D_TXPSE_STATUS 0x00010000 // Transmit pause status
667 #define AR_D_TXPSE_RESV1 0xFFFE0000 // Reserved
669 #define AR_D_TXSLOTMASK 0x12f0 // MAC DCU transmission slot mask
670 #define AR_D_TXSLOTMASK_NUM 0x0000000F // slot numbers
672 #define AR_MAC_LED 0x1f04 /* LED control */
673 #define AR_MAC_SCLK_RATE_IND 0x00000003 /* sleep clock indication */
674 #define AR_MAC_SCLK_RATE_IND_S 0
675 #define AR_MAC_SCLK_32MHZ 0x00000000 /* Sleep clock rate */
676 #define AR_MAC_SCLK_4MHZ 0x00000001 /* Sleep clock rate */
677 #define AR_MAC_SCLK_1MHZ 0x00000002 /* Sleep clock rate */
678 #define AR_MAC_SCLK_32KHZ 0x00000003 /* Sleep clock rate */
679 #define AR_MAC_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode */
680 #define AR_MAC_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select */
681 #define AR_MAC_LED_MODE_SEL 0x00000380 /* LED mode select */
682 #define AR_MAC_LED_MODE_SEL_S 7
683 #define AR_MAC_LED_MODE_PROP 0 /* Blink prop to filtered tx/rx */
684 #define AR_MAC_LED_MODE_RPROP 1 /* Blink prop to unfiltered tx/rx */
685 #define AR_MAC_LED_MODE_SPLIT 2 /* Blink power for tx/net for rx */
686 #define AR_MAC_LED_MODE_RAND 3 /* Blink randomly */
687 #define AR_MAC_LED_ASSOC_CTL 0x00000c00
688 #define AR_MAC_LED_ASSOC_NONE 0x00000000 /* STA is not associated or trying */
689 #define AR_MAC_LED_ASSOC_ACTIVE 0x00000400 /* STA is associated */
690 #define AR_MAC_LED_ASSOC_PENDING 0x00000800 /* STA is trying to associate */
692 #define AR_MAC_SLEEP 0x1ff0
693 #define AR_MAC_SLEEP_MAC_AWAKE 0x00000000 // mac is now awake
694 #define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001 // mac is now asleep
696 // DMA & PCI Registers in PCI space (usable during sleep)
697 #define AR_RC 0x4000 // Warm reset control register
698 #define AR_RC_AHB 0x00000001 // ahb reset
699 #define AR_RC_APB 0x00000002 // apb reset
701 #define AR_WA 0x4004 // PCI express work-arounds
703 #define AR_PM_STATE 0x4008 // power management state
704 #define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000 //for wow
706 #define AR_HOST_TIMEOUT 0x4018 // dma xfer timeout
707 #define AR_HOST_APB_TIMEOUT 0x0000FFFF // apb bus timeout
708 #define AR_HOST_LB_TIMEOUT 0xFFFF0000 // local bus timeout
710 #define AR_EEPROM 0x401c // eeprom info
711 #define AR_EEPROM_ABSENT 0x00000100
712 #define AR_EEPROM_CORRUPT 0x00000200
713 #define AR_EEPROM_PROT_MASK 0x03FFFC00
714 #define AR_EEPROM_PROT_MASK_S 10
716 // Protect Bits RP is read protect WP is write protect
717 #define EEPROM_PROTECT_RP_0_31 0x0001
718 #define EEPROM_PROTECT_WP_0_31 0x0002
719 #define EEPROM_PROTECT_RP_32_63 0x0004
720 #define EEPROM_PROTECT_WP_32_63 0x0008
721 #define EEPROM_PROTECT_RP_64_127 0x0010
722 #define EEPROM_PROTECT_WP_64_127 0x0020
723 #define EEPROM_PROTECT_RP_128_191 0x0040
724 #define EEPROM_PROTECT_WP_128_191 0x0080
725 #define EEPROM_PROTECT_RP_192_255 0x0100
726 #define EEPROM_PROTECT_WP_192_255 0x0200
727 #define EEPROM_PROTECT_RP_256_511 0x0400
728 #define EEPROM_PROTECT_WP_256_511 0x0800
729 #define EEPROM_PROTECT_RP_512_1023 0x1000
730 #define EEPROM_PROTECT_WP_512_1023 0x2000
731 #define EEPROM_PROTECT_RP_1024_2047 0x4000
732 #define EEPROM_PROTECT_WP_1024_2047 0x8000
735 #define AR_SREV 0x0600 /*mac silicon rev (expanded from 8 bits to 16 bits for Sowl) */
736 #define AR_SREV_ID 0x00000FFF /* Mask to read SREV info */
738 #define AR_SREV 0x4020 // mac silicon rev
739 #define AR_SREV_ID 0x000000FF /* Mask to read SREV info */
741 #define AR_SREV_VERSION 0x000000F0 /* Mask for Chip version */
742 #define AR_SREV_VERSION_S 4 /* Mask to shift Major Rev Info */
743 #define AR_SREV_REVISION 0x00000007 /* Mask for Chip revision level */
744 /* Sowl extension to SREV. AR_SREV_ID must be 0xFF */
745 #define AR_SREV_ID2 0xFFFFFFFF /* Mask to read SREV info */
746 #define AR_SREV_VERSION2 0xFFFC0000 /* Mask for Chip version */
747 #define AR_SREV_VERSION2_S 18 /* Mask to shift Major Rev Info */
748 #define AR_SREV_TYPE2 0x0003F000 /* Mask for Chip type */
749 #define AR_SREV_TYPE2_S 12 /* Mask to shift Major Rev Info */
750 #define AR_SREV_TYPE2_CHAIN 0x00001000 /* chain mode (1 = 3 chains, 0 = 2 chains) */
751 #define AR_SREV_TYPE2_HOST_MODE 0x00002000 /* host mode (1 = PCI, 0 = PCIe) */
752 #define AR_SREV_REVISION2 0x00000F00
753 #define AR_SREV_REVISION2_S 8
755 #define AR_SREV_VERSION_OWL_PCI 0xD
756 #define AR_SREV_VERSION_OWL_PCIE 0xC
758 #define AR_SREV_REVISION_OWL_10 0 /* Owl 1.0 */
759 #define AR_SREV_REVISION_OWL_20 1 /* Owl 2.0/2.1 */
760 #define AR_SREV_REVISION_OWL_22 2 /* Owl 2.2 */
762 #define AR_SREV_VERSION_SOWL 0x43
764 #define AR_SREV_VERSION_SOWL 0x1F
766 #define AR_SREV_REVISION_SOWL_10 0 /* Sowl 1.0 */
767 #define AR_SREV_REVISION_SOWL_11 1 /* Sowl 1.1 */
769 #define AR_SREV_VERSION_MERLIN 0x2f /* Merlin Version,0x2F for fusion_merlin branch */
770 #define AR_SREV_REVISION_MERLIN_10 0 /* Merlin 1.0 */
771 #define AR_SREV_REVISION_MERLIN_20 1 /* Merlin 2.0 */
772 #define AR_SREV_REVISION_MERLIN_21 2 /* Merlin 2.1 */
774 #define AR_SREV_OWL_10(_ah) (((_ah)->ah_macVersion == AR_SREV_VERSION_OWL_PCI) || \
775 ((_ah)->ah_macVersion == AR_SREV_VERSION_OWL_PCIE))
777 #define AR_SREV_OWL_20_OR_LATER(_ah) ((AH_PRIVATE((_ah))->ah_macVersion >= AR_SREV_VERSION_SOWL) || \
778 (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_20))
779 #define AR_SREV_OWL_22_OR_LATER(_ah) ((AH_PRIVATE((_ah))->ah_macVersion >= AR_SREV_VERSION_SOWL) || \
780 (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_22))
781 #define AR_SREV_SOWL_10_OR_LATER(_ah) ((AH_PRIVATE((_ah))->ah_macVersion >= AR_SREV_VERSION_SOWL))
783 #define AR_SREV_MERLIN(_ah) ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_MERLIN))
784 #define AR_SREV_MERLIN_10_OR_LATER(_ah) ((AH_PRIVATE((_ah))->ah_macVersion >= AR_SREV_VERSION_MERLIN))
785 #define AR_SREV_MERLIN_20(_ah) ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_MERLIN) && \
786 (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_MERLIN_20))
787 #define AR_SREV_MERLIN_20_OR_LATER(_ah) ((AH_PRIVATE((_ah))->ah_macVersion > AR_SREV_VERSION_MERLIN) || \
788 ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_MERLIN) && \
789 (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_MERLIN_20)))
791 #define AR_SREV_SOWL(_ah) ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_SOWL))
792 #define AR_SREV_SOWL_11(_ah) (AR_SREV_SOWL(_ah) && (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_SOWL_11))
794 #define AR_RADIO_SREV_MAJOR 0xf0
795 #define AR_RAD5133_SREV_MAJOR 0xc0 /* Fowl: 2+5G/3x3 */
796 #define AR_RAD2133_SREV_MAJOR 0xd0 /* Fowl: 2G/3x3 */
797 #define AR_RAD5122_SREV_MAJOR 0xe0 /* Fowl: 5G/2x2 */
798 #define AR_RAD2122_SREV_MAJOR 0xf0 /* Fowl: 2+5G/2x2 */
800 #define AR_AHB_MODE 0x4024 // ahb mode for dma
801 #define AR_AHB_EXACT_WR_EN 0x00000000 // write exact bytes
802 #define AR_AHB_BUF_WR_EN 0x00000001 // buffer write upto cacheline
803 #define AR_AHB_EXACT_RD_EN 0x00000000 // read exact bytes
804 #define AR_AHB_CACHELINE_RD_EN 0x00000002 // read upto end of cacheline
805 #define AR_AHB_PREFETCH_RD_EN 0x00000004 // prefetch upto page boundary
806 #define AR_AHB_PAGE_SIZE_1K 0x00000000 // set page-size as 1k
807 #define AR_AHB_PAGE_SIZE_2K 0x00000008 // set page-size as 2k
808 #define AR_AHB_PAGE_SIZE_4K 0x00000010 // set page-size as 4k
810 #define AR_INTR_RTC_IRQ 0x00000001 // rtc in shutdown state
811 #define AR_INTR_MAC_IRQ 0x00000002 // pending mac interrupt
812 #define AR_INTR_EEP_PROT_ACCESS 0x00000004 // eeprom protected area access
813 #define AR_INTR_MAC_AWAKE 0x00020000 // mac is awake
814 #define AR_INTR_MAC_ASLEEP 0x00040000 // mac is asleep
815 /* TODO: fill in other values */
816 #define AR_INTR_GPIO 0x3FF00000 // gpio interrupted
817 #define AR_INTR_GPIO_S 20
819 #define AR_INTR_SYNC_CAUSE_CLR 0x4028 // clear interrupt
820 #define AR_INTR_SYNC_CAUSE 0x4028 // check pending interrupts
821 #define AR_INTR_SYNC_ENABLE 0x402c // enable interrupts
822 #define AR_INTR_ASYNC_MASK 0x4030 // asynchronous interrupt mask
823 #define AR_INTR_SYNC_MASK 0x4034 // synchronous interrupt mask
824 #define AR_INTR_ASYNC_CAUSE 0x4038 // check pending interrupts
825 #define AR_INTR_ASYNC_ENABLE 0x403c // enable interrupts
829 * synchronous interrupt signals
832 AR_INTR_SYNC_RTC_IRQ = 0x00000001,
833 AR_INTR_SYNC_MAC_IRQ = 0x00000002,
834 AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS = 0x00000004,
835 AR_INTR_SYNC_APB_TIMEOUT = 0x00000008,
836 AR_INTR_SYNC_PCI_MODE_CONFLICT = 0x00000010,
837 AR_INTR_SYNC_HOST1_FATAL = 0x00000020,
838 AR_INTR_SYNC_HOST1_PERR = 0x00000040,
839 AR_INTR_SYNC_TRCV_FIFO_PERR = 0x00000080,
840 AR_INTR_SYNC_RADM_CPL_EP = 0x00000100,
841 AR_INTR_SYNC_RADM_CPL_DLLP_ABORT = 0x00000200,
842 AR_INTR_SYNC_RADM_CPL_DLP_ABORT = 0x00000400,
843 AR_INTR_SYNC_RADM_CPL_ECRC_ERR = 0x00000800,
844 AR_INTR_SYNC_RADM_CPL_TIMEOUT = 0x00001000,
845 AR_INTR_SYNC_LOCAL_TIMEOUT = 0x00002000,
846 AR_INTR_SYNC_PM_ACCESS = 0x00004000,
847 AR_INTR_SYNC_MAC_AWAKE = 0x00008000,
848 AR_INTR_SYNC_MAC_ASLEEP = 0x00010000,
849 AR_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00020000,
850 AR_INTR_SYNC_ALL = 0x0003FFFF,
853 #define AR_NUM_GPIO 10 // Ten numbered 0 to 9.
857 #define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 // enable interrupts: bits 18..31
858 #define AR_INTR_ASYNC_ENABLE_GPIO_S 18 // enable interrupts: bits 18..31
861 #define AR_PCIE_SERDES 0x4040
862 #define AR_PCIE_SERDES2 0x4044
863 #define AR_PCIE_PM_CTRL 0x4014
864 #define AR_PCIE_PM_CTRL_ENA 0x00080000
866 #define AR928X_NUM_GPIO 10 // Ten numbered 0 to 9 for Merlin.
868 #define AR_GPIO_IN_OUT 0x4048 // GPIO input / output register
870 #define AR_GPIO_IN_VAL 0x0FFFC000
871 #define AR_GPIO_IN_VAL_S 14
872 #define AR928X_GPIO_IN_VAL 0x000FFC00 // added for Merlin
873 #define AR928X_GPIO_IN_VAL_S 10 // added for Merlin
875 /* Added for Merlin */
876 #define AR_GPIO_OE_OUT 0x404c // GPIO output register
877 #define AR_GPIO_OE_OUT_DRV 0x3 // 2 bit field mask, shifted by 2*bitpos
878 #define AR_GPIO_OE_OUT_DRV_NO 0x0 // tristate
879 #define AR_GPIO_OE_OUT_DRV_LOW 0x1 // drive if low
880 #define AR_GPIO_OE_OUT_DRV_HI 0x2 // drive if high
881 #define AR_GPIO_OE_OUT_DRV_ALL 0x3 // drive always
882 /* 4050-405C added for Merlin */
883 #define AR_GPIO_INTR_POL 0x4050 // GPIO interrup polarity: 0 == high level, 1 == lo level
884 #define AR_GPIO_INTR_POL_VAL 0x00001FFF // bits 13:0 correspond to gpio 13:0
885 #define AR_GPIO_INTR_POL_VAL_S 0 // bits 13:0 correspond to gpio 13:0
887 #define AR_GPIO_INPUT_EN_VAL 0x4054 // GPIO input enable and value
888 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 // default value for rfsilent_bb_l
889 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7
890 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 // 0 == set rfsilent_bb_l to default, 1 == connect rfsilent_bb_l to baseband
891 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15
892 #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000
893 #define AR_GPIO_JTAG_DISABLE 0x00020000 // 1 == disable JTAG
895 #define AR_GPIO_INPUT_MUX1 0x4058
897 #define AR_GPIO_INPUT_MUX2 0x405c
898 #define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f // bits 0..3: input mux for clk25 input
899 #define AR_GPIO_INPUT_MUX2_CLK25_S 0 // bits 0..3: input mux for clk25 input
900 #define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0 // bits 4..7: input mux for rfsilent_bb_l input
901 #define AR_GPIO_INPUT_MUX2_RFSILENT_S 4 // bits 4..7: input mux for rfsilent_bb_l input
902 #define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00 // bits 8..11: input mux for RTC Reset input
903 #define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 // bits 8..11: input mux for RTC Reset input
905 #define AR_GPIO_OUTPUT_MUX1 0x4060
906 /* 4064-4068 added for Merlin */
907 #define AR_GPIO_OUTPUT_MUX2 0x4064
908 #define AR_GPIO_OUTPUT_MUX3 0x4068
910 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
911 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
912 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
913 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
914 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
916 #define AR_INPUT_STATE 0x406c
918 #define AR_GPIO_PDPU 0x4088
920 /* 4094 added for Merlin */
921 #define AR_PCIE_MSI 0x4094
922 #define AR_PCIE_MSI_ENABLE 0x00000001
925 #define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */
927 // AR9280: rf long shift registers
928 #define AR_AN_RF2G1_CH0 0x7810
929 #define AR_AN_RF2G1_CH0_OB 0x03800000
930 #define AR_AN_RF2G1_CH0_OB_S 23
931 #define AR_AN_RF2G1_CH0_DB 0x1C000000
932 #define AR_AN_RF2G1_CH0_DB_S 26
934 #define AR_AN_RF5G1_CH0 0x7818
935 #define AR_AN_RF5G1_CH0_OB5 0x00070000
936 #define AR_AN_RF5G1_CH0_OB5_S 16
937 #define AR_AN_RF5G1_CH0_DB5 0x00380000
938 #define AR_AN_RF5G1_CH0_DB5_S 19
940 #define AR_AN_RF2G1_CH1 0x7834
941 #define AR_AN_RF2G1_CH1_OB 0x03800000
942 #define AR_AN_RF2G1_CH1_OB_S 23
943 #define AR_AN_RF2G1_CH1_DB 0x1C000000
944 #define AR_AN_RF2G1_CH1_DB_S 26
946 #define AR_AN_RF5G1_CH1 0x783C
947 #define AR_AN_RF5G1_CH1_OB5 0x00070000
948 #define AR_AN_RF5G1_CH1_OB5_S 16
949 #define AR_AN_RF5G1_CH1_DB5 0x00380000
950 #define AR_AN_RF5G1_CH1_DB5_S 19
952 #define AR_AN_TOP2 0x7894
953 #define AR_AN_TOP2_XPABIAS_LVL 0xC0000000
954 #define AR_AN_TOP2_XPABIAS_LVL_S 30
955 #define AR_AN_TOP2_LOCALBIAS 0x00200000
956 #define AR_AN_TOP2_LOCALBIAS_S 21
957 #define AR_AN_TOP2_PWDCLKIND 0x00400000
958 #define AR_AN_TOP2_PWDCLKIND_S 22
960 #define AR_AN_SYNTH9 0x7868
961 #define AR_AN_SYNTH9_REFDIVA 0xf8000000
962 #define AR_AN_SYNTH9_REFDIVA_S 27
964 #endif // MAGPIE_MERLIN
967 #define AR_GPIO_IN 0x4048 // GPIO input register
969 #define AR_GPIO_INTR_OUT 0x404c // GPIO output register
970 #define AR_GPIO_OUT_CTRL 0x000003FF // 0 = out, 1 = in
971 #define AR_GPIO_OUT_VAL 0x000FFC00
972 #define AR_GPIO_OUT_VAL_S 10
973 #define AR_GPIO_INTR_CTRL 0x3FF00000
974 #define AR_GPIO_INTR_CTRL_S 20
976 #define AR_GPIO_OUTPUT_MUX1 0x4060
978 #define AR_EEPROM_STATUS_DATA 0x407c
979 #define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff
980 #define AR_EEPROM_STATUS_DATA_VAL_S 0
981 #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000
982 #define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000
983 #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000
984 #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000
986 #define AR_OBS 0x4080
990 #define AR_RTC_SOWL_PLL_DIV 0x000003ff
991 #define AR_RTC_SOWL_PLL_DIV_S 0
992 #define AR_RTC_SOWL_PLL_REFDIV 0x00003C00
993 #define AR_RTC_SOWL_PLL_REFDIV_S 10
994 #define AR_RTC_SOWL_PLL_CLKSEL 0x0000C000
995 #define AR_RTC_SOWL_PLL_CLKSEL_S 14
998 #define AR_RTC_RC 0x7000 /* reset control */
999 #define AR_RTC_RC_M 0x00000003
1000 #define AR_RTC_RC_MAC_WARM 0x00000001
1001 #define AR_RTC_RC_MAC_COLD 0x00000002
1002 #define AR_RTC_PLL_CONTROL 0x7014
1004 #define AR_RTC_PLL_DIV 0x0000001f
1005 #define AR_RTC_PLL_DIV_S 0
1006 #define AR_RTC_PLL_DIV2 0x00000020
1007 #define AR_RTC_PLL_REFDIV_5 0x000000c0
1008 #define AR_RTC_PLL_CLKSEL_S 8
1009 #define AR_RTC_PLL_CLKSEL 0x00000300
1011 #define AR_RTC_RESET 0x7040 /* reset RTC */
1013 #define AR_RTC_STATUS 0x7044 /* system sleep status */
1014 #define AR_RTC_STATUS_M 0x0000000f
1015 #define AR_RTC_STATUS_SHUTDOWN 0x00000001
1016 #define AR_RTC_STATUS_ON 0x00000002
1017 #define AR_RTC_STATUS_SLEEP 0x00000004
1018 #define AR_RTC_STATUS_WAKEUP 0x00000008
1020 #define AR_RTC_SLEEP_CLK 0x7048
1021 #define AR_RTC_FORCE_DERIVED_CLK 0x2
1023 #define AR_RTC_FORCE_WAKE 0x704c /* control MAC force wake */
1024 #define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */
1025 #define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */
1027 #define AR_RTC_INTR_CAUSE 0x7050 /* RTC interrupt cause/clear */
1028 #define AR_RTC_INTR_ENABLE 0x7054 /* RTC interrupt enable */
1029 #define AR_RTC_INTR_MASK 0x7058 /* RTC interrupt mask */
1031 #define AR_SEQ_MASK 0x8060 /* MAC AES mute mask */
1033 #define AR_RTC_BASE 0x00020000
1034 #define AR_RTC_RC (AR_RTC_BASE + 0x0000) /* reset control */
1035 #define AR_RTC_RC_M 0x00000003
1036 #define AR_RTC_RC_MAC_WARM 0x00000001
1037 #define AR_RTC_RC_MAC_COLD 0x00000002
1038 #define AR_RTC_RC_COLD_RESET 0x00000004
1039 #define AR_RTC_RC_WARM_RESET 0x00000008
1041 #define AR_RTC_PLL_CONTROL (AR_RTC_BASE + 0x0014)
1042 #define AR_RTC_PLL_DIV 0x0000001f
1043 #define AR_RTC_PLL_DIV_S 0
1044 #define AR_RTC_PLL_DIV2 0x00000020
1045 #define AR_RTC_PLL_REFDIV_5 0x000000c0
1046 #define AR_RTC_PLL_CLKSEL_S 8
1047 #define AR_RTC_PLL_CLKSEL 0x00000300
1049 #define AR_RTC_RESET (AR_RTC_BASE + 0x0040) /* reset RTC */
1050 #define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */
1052 #define AR_RTC_STATUS (AR_RTC_BASE + 0x0044) /* system sleep status */
1053 #define AR_RTC_PM_STATUS_M 0x0000000f /* Pwr Mgmt Status is the last 4 bits */
1054 #define AR_RTC_STATUS_M 0x0000003f /* RTC Status is the last 6 bits */
1055 #define AR_RTC_STATUS_SHUTDOWN 0x00000001
1056 #define AR_RTC_STATUS_ON 0x00000002
1057 #define AR_RTC_STATUS_SLEEP 0x00000004
1058 #define AR_RTC_STATUS_WAKEUP 0x00000008
1060 #define AR_RTC_SLEEP_CLK (AR_RTC_BASE + 0x0048)
1061 #define AR_RTC_FORCE_DERIVED_CLK 0x2
1063 #define AR_RTC_FORCE_WAKE (AR_RTC_BASE + 0x004c) /* control MAC force wake */
1064 #define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */
1065 #define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */
1067 #define AR_RTC_INTR_CAUSE (AR_RTC_BASE + 0x0050) /* RTC interrupt cause/clear */
1068 #define AR_RTC_INTR_ENABLE (AR_RTC_BASE + 0x0054) /* RTC interrupt enable */
1069 #define AR_RTC_INTR_MASK (AR_RTC_BASE + 0x0058) /* RTC interrupt mask */
1073 // MAC PCU Registers
1074 #define AR_STA_ID0 0x8000 // MAC station ID0 - low 32 bits
1075 #define AR_STA_ID1 0x8004 // MAC station ID1 - upper 16 bits
1076 #define AR_STA_ID1_SADH_MASK 0x0000FFFF // Mask for 16 msb of MAC addr
1077 #define AR_STA_ID1_STA_AP 0x00010000 // Device is AP
1078 #define AR_STA_ID1_ADHOC 0x00020000 // Device is ad-hoc
1079 #define AR_STA_ID1_PWR_SAV 0x00040000 // Power save in generated frames
1080 #define AR_STA_ID1_KSRCHDIS 0x00080000 // Key search disable
1081 #define AR_STA_ID1_PCF 0x00100000 // Observe PCF
1082 #define AR_STA_ID1_USE_DEFANT 0x00200000 // Use default antenna
1083 #define AR_STA_ID1_DEFANT_UPDATE 0x00400000 // Update default ant w/TX antenna
1084 #define AR_STA_ID1_RTS_USE_DEF 0x00800000 // Use default antenna to send RTS
1085 #define AR_STA_ID1_ACKCTS_6MB 0x01000000 // Use 6Mb/s rate for ACK & CTS
1086 #define AR_STA_ID1_BASE_RATE_11B 0x02000000 // Use 11b base rate for ACK & CTS
1087 #define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000 // default ant for generated frames
1088 #define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000 // Enable Michael
1089 #define AR_STA_ID1_KSRCH_MODE 0x10000000 // Look-up unique key when !keyID
1090 #define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 // Don't replace seq num
1091 #define AR_STA_ID1_CBCIV_ENDIAN 0x40000000 // IV endian-ness in CBC nonce
1092 #define AR_STA_ID1_MCAST_KSRCH 0x80000000 // Adhoc key search enable
1094 #define AR_BSS_ID0 0x8008 // MAC BSSID low 32 bits
1095 #define AR_BSS_ID1 0x800C // MAC BSSID upper 16 bits / AID
1096 #define AR_BSS_ID1_U16 0x0000FFFF // Mask for upper 16 bits of BSSID
1097 #define AR_BSS_ID1_AID 0x07FF0000 // Mask for association ID
1098 #define AR_BSS_ID1_AID_S 16 // Shift for association ID
1100 #define AR_BCN_RSSI_AVE 0x8010 // MAC Beacon average RSSI
1101 #define AR_BCN_RSSI_AVE_MASK 0x00000FFF // Beacon RSSI mask
1103 #define AR_TIME_OUT 0x8014 // MAC ACK & CTS time-out
1104 #define AR_TIME_OUT_ACK 0x00003FFF // Mask for ACK time-out
1105 #define AR_TIME_OUT_ACK_S 0
1106 #define AR_TIME_OUT_CTS 0x3FFF0000 // Mask for CTS time-out
1107 #define AR_TIME_OUT_CTS_S 16
1109 #define AR_RSSI_THR 0x8018 // beacon RSSI warning / bmiss threshold
1110 #define AR_RSSI_THR_MASK 0x000000FF // Beacon RSSI warning threshold
1111 #define AR_RSSI_THR_BM_THR 0x0000FF00 // Mask for Missed beacon threshold
1112 #define AR_RSSI_THR_BM_THR_S 8 // Shift for Missed beacon threshold
1113 #define AR_RSSI_BCN_WEIGHT 0x1F000000 // RSSI average weight
1114 #define AR_RSSI_BCN_WEIGHT_S 24
1115 #define AR_RSSI_BCN_RSSI_RST 0x20000000 // Reset RSSI value
1117 #define AR_USEC 0x801c // MAC transmit latency register
1118 #define AR_USEC_USEC 0x0000007F // Mask for clock cycles in 1 usec
1119 #define AR_USEC_TX_LAT 0x007FC000 // tx latency to start of SIGNAL (usec)
1120 #define AR_USEC_TX_LAT_S 14 // tx latency to start of SIGNAL (usec)
1121 #define AR_USEC_RX_LAT 0x1F800000 // rx latency to start of SIGNAL (usec)
1122 #define AR_USEC_RX_LAT_S 23 // rx latency to start of SIGNAL (usec)
1124 #define AR_RESET_TSF 0x8020
1125 #define AR_RESET_TSF_ONCE 0x01000000 // reset tsf once ; self-clears bit
1127 #define AR_MAX_CFP_DUR 0x8038 // MAC maximum CFP duration
1128 #define AR_CFP_VAL 0x0000FFFF // CFP value in uS
1130 #define AR_RX_FILTER 0x803C // MAC receive filter register
1131 #define AR_RX_FILTER_ALL 0x00000000 // Disallow all frames
1132 #define AR_RX_UCAST 0x00000001 // Allow unicast frames
1133 #define AR_RX_MCAST 0x00000002 // Allow multicast frames
1134 #define AR_RX_BCAST 0x00000004 // Allow broadcast frames
1135 #define AR_RX_CONTROL 0x00000008 // Allow control frames
1136 #define AR_RX_BEACON 0x00000010 // Allow beacon frames
1137 #define AR_RX_PROM 0x00000020 // Promiscuous mode all packets
1138 #define AR_RX_PROBE_REQ 0x00000080 // Any probe request frameA
1139 #define AR_RX_MY_BEACON 0x00000200 // Any beacon frame with matching BSSID
1140 #define AR_RX_COMPR_BAR 0x00000400 // Compressed directed block ack request
1141 #define AR_RX_COMPR_BA 0x00000800 // Compressed directed block ack
1142 #define AR_RX_UNCOM_BA_BAR 0x00001000 // Uncompressed directed BA or BAR
1145 #define AR_RX_XR_POLL 0x00000040 // Allow XR Poll frames
1147 #define AR_RX_PROBE_REQ 0x00000080 // Allow probe request frames
1148 #define AR_RX_MY_BEACON 0x00000200 // Allow beacons with matching BSSID
1150 #define AR_MCAST_FIL0 0x8040 // MAC multicast filter lower 32 bits
1151 #define AR_MCAST_FIL1 0x8044 // MAC multicast filter upper 32 bits
1153 #define AR_DIAG_SW 0x8048 // MAC PCU control register
1154 #define AR_DIAG_CACHE_ACK 0x00000001 // disable ACK when no valid key
1155 #define AR_DIAG_ACK_DIS 0x00000002 // disable ACK generation
1156 #define AR_DIAG_CTS_DIS 0x00000004 // disable CTS generation
1157 #define AR_DIAG_ENCRYPT_DIS 0x00000008 // disable encryption
1158 #define AR_DIAG_DECRYPT_DIS 0x00000010 // disable decryption
1159 #define AR_DIAG_RX_DIS 0x00000020 // disable receive
1160 #define AR_DIAG_LOOP_BACK 0x00000040 // enable loopback
1161 #define AR_DIAG_CORR_FCS 0x00000080 // corrupt FCS
1162 #define AR_DIAG_CHAN_INFO 0x00000100 // dump channel info
1164 #define AR_DIAG_EN_SCRAMSD 0x00000200 // enable fixed scrambler seed
1166 #define AR_DIAG_SCRAM_SEED 0x0001FE00 // Mask for fixed scrambler seed
1167 #define AR_DIAG_SCRAM_SEED_S 8 // Shift for fixed scrambler seed
1168 #define AR_DIAG_FRAME_NV0 0x00020000 // accept w/protocol version !0
1169 #define AR_DIAG_OBS_PT_SEL1 0x000C0000 // observation point select
1170 #define AR_DIAG_OBS_PT_SEL1_S 18 // Shift for observation point select
1171 #define AR_DIAG_FORCE_RX_CLEAR 0x00100000 // force rx_clear high
1172 #define AR_DIAG_IGNORE_VIRT_CS 0x00200000 // ignore virtual carrier sense
1173 #define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000 // force channel idle high
1174 #define AR_DIAG_EIFS_CTRL_ENA 0x00800000 // use framed and ~wait_wep if 0
1175 #define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 // dual chain channel info
1176 #define AR_DIAG_RX_ABORT 0x02000000 // abort rx
1177 #define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000 // saturate cycle cnts (no shift)
1178 #define AR_DIAG_OBS_PT_SEL2 0x08000000 // Mask for observation point sel
1179 #define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000 // force rx_clear (ctl) low (i.e. busy)
1180 #define AR_DIAG_RX_CLEAR_EXT_LOW 0x20000000 // force rx_clear (ext) low (i.e. busy)
1182 #define AR_TSF_L32 0x804c // MAC local clock lower 32 bits
1183 #define AR_TSF_U32 0x8050 // MAC local clock upper 32 bits
1185 #define AR_TST_ADDAC 0x8054 // ADDAC test register
1186 #define AR_DEF_ANTENNA 0x8058 // default antenna register
1188 #define AR_DEF_ANT_CHN_SEL 0x4 // Default Ant Chain Select bit
1189 #define AR_DEF_ANT_CHN0_ANT 0x1 // Def Ant Chain 0 Antenna Select bit
1190 #define AR_DEF_ANT_CHN1_ANT 0x2 // Def Ant Chain 1 Antenna Select bit
1193 #define AR_AES_MUTE_MASK0 0x805c // MAC AES mute mask
1194 #define AR_AES_MUTE_MASK0_FC 0x0000FFFF // frame ctrl mask bits
1195 #define AR_AES_MUTE_MASK0_QOS 0xFFFF0000 // qos ctrl mask bits
1196 #define AR_AES_MUTE_MASK0_QOS_S 16
1198 #define AR_AES_MUTE_MASK1 0x8060 // MAC AES mute mask
1199 #define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF // seq + frag mask bits
1201 #define AR_GATED_CLKS 0x8064 // control clock domain
1202 #define AR_GATED_CLKS_TX 0x00000002
1203 #define AR_GATED_CLKS_RX 0x00000004
1204 #define AR_GATED_CLKS_REG 0x00000008
1206 #define AR_OBS_BUS_CTRL 0x8068 // select a bus for observation
1207 #define AR_OBS_BUS_SEL_1 0x00040000
1208 #define AR_OBS_BUS_SEL_2 0x00080000
1209 #define AR_OBS_BUS_SEL_3 0x000C0000
1210 #define AR_OBS_BUS_SEL_4 0x08040000
1211 #define AR_OBS_BUS_SEL_5 0x08080000
1213 #define AR_OBS_BUS_1 0x806c // mac debug observation bus
1214 #define AR_OBS_BUS_1_PCU 0x00000001
1215 #define AR_OBS_BUS_1_RX_END 0x00000002
1216 #define AR_OBS_BUS_1_RX_WEP 0x00000004
1217 #define AR_OBS_BUS_1_RX_BEACON 0x00000008
1218 #define AR_OBS_BUS_1_RX_FILTER 0x00000010
1219 #define AR_OBS_BUS_1_TX_HCF 0x00000020
1220 #define AR_OBS_BUS_1_QUIET_TIME 0x00000040
1221 #define AR_OBS_BUS_1_CHAN_IDLE 0x00000080
1222 #define AR_OBS_BUS_1_TX_HOLD 0x00000100
1223 #define AR_OBS_BUS_1_TX_FRAME 0x00000200
1224 #define AR_OBS_BUS_1_RX_FRAME 0x00000400
1225 #define AR_OBS_BUS_1_RX_CLEAR 0x00000800
1226 #define AR_OBS_BUS_1_WEP_STATE 0x0003F000
1227 #define AR_OBS_BUS_1_WEP_STATE_S 12
1228 #define AR_OBS_BUS_1_RX_STATE 0x01F00000
1229 #define AR_OBS_BUS_1_RX_STATE_S 20
1230 #define AR_OBS_BUS_1_TX_STATE 0x7E000000
1231 #define AR_OBS_BUS_1_TX_STATE_S 25
1233 #define AR_LAST_TSTP 0x8080 // MAC Time stamp of the last beacon received
1234 #define AR_NAV 0x8084 // MAC current NAV value
1235 #define AR_RTS_OK 0x8088 // MAC RTS exchange success counter
1236 #define AR_RTS_FAIL 0x808c // MAC RTS exchange failure counter
1237 #define AR_ACK_FAIL 0x8090 // MAC ACK failure counter
1238 #define AR_FCS_FAIL 0x8094 // FCS check failure counter
1239 #define AR_BEACON_CNT 0x8098 // Valid beacon counter
1242 #define AR_XRMODE 0x80c0 // Extended range mode
1243 #define AR_XRMODE_XR_POLL_TYPE_M 0x00000003 // poll type mask
1244 #define AR_XRMODE_XR_POLL_TYPE_S 0
1245 #define AR_XRMODE_XR_POLL_SUBTYPE_M 0x0000003c // poll type mask
1246 #define AR_XRMODE_XR_POLL_SUBTYPE_S 2
1247 #define AR_XRMODE_XR_WAIT_FOR_POLL 0x00000080 // wait for poll sta only
1248 #define AR_XRMODE_XR_FRAME_HOLD_M 0xfff00000 // cycles hold for chirps
1249 #define AR_XRMODE_XR_FRAME_HOLD_S 20
1251 #define AR_XRDEL 0x80c4 // Extended range delay
1252 #define AR_XRDEL_SLOT_DELAY_M 0x0000ffff // cycles
1253 #define AR_XRDEL_SLOT_DELAY_S 0
1254 #define AR_XRDEL_CHIRP_DATA_DELAY_M 0xffff0000 // cycles
1255 #define AR_XRDEL_CHIRP_DATA_DELAY_S 16
1257 #define AR_XRTO 0x80c8 // Extended range timeout
1258 #define AR_XRTO_CHIRP_TO_M 0x0000ffff // cycles
1259 #define AR_XRTO_CHIRP_TO_S 0
1260 #define AR_XRTO_POLL_TO_M 0xffff0000 // cycles
1261 #define AR_XRTO_POLL_TO_S 16
1263 #define AR_XRCRP 0x80cc // Extended range chirp
1264 #define AR_XRCRP_SEND_CHIRP 0x00000001 // generate stand alone chirp
1265 #define AR_XRCRP_CHIRP_GAP_M 0xffff0000 // cycles
1266 #define AR_XRCRP_CHIRP_GAP_S 16
1268 #define AR_XRSTMP 0x80d0 // Extended range stomp
1269 #define AR_XRSTMP_RX_ABORT_RSSI 0x00000001 // stomp low rssi receive
1270 #define AR_XRSTMP_RX_ABORT_BSSID 0x00000002 // stomp foreign bssid receive
1271 #define AR_XRSTMP_TX_STOMP_RSSI 0x00000004 // xmit stomp low rssi receive
1272 #define AR_XRSTMP_TX_STOMP_BSSID 0x00000008 // xmit stomp foreign bssid rx
1273 #define AR_XRSTMP_TX_STOMP_DATA 0x00000010 // xmit stomp receive data
1274 #define AR_XRSTMP_RX_ABORT_DATA 0x00000020 // stomp receive data
1275 #define AR_XRSTMP_TX_RSSI_THRESH_M 0x0000FF00 // threshold for tx stomp
1276 #define AR_XRSTMP_TX_RSSI_THRESH_S 8
1277 #define AR_XRSTMP_RX_RSSI_THRESH_M 0x00FF0000 // threshold for tx stomp
1278 #define AR_XRSTMP_RX_RSSI_THRESH_S 16
1281 #define AR_SLEEP1 0x80d4 // Enhanced sleep control 1
1283 #define AR_SLEEP1_NEXT_DTIM_M 0x0007ffff // Absolute time(1/8TU) for next dtim mask
1284 #define AR_SLEEP1_NEXT_DTIM_S 0 // Absolute time(1/8TU) for next dtim shift
1286 #define AR_SLEEP1_ASSUME_DTIM 0x00080000 // Assume DTIM on missed beacon
1288 #define AR_SLEEP1_ENH_SLEEP_ENABLE 0x00100000 // Enables Venice sleep logic
1290 #define AR_SLEEP1_CAB_TIMEOUT 0xFFE00000 // Cab timeout(TU) mask
1291 #define AR_SLEEP1_CAB_TIMEOUT_S 21 // Cab timeout(TU) shift
1293 #define AR_SLEEP2 0x80d8 // Enhanced sleep control 2
1295 #define AR_SLEEP2_NEXT_TIM_M 0x0007ffff // Absolute time(1/8TU) for next tim/beacon mask
1296 #define AR_SLEEP2_NEXT_TIM_S 0 // Absolute time(1/8TU) for next tim/beacon shift
1298 #define AR_SLEEP2_BEACON_TIMEOUT 0xFFE00000 // Beacon timeout(TU) mask
1299 #define AR_SLEEP2_BEACON_TIMEOUT_S 21 // Beacon timeout(TU) shift
1302 #define AR_SLEEP3 0x80dc // Enhanced sleep control 3
1303 #define AR_SLEEP3_TIM_PERIOD_M 0x0000ffff // Tim/Beacon period(TU) mask
1304 #define AR_SLEEP3_TIM_PERIOD_S 0 // Tim/Beacon period(TU) shift
1305 #define AR_SLEEP3_DTIM_PERIOD_M 0xffff0000 // DTIM period(TU) mask
1306 #define AR_SLEEP3_DTIM_PERIOD_S 16 // DTIM period(TU) shift
1309 #define AR_BSSMSKL 0x80e0 // BSSID mask lower 32 bits
1310 #define AR_BSSMSKU 0x80e4 // BSSID mask upper 16 bits
1312 #define AR_TPC 0x80e8 // Transmit power control for gen frames
1313 #define AR_TPC_ACK 0x0000003f // ack frames mask
1314 #define AR_TPC_ACK_S 0x00 // ack frames shift
1315 #define AR_TPC_CTS 0x00003f00 // cts frames mask
1316 #define AR_TPC_CTS_S 0x08 // cts frames shift
1317 #define AR_TPC_CHIRP 0x003f0000 // chirp frames mask
1318 #define AR_TPC_CHIRP_S 0x16 // chirp frames shift
1320 #define AR_TFCNT 0x80ec // Profile count transmit frames
1321 #define AR_RFCNT 0x80f0 // Profile count receive frames
1322 #define AR_RCCNT 0x80f4 // Profile count receive clear
1323 #define AR_CCCNT 0x80f8 // Profile count cycle counter
1325 #define AR_QUIET1 0x80fc // Quiet time programming for TGh
1327 #define AR_QUIET1_NEXT_QUIET_S 0 // TSF of next quiet period (TU)
1328 #define AR_QUIET1_NEXT_QUIET_M 0x0000ffff
1329 #define AR_QUIET1_QUIET_ENABLE 0x00010000 // Enable Quiet time operation
1331 #define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000 // ack/cts in quiet period
1332 #define AR_QUIET2 0x8100 // More Quiet programming
1334 #define AR_QUIET2_QUIET_PERIOD_S 0 // Periodicity of quiet period (TU)
1335 #define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff
1337 #define AR_QUIET2_QUIET_DURATION_S 16 // quiet period (TU)
1338 #define AR_QUIET2_QUIET_DURATION 0xffff0000
1340 #define AR_TSF_PARM 0x8104 // TSF parameters
1341 #define AR_TSF_INCREMENT_M 0x000000ff
1342 #define AR_TSF_INCREMENT_S 0x00
1344 #define AR_QOS_NO_ACK 0x8108 // locate no_ack in qos
1345 #define AR_QOS_NO_ACK_TWO_BIT 0x0000000f // 2 bit sentinel for no-ack
1346 #define AR_QOS_NO_ACK_TWO_BIT_S 0
1347 #define AR_QOS_NO_ACK_BIT_OFF 0x00000070 // offset for no-ack
1348 #define AR_QOS_NO_ACK_BIT_OFF_S 4
1349 #define AR_QOS_NO_ACK_BYTE_OFF 0x00000180 // from end of header
1350 #define AR_QOS_NO_ACK_BYTE_OFF_S 7
1352 #define AR_PHY_ERR 0x810c // Phy errors to be filtered
1353 /* XXX validate! XXX */
1354 #define AR_PHY_ERR_DCHIRP 0x00000008 // Bit 3 enables double chirp
1355 #define AR_PHY_ERR_RADAR 0x00000020 // Bit 5 is Radar signal
1356 #define AR_PHY_ERR_OFDM_TIMING 0x00020000 // Bit 17 is false detect for OFDM
1357 #define AR_PHY_ERR_CCK_TIMING 0x02000000 // Bit 25 is false detect for CCK
1359 #define AR_RXFIFO_CFG 0x8114
1361 /* XXX sub-fields? XXX */
1362 #define AR_MIC_QOS_CONTROL 0x8118
1363 #define AR_MIC_QOS_SELECT 0x811c
1365 #define AR_PCU_MISC 0x8120 // PCU Miscellaneous Mode
1366 #define AR_PCU_FORCE_BSSID_MATCH 0x00000001 // force bssid to match
1367 #define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 // tx/rx mic key are together
1368 #define AR_PCU_TX_ADD_TSF 0x00000008 // add tx_tsf + int_tsf
1369 #define AR_PCU_CCK_SIFS_MODE 0x00000010 // assume 11b sifs programmed
1370 #define AR_PCU_RX_ANT_UPDT 0x00000800 // KC_RX_ANT_UPDATE
1371 #define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 // enforce txop / tbtt
1372 #define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 // count bmiss's when sleeping
1373 #define AR_PCU_BUG_12306_FIX_ENA 0x00020000 // use rx_clear to count sifs
1374 #define AR_PCU_FORCE_QUIET_COLL 0x00040000 // kill xmit for channel change
1375 #define AR_PCU_BT_ANT_PREVENT_RX 0x00100000
1376 #define AR_PCU_TBTT_PROTECT 0x00200000 // no xmit upto tbtt + 20 uS
1377 #define AR_PCU_CLEAR_VMF 0x01000000 // clear vmf mode (fast cc)
1378 #define AR_PCU_CLEAR_BA_VALID 0x04000000 // clear ba state
1381 #define AR_FILT_OFDM 0x8124
1382 #define AR_FILT_OFDM_COUNT 0x00FFFFFF // count of filtered ofdm
1384 #define AR_FILT_CCK 0x8128
1385 #define AR_FILT_CCK_COUNT 0x00FFFFFF // count of filtered cck
1387 #define AR_PHY_ERR_1 0x812c
1388 #define AR_PHY_ERR_1_COUNT 0x00FFFFFF // phy errs that pass mask_1
1389 #define AR_PHY_ERR_MASK_1 0x8130 // mask for err_1_count
1391 #define AR_PHY_ERR_2 0x8134
1392 #define AR_PHY_ERR_2_COUNT 0x00FFFFFF // phy errs that pass mask_2
1393 #define AR_PHY_ERR_MASK_2 0x8138 // mask for err_2_count
1395 #define AR_PHY_COUNTMAX (3 << 22) // Max counted before intr
1396 #define AR_MIBCNT_INTRMASK (3 << 22) // Mask top 2 bits of counters
1398 #define AR_TSF_THRESHOLD 0x813c // interrupt if rx_tsf-int_tsf
1399 #define AR_TSF_THRESHOLD_VAL 0x0000FFFF // exceeds threshold
1401 #define AR_PHY_ERR_EIFS_MASK 0x8144 // phy_errs causing eifs delay
1403 #define AR_PHY_ERR_3 0x8168
1404 #define AR_PHY_ERR_3_COUNT 0x00FFFFFF // phy errs that pass mask_3
1405 #define AR_PHY_ERR_MASK_3 0x816c // mask for err_3_count
1407 #define AR_BT_COEX_MODE 0x8170
1408 #define AR_BT_TIME_EXTEND 0x000000ff
1409 #define AR_BT_TIME_EXTEND_S 0
1410 #define AR_BT_TXSTATE_EXTEND 0x00000100
1411 #define AR_BT_TXSTATE_EXTEND_S 8
1412 #define AR_BT_TX_FRAME_EXTEND 0x00000200
1413 #define AR_BT_TX_FRAME_EXTEND_S 9
1414 #define AR_BT_MODE 0x00000c00
1415 #define AR_BT_MODE_S 10
1416 #define AR_BT_QUIET 0x00001000
1417 #define AR_BT_QUIET_S 12
1418 #define AR_BT_QCU_THRESH 0x0001e000
1419 #define AR_BT_QCU_THRESH_S 13
1420 #define AR_BT_RX_CLEAR_POLARITY 0x00020000
1421 #define AR_BT_RX_CLEAR_POLARITY_S 17
1422 #define AR_BT_PRIORITY_TIME 0x00fc0000
1423 #define AR_BT_PRIORITY_TIME_S 18
1424 #define AR_BT_FIRST_SLOT_TIME 0xff000000
1425 #define AR_BT_FIRST_SLOT_TIME_S 24
1427 #define AR_BT_COEX_WEIGHT 0x8174
1428 #define AR_BT_BT_WGHT 0x0000ffff
1429 #define AR_BT_BT_WGHT_S 0
1430 #define AR_BT_WL_WGHT 0xffff0000
1431 #define AR_BT_WL_WGHT_S 16
1433 #define AR_TXSIFS 0x81d0
1434 #define AR_TXSIFS_TIME 0x000000FF // uS in SIFS
1435 #define AR_TXSIFS_TX_LATENCY 0x00000F00 // uS for transmission thru bb
1436 #define AR_TXSIFS_TX_LATENCY_S 8
1437 #define AR_TXSIFS_ACK_SHIFT 0x00007000 // chan width for ack
1438 #define AR_TXSIFS_ACK_SHIFT_S 12
1440 #define AR_TXOP_X 0x81ec // txop for legacy non-qos
1441 #define AR_TXOP_X_VAL 0x000000FF
1443 /* on-demand subfields */
1444 #define AR_TXOP_0_3 0x81f0 // txop for various tid's
1445 #define AR_TXOP_4_7 0x81f4
1446 #define AR_TXOP_8_11 0x81f8
1447 #define AR_TXOP_12_15 0x81fc
1450 #define AR_KC_MASK 0x81c4 // MAC Key Cache Mask for words 0x10 0x14
1451 // 0 is write allow 1 is write blocked
1452 #define AR_KC_MASK_TYPE_M 0x00000007 // MAC Key Cache Type Mask
1453 #define AR_KC_MASK_LAST_TX_ANT 0x00000008 // MAC Key Cache Last Tx Ant Mask
1454 #define AR_KC_MASK_ASYNC_MASK_M 0x000001f0 // MAC Key Cache Async Rate Offset Mask
1455 #define AR_KC_MASK_UPDT_BF 0x00000200 // MAC Key Cache Update Bf coef Mask
1456 #define AR_KC_MASK_RX_CHAIN0_ACK 0x00000400 // MAC Key Cache Ack Ant Ch 0 Mask
1457 #define AR_KC_MASK_RX_CHAIN1_ACK 0x00000800 // MAC Key Cache Ack Ant Ch 1 Mask
1458 #define AR_KC_MASK_TX_CHAIN0_SEL 0x00001000 // MAC Key Cache Tx Sel Ant Ch 0 Mask
1459 #define AR_KC_MASK_TX_CHAIN1_SEL 0x00002000 // MAC Key Cache Tx Sel Ant Ch 1 Mask
1460 #define AR_KC_MASK_CHAIN_SEL 0x00004000 // MAC Key Cache Chain Sel Mask
1461 #define AR_KC_MASK_WORD_10 0x00010000 // MAC Key Cache Word 0x10 Mask
1464 /* generic timers based on tsf - all uS */
1465 #define AR_NEXT_TBTT_TIMER 0x8200
1466 #define AR_NEXT_DMA_BEACON_ALERT 0x8204
1467 #define AR_NEXT_SWBA 0x8208
1468 #define AR_NEXT_CFP 0x8208
1469 #define AR_NEXT_HCF 0x820C
1470 #define AR_NEXT_TIM 0x8210
1471 #define AR_NEXT_DTIM 0x8214
1472 #define AR_NEXT_QUIET_TIMER 0x8218
1473 #define AR_NEXT_NDP_TIMER 0x821C
1475 #define AR_BEACON_PERIOD 0x8220
1476 #define AR_DMA_BEACON_PERIOD 0x8224
1477 #define AR_SWBA_PERIOD 0x8228
1478 #define AR_HCF_PERIOD 0x822C
1479 #define AR_TIM_PERIOD 0x8230
1480 #define AR_DTIM_PERIOD 0x8234
1481 #define AR_QUIET_PERIOD 0x8238
1482 #define AR_NDP_PERIOD 0x823C
1484 #define AR_TIMER_MODE 0x8240
1485 #define AR_TBTT_TIMER_EN 0x00000001
1486 #define AR_DBA_TIMER_EN 0x00000002
1487 #define AR_SWBA_TIMER_EN 0x00000004
1488 #define AR_HCF_TIMER_EN 0x00000008
1489 #define AR_TIM_TIMER_EN 0x00000010
1490 #define AR_DTIM_TIMER_EN 0x00000020
1491 #define AR_QUIET_TIMER_EN 0x00000040
1492 #define AR_NDP_TIMER_EN 0x00000080
1493 #define AR_TIMER_OVERFLOW_INDEX 0x00000700
1494 #define AR_TIMER_OVERFLOW_INDEX_S 8
1495 #define AR_TIMER_THRESH 0xFFFFF000
1496 #define AR_TIMER_THRESH_S 12
1498 #define AR_SLP32_MODE 0x8244
1499 #define AR_SLP32_HALF_CLK_LATENCY 0x000FFFFF // rising <-> falling edge
1500 #define AR_SLP32_ENA 0x00100000
1501 #define AR_SLP32_TSF_WRITE_STATUS 0x00200000 // tsf update in progress
1503 #define AR_SLP32_WAKE 0x8248
1504 #define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF // time to wake crystal
1506 #define AR_SLP32_INC 0x824c
1507 #define AR_SLP32_TST_INC 0x000FFFFF
1509 #define AR_SLP_CNT 0x8250 // 32kHz cycles for which mac is asleep
1510 #define AR_SLP_CYCLE_CNT 0x8254 // absolute number of 32kHz cycles
1512 #define AR_SLP_MIB_CTRL 0x8258
1513 #define AR_SLP_MIB_CLEAR 0x00000001 // clear pending
1514 #define AR_SLP_MIB_PENDING 0x00000002 // clear counters
1516 #ifdef AR5416_EMULATION
1517 // MAC trace buffer registers (emulation only)
1518 #define AR_MAC_PCU_LOGIC_ANALYZER 0x8264
1519 #define AR_MAC_PCU_LOGIC_ANALYZER_CTL 0x0000000F
1520 #define AR_MAC_PCU_LOGIC_ANALYZER_HOLD 0x00000001
1521 #define AR_MAC_PCU_LOGIC_ANALYZER_CLEAR 0x00000002
1522 #define AR_MAC_PCU_LOGIC_ANALYZER_STATE 0x00000004
1523 #define AR_MAC_PCU_LOGIC_ANALYZER_ENABLE 0x00000008
1524 #define AR_MAC_PCU_LOGIC_ANALYZER_QCU_SEL 0x000000F0
1525 #define AR_MAC_PCU_LOGIC_ANALYZER_QCU_SEL_S 4
1526 #define AR_MAC_PCU_LOGIC_ANALYZER_INT_ADDR 0x0003FF00
1527 #define AR_MAC_PCU_LOGIC_ANALYZER_INT_ADDR_S 8
1529 #define AR_MAC_PCU_LOGIC_ANALYZER_DIAG_MODE 0xFFFC0000
1530 #define AR_MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_S 18
1531 #define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20614 0x00040000
1532 #define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000
1533 #define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20803 0x40000000
1535 #define AR_MAC_PCU_LOGIC_ANALYZER_32L 0x8268
1536 #define AR_MAC_PCU_LOGIC_ANALYZER_16U 0x826C
1538 #define AR_MAC_PCU_TRACE_REG_START 0xE000
1539 #define AR_MAC_PCU_TRACE_REG_END 0xFFFC
1540 #define AR_MAC_PCU_TRACE_BUFFER_LENGTH (AR_MAC_PCU_TRACE_REG_END - AR_MAC_PCU_TRACE_REG_START + sizeof(a_uint32_t))
1541 #endif // AR5416_EMULATION
1543 #define AR_2040_MODE 0x8318
1544 #define AR_2040_JOINED_RX_CLEAR 0x00000001 // use ctl + ext rx_clear for cca
1546 /* Additional cycle counter. See also AR_CCCNT */
1547 #define AR_EXTRCCNT 0x8328 // extension channel rx clear count
1548 // counts number of cycles rx_clear (ext) is low (i.e. busy)
1549 // when the MAC is not actively transmitting/receiving
1551 #define AR_SELFGEN_MASK 0x832c
1555 #define AR_FRM_TYPE_CAP_TBL 0x8500 // Frame Type Capabilities Table
1556 #define AR_FRM_TYPE_CAP_SIZE 64 // Frame Type Cap. Table Size
1557 #define AR_FTC_BF_RX_UPDT_NORM 0x00000001 // BFCOEF_RX_UPDATE_NORMAL
1558 #define AR_FTC_BF_RX_UPDT_SELF 0x00000002 // BFCOEF_RX_UPDATE_SELF_GEN
1559 #define AR_FTC_BF_TX_ENB_NORM 0x00000004 // BFCOEF_TX_ENABLE_NORMAL
1560 #define AR_FTC_BF_TX_ENB_SELF 0x00000008 // BFCOEF_TX_ENABLE_SELF_GEN
1561 #define AR_FTC_BF_TX_ENB_GEN 0x00000010 // BFCOEF_TX_ENABLE_GEN
1562 #define AR_FTC_BF_TX_ENB_MCAST 0x00000020 // BFCOEF_TX_ENABLE_MCAST
1564 // rate duration registers - used for Multi-rate retry.
1565 #define AR_RATE_DURATION_0 0x8700 // 32 registers from 0x8700 to 0x87CC
1566 #define AR_RATE_DURATION_31 0x87CC
1569 #define AR_KEYTABLE_0 0x8800 /* MAC Key Cache */
1570 #define AR_KEYTABLE(_n) (AR_KEYTABLE_0 + ((_n)*32))
1571 #define AR_KEY_CACHE_SIZE 128
1572 #define AR_RSVD_KEYTABLE_ENTRIES 4
1573 #define AR_KEY_TYPE 0x00000007 // MAC Key Type Mask
1574 #define AR_KEYTABLE_TYPE_40 0x00000000 /* WEP 40 bit key */
1575 #define AR_KEYTABLE_TYPE_104 0x00000001 /* WEP 104 bit key */
1576 #define AR_KEYTABLE_TYPE_128 0x00000003 /* WEP 128 bit key */
1577 #define AR_KEYTABLE_TYPE_TKIP 0x00000004 /* TKIP and Michael */
1578 #define AR_KEYTABLE_TYPE_AES 0x00000005 /* AES/OCB 128 bit key */
1579 #define AR_KEYTABLE_TYPE_CCM 0x00000006 /* AES/CCM 128 bit key */
1580 #define AR_KEYTABLE_TYPE_CLR 0x00000007 /* no encryption */
1581 #define AR_KEYTABLE_ANT 0x00000008 /* previous transmit antenna */
1582 #define AR_KEYTABLE_VALID 0x00008000 /* key and MAC address valid */
1583 #define AR_KEYTABLE_KEY0(_n) (AR_KEYTABLE(_n) + 0) /* key bit 0-31 */
1584 #define AR_KEYTABLE_KEY1(_n) (AR_KEYTABLE(_n) + 4) /* key bit 32-47 */
1585 #define AR_KEYTABLE_KEY2(_n) (AR_KEYTABLE(_n) + 8) /* key bit 48-79 */
1586 #define AR_KEYTABLE_KEY3(_n) (AR_KEYTABLE(_n) + 12) /* key bit 80-95 */
1587 #define AR_KEYTABLE_KEY4(_n) (AR_KEYTABLE(_n) + 16) /* key bit 96-127 */
1588 #define AR_KEYTABLE_TYPE(_n) (AR_KEYTABLE(_n) + 20) /* key type */
1589 #define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24) /* MAC address 1-32 */
1590 #define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28) /* MAC address 33-47 */
1592 #define BT_WGHT 0xff55
1593 #define STOMP_ALL_WLAN_WGHT 0xfcfc
1594 #define STOMP_LOW_WLAN_WGHT 0xa8a8
1595 #define STOMP_NONE_WLAN_WGHT 0x0000