2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include "ah_internal.h"
39 #include "ar5416reg.h"
40 #include "ar5416desc.h"
42 #define N(a) (sizeof(a)/sizeof(a[0]))
43 #define AR_INTR_SPURIOUS 0xffffffff
44 #define ar5416_desc ar5416_desc_20
45 #define AR5416_ABORT_LOOPS 1000
46 #define AR5416_ABORT_WAIT 5
47 #define AR5416DESC AR5416DESC_20
48 #define AR5416DESC_CONST AR5416DESC_CONST_20
54 static const struct ath_hal_private ar5416hal_10 = {{
55 .ah_getRateTable = ar5416GetRateTable,
56 .ah_detach = ar5416Detach,
58 /* Transmit functions */
59 .ah_updateTxTrigLevel = ar5416UpdateTxTrigLevel,
60 .ah_setTxDP = ar5416SetTxDP,
61 .ah_numTxPending = ar5416NumTxPending,
62 .ah_startTxDma = ar5416StartTxDma,
63 .ah_stopTxDma = ar5416StopTxDma,
65 .ah_abortTxDma = ar5416AbortTxDma,
68 .ah_getTsf64 = ar5416GetTsf64,
69 .ah_setRxFilter = ar5416SetRxFilter,
72 .ah_setRxDP = ar5416SetRxDP,
73 .ah_stopDmaReceive = ar5416StopDmaReceive,
74 .ah_enableReceive = ar5416EnableReceive,
75 .ah_stopPcuReceive = ar5416StopPcuReceive,
77 /* Interrupt Functions */
78 .ah_isInterruptPending = ar5416IsInterruptPending,
79 .ah_getPendingInterrupts = ar5416GetPendingInterrupts,
80 .ah_setInterrupts = ar5416SetInterrupts,
84 void ar5416Detach(struct ath_hal *ah)
86 HALASSERT(ah != AH_NULL);
91 ar5416Attach(a_uint32_t devid,HAL_SOFTC sc, adf_os_device_t dev,
92 a_uint32_t flags, HAL_STATUS *status)
94 struct ath_hal_5416 *ahp;
97 ahp = ath_hal_malloc(sizeof (struct ath_hal_5416));
102 ah = &ahp->ah_priv.h;
104 OS_MEMCPY(&ahp->ah_priv, &ar5416hal_10, sizeof(struct ath_hal_private));
109 /* If its a Owl 2.0 chip then change the hal structure to
110 point to the Owl 2.0 ar5416_hal_20 structure */
112 ah->ah_set11nTxDesc = ar5416Set11nTxDesc_20;
113 ah->ah_set11nRateScenario = ar5416Set11nRateScenario_20;
114 ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst_20;
115 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle_20;
116 ah->ah_set11nAggrLast = ar5416Set11nAggrLast_20;
117 ah->ah_clr11nAggr = ar5416Clr11nAggr_20;
118 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration_20;
119 ah->ah_setupRxDesc = ar5416SetupRxDesc_20;
120 ah->ah_procRxDescFast = ar5416ProcRxDescFast_20;
121 ah->ah_updateCTSForBursting = NULL;
122 ah->ah_setupTxDesc = ar5416SetupTxDesc_20;
123 ah->ah_reqTxIntrDesc = ar5416IntrReqTxDesc_20;
124 ah->ah_fillTxDesc = ar5416FillTxDesc_20;
125 ah->ah_fillKeyTxDesc = ar5416FillKeyTxDesc_20;
126 ah->ah_procTxDesc = ar5416ProcTxDesc_20;
127 ah->ah_set11nVirtualMoreFrag = ar5416Set11nVirtualMoreFrag_20;
133 /**********************/
134 /* Interrupt Handling */
135 /**********************/
137 HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah)
139 a_uint32_t host_isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE);
141 * Some platforms trigger our ISR before applying power to
142 * the card, so make sure.
144 return ((host_isr != AR_INTR_SPURIOUS) && (host_isr & AR_INTR_MAC_IRQ));
147 HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
151 HAL_BOOL fatal_int = AH_FALSE;
152 a_uint32_t sync_cause;
154 if (OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
155 if ((OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) != AR_RTC_STATUS_ON) {
164 isr = OS_REG_READ(ah, AR_ISR_RAC);
165 if (isr == 0xffffffff) {
170 *masked = isr & HAL_INT_COMMON;
172 #ifdef AR5416_INT_MITIGATION
173 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) {
174 *masked |= HAL_INT_RX;
176 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) {
177 *masked |= HAL_INT_TX;
181 if (isr & AR_ISR_BCNMISC) {
184 s2_s = OS_REG_READ(ah, AR_ISR_S2_S);
186 if (s2_s & AR_ISR_S2_GTT) {
187 *masked |= HAL_INT_GTT;
190 if (s2_s & AR_ISR_S2_CST) {
191 *masked |= HAL_INT_CST;
195 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
196 *masked |= HAL_INT_RX;
197 if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) {
198 struct ath_hal_5416 *ahp = AH5416(ah);
199 a_uint32_t s0_s, s1_s;
201 *masked |= HAL_INT_TX;
202 s0_s = OS_REG_READ(ah, AR_ISR_S0_S);
203 s1_s = OS_REG_READ(ah, AR_ISR_S1_S);
204 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
205 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
206 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
207 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
211 sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
212 fatal_int = ((sync_cause != AR_INTR_SPURIOUS) &&
213 (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))) ?
216 if (AH_TRUE == fatal_int) {
217 OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
218 (void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
225 ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
227 struct ath_hal_5416 *ahp = AH5416(ah);
228 a_uint32_t omask = ahp->ah_maskReg;
231 if (omask & HAL_INT_GLOBAL) {
232 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
233 (void) OS_REG_READ(ah, AR_IER);
236 mask = ints & HAL_INT_COMMON;
237 if (ints & HAL_INT_TX) {
238 #ifdef AR5416_INT_MITIGATION
239 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
242 mask |= AR_IMR_TXDESC;
244 mask |= AR_IMR_TXERR;
245 mask |= AR_IMR_TXEOL;
247 if (ints & HAL_INT_RX) {
248 mask |= AR_IMR_RXERR;
249 #ifdef AR5416_INT_MITIGATION
250 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
252 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
256 if (ints & (HAL_INT_GTT | HAL_INT_CST)) {
257 mask |= AR_IMR_BCNMISC;
260 OS_REG_WRITE(ah, AR_IMR, mask);
261 (void) OS_REG_READ(ah, AR_IMR);
262 ahp->ah_maskReg = ints;
264 /* Re-enable interrupts if they were enabled before. */
265 if (ints & HAL_INT_GLOBAL) {
266 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
267 /* See explanation above... */
268 (void) OS_REG_READ(ah, AR_IER);
271 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
272 OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
273 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ALL);
282 u_int64_t ar5416GetTsf64(struct ath_hal *ah)
286 tsf = OS_REG_READ(ah, AR_TSF_U32);
287 tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32);
295 void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp)
297 OS_REG_WRITE(ah, AR_RXDP, rxdp);
298 HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
301 void ar5416SetMulticastFilter(struct ath_hal *ah, a_uint32_t filter0, a_uint32_t filter1)
303 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
304 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
307 HAL_BOOL ar5416ClrMulticastFilterIndex(struct ath_hal *ah, a_uint32_t ix)
314 val = OS_REG_READ(ah, AR_MCAST_FIL1);
315 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
317 val = OS_REG_READ(ah, AR_MCAST_FIL0);
318 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
323 HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah)
325 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
326 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
333 HAL_BOOL ar5416SetMulticastFilterIndex(struct ath_hal *ah, a_uint32_t ix)
340 val = OS_REG_READ(ah, AR_MCAST_FIL1);
341 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));
343 val = OS_REG_READ(ah, AR_MCAST_FIL0);
344 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));
349 void ar5416SetRxFilter(struct ath_hal *ah, a_uint32_t bits)
353 OS_REG_WRITE(ah, AR_RX_FILTER, (bits & 0xff) | AR_RX_COMPR_BAR);
355 if (bits & HAL_RX_FILTER_PHYRADAR)
356 phybits |= AR_PHY_ERR_RADAR;
357 if (bits & HAL_RX_FILTER_PHYERR)
358 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
359 OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
361 OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
363 OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
367 void ar5416EnableReceive(struct ath_hal *ah)
369 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
372 void ar5416StopPcuReceive(struct ath_hal *ah)
374 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
377 HAL_BOOL ar5416SetupRxDesc_20(struct ath_hal *ah, struct ath_rx_desc *ds,
378 a_uint32_t size, a_uint32_t flags)
380 struct ar5416_desc *ads = AR5416DESC(ds);
382 HALASSERT((size &~ AR_BufLen) == 0);
384 ads->ds_ctl1 = size & AR_BufLen;
385 if (flags & HAL_RXDESC_INTREQ)
386 ads->ds_ctl1 |= AR_RxIntrReq;
388 /* this should be enough */
389 ads->ds_rxstatus8 &= ~AR_RxDone;
394 HAL_STATUS ar5416ProcRxDescFast_20(struct ath_hal *ah, struct ath_rx_desc *ds,
395 a_uint32_t pa, struct ath_desc *nds,
396 struct ath_rx_status *rx_stats)
398 struct ar5416_desc ads;
399 struct ar5416_desc *adsp = AR5416DESC(ds);
400 struct ar5416_desc *ands = AR5416DESC(nds);
402 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
403 return HAL_EINPROGRESS;
405 * Given the use of a self-linked tail be very sure that the hw is
406 * done with this descriptor; the hw may have done this descriptor
407 * once and picked it up again...make sure the hw has moved on.
409 if ((ands->ds_rxstatus8 & AR_RxDone) == 0
410 && OS_REG_READ(ah, AR_RXDP) == pa)
411 return HAL_EINPROGRESS;
414 * Now we need to get the stats from the descriptor. Since desc are
415 * uncached, lets make a copy of the stats first. Note that, since we
416 * touch most of the rx stats, a memcpy would always be more efficient
418 * Next we fill in all values in a caller passed stack variable.
419 * This reduces the number of uncached accesses.
420 * Do this copy here, after the check so that when the checks fail, we
421 * dont end up copying the entire stats uselessly.
423 ads.u.rx = adsp->u.rx;
425 rx_stats->rs_status = 0;
426 rx_stats->rs_flags = 0;
428 rx_stats->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
429 rx_stats->rs_tstamp = ads.AR_RcvTimestamp;
431 /* XXX what about KeyCacheMiss? */
432 rx_stats->rs_rssi_combined =
433 MS(ads.ds_rxstatus4, AR_RxRSSICombined);
434 rx_stats->rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00);
435 rx_stats->rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01);
436 rx_stats->rs_rssi_ctl2 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt02);
437 rx_stats->rs_rssi_ext0 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt10);
438 rx_stats->rs_rssi_ext1 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt11);
439 rx_stats->rs_rssi_ext2 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt12);
440 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
441 rx_stats->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
443 rx_stats->rs_keyix = HAL_RXKEYIX_INVALID;
444 /* NB: caller expected to do rate table mapping */
445 rx_stats->rs_rate = RXSTATUS_RATE(ah, (&ads));
446 rx_stats->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
448 rx_stats->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
449 rx_stats->rs_moreaggr = (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
450 rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_GI) ? HAL_RX_GI : 0;
451 rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_2040) ? HAL_RX_2040 : 0;
453 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
454 rx_stats->rs_flags |= HAL_RX_DELIM_CRC_PRE;
455 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
456 rx_stats->rs_flags |= HAL_RX_DELIM_CRC_POST;
457 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
458 rx_stats->rs_flags |= HAL_RX_DECRYPT_BUSY;
460 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
462 * These four bits should not be set together. The
463 * 5416 spec states a Michael error can only occur if
464 * DecryptCRCErr not set (and TKIP is used). Experience
465 * indicates however that you can also get Michael errors
466 * when a CRC error is detected, but these are specious.
467 * Consequently we filter them out here so we don't
468 * confuse and/or complicate drivers.
470 if (ads.ds_rxstatus8 & AR_CRCErr)
471 rx_stats->rs_status |= HAL_RXERR_CRC;
472 else if (ads.ds_rxstatus8 & AR_PHYErr) {
475 rx_stats->rs_status |= HAL_RXERR_PHY;
476 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
477 rx_stats->rs_phyerr = phyerr;
478 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
479 rx_stats->rs_status |= HAL_RXERR_DECRYPT;
480 else if (ads.ds_rxstatus8 & AR_MichaelErr)
481 rx_stats->rs_status |= HAL_RXERR_MIC;
483 rx_stats->evm0=ads.AR_RxEVM0;
484 rx_stats->evm1=ads.AR_RxEVM1;
485 rx_stats->evm2=ads.AR_RxEVM2;
494 HAL_BOOL ar5416UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
496 struct ath_hal_5416 *ahp = AH5416(ah);
497 a_uint32_t txcfg, curLevel, newLevel;
501 * Disable interrupts while futzing with the fifo level.
503 omask = ar5416SetInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL);
505 txcfg = OS_REG_READ(ah, AR_TXCFG);
506 curLevel = MS(txcfg, AR_FTRIG);
510 if (curLevel < MAX_TX_FIFO_THRESHOLD)
512 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
514 if (newLevel != curLevel)
515 OS_REG_WRITE(ah, AR_TXCFG,
516 (txcfg &~ AR_FTRIG) | SM(newLevel, AR_FTRIG));
518 /* re-enable chip interrupts */
519 ar5416SetInterrupts(ah, omask);
521 return (newLevel != curLevel);
524 HAL_BOOL ar5416SetTxDP(struct ath_hal *ah, a_uint32_t q, a_uint32_t txdp)
526 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
527 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
530 * Make sure that TXE is deasserted before setting the TXDP. If TXE
531 * is still asserted, setting TXDP will have no effect.
533 HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0);
535 OS_REG_WRITE(ah, AR_QTXDP(q), txdp);
540 HAL_BOOL ar5416StartTxDma(struct ath_hal *ah, a_uint32_t q)
542 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
543 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
545 /* Check to be sure we're not enabling a q that has its TXD bit set. */
546 HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1 << q)) == 0);
548 OS_REG_WRITE(ah, AR_Q_TXE, 1 << q);
553 a_uint32_t ar5416NumTxPending(struct ath_hal *ah, a_uint32_t q)
557 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
558 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
560 npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
563 * Pending frame count (PFC) can momentarily go to zero
564 * while TXE remains asserted. In other words a PFC of
565 * zero is not sufficient to say that the queue has stopped.
567 if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q))
571 if (npend && (AH5416(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) {
572 if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) {
573 isrPrintf("RTSD on CAB queue\n");
574 /* Clear the ReadyTime shutdown status bits */
575 OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q);
582 HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah)
587 * set txd on all queues
589 OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
594 OS_REG_SET_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF));
595 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
596 OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
599 * wait on all tx queues
601 for (q = 0; q < AR_NUM_QCU; q++) {
602 for (i = 0; i < AR5416_ABORT_LOOPS; i++) {
603 if (!ar5416NumTxPending(ah, q))
606 OS_DELAY(AR5416_ABORT_WAIT);
608 if (i == AR5416_ABORT_LOOPS) {
614 * clear tx abort bits
616 OS_REG_CLR_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF));
617 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
618 OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
623 OS_REG_WRITE(ah, AR_Q_TXD, 0);
628 HAL_BOOL ar5416StopTxDma(struct ath_hal*ah, a_uint32_t q)
632 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
634 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
636 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
637 for (i = 1000; i != 0; i--) {
638 if (ar5416NumTxPending(ah, q) == 0)
640 OS_DELAY(100); /* XXX get actual value */
643 OS_REG_WRITE(ah, AR_Q_TXD, 0);
647 void ar5416IntrReqTxDesc_20(struct ath_hal *ah, struct ath_desc *ds)
649 struct ar5416_desc *ads = AR5416DESC(ds);
650 ads->ds_ctl0 |= AR_TxIntrReq;
653 HAL_BOOL ar5416SetupTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
658 a_uint32_t txRate0, a_uint32_t txTries0,
662 a_uint32_t rtsctsRate,
663 a_uint32_t rtsctsDuration,
664 a_uint32_t compicvLen,
665 a_uint32_t compivLen,
668 #define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
670 struct ar5416_desc *ads = AR5416DESC(ds);
674 ads->ds_txstatus9 &= ~AR_TxDone;
676 HALASSERT(txTries0 != 0);
677 HALASSERT(isValidPktType(type));
678 HALASSERT(isValidTxRate(txRate0));
679 HALASSERT((flags & RTSCTS) != RTSCTS);
684 ads->ds_ctl0 = (pktLen & AR_FrameLen)
685 | (txPower << AR_XmitPower_S)
686 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
687 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
688 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0);
690 ads->ds_ctl1 = (type << AR_FrameType_S)
691 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0);
692 ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0);
693 ads->ds_ctl3 = (txRate0 << AR_XmitRate0_S);
695 ads->ds_ctl7 = SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel0)
696 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel1)
697 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel2)
698 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel3);
700 if (keyIx != HAL_TXKEYIX_INVALID) {
701 /* XXX validate key index */
702 ads->ds_ctl1 |= SM(keyIx, AR_DestIdx);
703 ads->ds_ctl0 |= AR_DestIdxValid;
706 if (flags & RTSCTS) {
707 if (!isValidTxRate(rtsctsRate)) {
710 /* XXX validate rtsctsDuration */
711 ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0)
712 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0);
713 ads->ds_ctl2 |= SM(rtsctsDuration, AR_BurstDur);
714 ads->ds_ctl3 |= (rtsctsRate << AR_RTSCTSRate_S);
721 HAL_BOOL ar5416FillTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
722 a_uint32_t segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
723 const struct ath_tx_desc *ds0)
725 struct ar5416_desc *ads = AR5416DESC(ds);
727 HALASSERT((segLen &~ AR_BufLen) == 0);
731 * First descriptor, don't clobber xmit control data
732 * setup by ar5416SetupTxDesc.
734 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
735 } else if (lastSeg) {
737 * Last descriptor in a multi-descriptor frame,
738 * copy the multi-rate transmit parameters from
739 * the first frame for processing on completion.
742 ads->ds_ctl1 = segLen;
743 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
744 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
747 * Intermediate descriptor in a multi-descriptor frame.
750 ads->ds_ctl1 = segLen | AR_TxMore;
754 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
759 HAL_BOOL ar5416FillKeyTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
760 HAL_KEY_TYPE keyType)
762 struct ar5416_desc *ads = AR5416DESC(ds);
764 ads->ds_ctl6 = SM(keyType, AR_EncrType);
768 HAL_STATUS ar5416ProcTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *gds)
770 struct ar5416_desc *ads = AR5416DESC(gds);
771 struct ath_tx_desc *ds = (struct ath_tx_desc *)gds;
773 if ((ads->ds_txstatus9 & AR_TxDone) == 0)
774 return HAL_EINPROGRESS;
776 ads->ds_txstatus9 &= ~AR_TxDone;
778 /* Update software copies of the HW status */
779 ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
780 ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp;
781 ds->ds_txstat.ts_status = 0;
782 ds->ds_txstat.ts_flags = 0;
784 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
785 ds->ds_txstat.ts_status |= HAL_TXERR_XRETRY;
786 if (ads->ds_txstatus1 & AR_Filtered)
787 ds->ds_txstat.ts_status |= HAL_TXERR_FILT;
788 if (ads->ds_txstatus1 & AR_FIFOUnderrun)
789 ds->ds_txstat.ts_status |= HAL_TXERR_FIFO;
790 if (ads->ds_txstatus9 & AR_TxOpExceeded)
791 ds->ds_txstat.ts_status |= HAL_TXERR_XTXOP;
792 if (ads->ds_txstatus1 & AR_TxTimerExpired)
793 ds->ds_txstat.ts_status |= HAL_TXERR_TIMER_EXPIRED;
795 if (ads->ds_txstatus1 & AR_DescCfgErr)
796 ds->ds_txstat.ts_flags |= HAL_TX_DESC_CFG_ERR;
797 if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
798 ds->ds_txstat.ts_flags |= HAL_TX_DATA_UNDERRUN;
799 ar5416UpdateTxTrigLevel(ah, AH_TRUE);
801 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
802 ds->ds_txstat.ts_flags |= HAL_TX_DELIM_UNDERRUN;
803 ar5416UpdateTxTrigLevel(ah, AH_TRUE);
805 if (ads->ds_txstatus0 & AR_TxBaStatus) {
806 ds->ds_txstat.ts_flags |= HAL_TX_BA;
807 ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
808 ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
812 * Extract the transmit rate used and mark the rate as
813 * ``alternate'' if it wasn't the series 0 rate.
815 ds->ds_txstat.ts_rate = MS(ads->ds_txstatus9, AR_FinalTxIdx);
816 ds->ds_txstat.ts_rssi_combined =
817 MS(ads->ds_txstatus5, AR_TxRSSICombined);
818 ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
819 ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
820 ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
821 ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
822 ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
823 ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
824 ds->ds_txstat.evm0 = ads->AR_TxEVM0;
825 ds->ds_txstat.evm1 = ads->AR_TxEVM1;
826 ds->ds_txstat.evm2 = ads->AR_TxEVM2;
827 ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
828 ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
829 ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
830 ds->ds_txstat.ts_antenna = 0; /* ignored for owl */
835 void ar5416Set11nTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
836 a_uint32_t pktLen, HAL_PKT_TYPE type, a_uint32_t txPower,
837 a_uint32_t keyIx, HAL_KEY_TYPE keyType,
840 struct ar5416_desc *ads = AR5416DESC(ds);
842 HALASSERT(isValidPktType(type));
843 HALASSERT(isValidKeyType(keyType));
848 ads->ds_ctl0 = (pktLen & AR_FrameLen)
849 | (flags & HAL_TXDESC_VMF ? AR_VirtMoreFrag : 0)
850 | SM(txPower, AR_XmitPower)
851 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0)
852 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
853 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
854 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0)
855 | (keyIx != HAL_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
856 | (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0);
858 ads->ds_ctl1 = (keyIx != HAL_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
859 | SM(type, AR_FrameType)
860 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0)
861 | (flags & HAL_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
862 | (flags & HAL_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
864 ads->ds_ctl6 = SM(keyType, AR_EncrType);
869 void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_tx_desc *ds,
870 a_uint32_t durUpdateEn, a_uint32_t rtsctsRate,
871 a_uint32_t rtsctsDuration,
872 HAL_11N_RATE_SERIES series[], a_uint32_t nseries,
875 struct ar5416_desc *ads = AR5416DESC(ds);
878 HALASSERT(nseries == 4);
882 * Rate control settings override
884 ds_ctl0 = ads->ds_ctl0;
886 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
887 if (flags & HAL_TXDESC_RTSENA) {
888 ds_ctl0 &= ~AR_CTSEnable;
889 ds_ctl0 |= AR_RTSEnable;
891 ds_ctl0 &= ~AR_RTSEnable;
892 ds_ctl0 |= AR_CTSEnable;
895 ds_ctl0 = (ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
898 ads->ds_ctl0 = ds_ctl0;
900 ads->ds_ctl2 = set11nTries(series, 0)
901 | set11nTries(series, 1)
902 | set11nTries(series, 2)
903 | set11nTries(series, 3)
904 | (durUpdateEn ? AR_DurUpdateEn : 0);
906 ads->ds_ctl3 = set11nRate(series, 0)
907 | set11nRate(series, 1)
908 | set11nRate(series, 2)
909 | set11nRate(series, 3);
911 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
912 | set11nPktDurRTSCTS(series, 1);
914 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
915 | set11nPktDurRTSCTS(series, 3);
917 ads->ds_ctl7 = set11nRateFlags(series, 0)
918 | set11nRateFlags(series, 1)
919 | set11nRateFlags(series, 2)
920 | set11nRateFlags(series, 3)
921 | SM(rtsctsRate, AR_RTSCTSRate);
926 void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_tx_desc *ds,
927 a_uint32_t durUpdateEn, a_uint32_t rtsctsRate,
928 a_uint32_t rtsctsDuration,
929 HAL_11N_RATE_SERIES series[], a_uint32_t nseries,
932 struct ar5416_desc *ads = AR5416DESC(ds);
935 HALASSERT(nseries == 4);
939 * Rate control settings override
941 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
942 ds_ctl0 = ads->ds_ctl0;
944 if (flags & HAL_TXDESC_RTSENA) {
945 ds_ctl0 &= ~AR_CTSEnable;
946 ds_ctl0 |= AR_RTSEnable;
948 ds_ctl0 &= ~AR_RTSEnable;
949 ds_ctl0 |= AR_CTSEnable;
952 ads->ds_ctl0 = ds_ctl0;
955 ads->ds_ctl2 = set11nTries(series, 0)
956 | set11nTries(series, 1)
957 | set11nTries(series, 2)
958 | set11nTries(series, 3)
959 | (durUpdateEn ? AR_DurUpdateEn : 0);
961 ads->ds_ctl3 = set11nRate(series, 0)
962 | set11nRate(series, 1)
963 | set11nRate(series, 2)
964 | set11nRate(series, 3);
966 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
967 | set11nPktDurRTSCTS(series, 1);
969 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
970 | set11nPktDurRTSCTS(series, 3);
972 ads->ds_ctl7 = set11nRateFlags(series, 0)
973 | set11nRateFlags(series, 1)
974 | set11nRateFlags(series, 2)
975 | set11nRateFlags(series, 3)
976 | SM(rtsctsRate, AR_RTSCTSRate);
981 void ar5416Set11nAggrFirst_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uint32_t aggrLen,
982 a_uint32_t numDelims)
984 struct ar5416_desc *ads = AR5416DESC(ds);
986 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
988 ads->ds_ctl6 &= ~(AR_AggrLen | AR_PadDelim);
989 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen) |
990 SM(numDelims, AR_PadDelim);
993 void ar5416Set11nAggrMiddle_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uint32_t numDelims)
995 struct ar5416_desc *ads = AR5416DESC(ds);
998 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
1001 * We use a stack variable to manipulate ctl6 to reduce uncached
1002 * read modify, modfiy, write.
1004 ctl6 = ads->ds_ctl6;
1005 ctl6 &= ~AR_PadDelim;
1006 ctl6 |= SM(numDelims, AR_PadDelim);
1007 ads->ds_ctl6 = ctl6;
1010 void ar5416Set11nAggrLast_20(struct ath_hal *ah, struct ath_tx_desc *ds)
1012 struct ar5416_desc *ads = AR5416DESC(ds);
1014 ads->ds_ctl1 |= AR_IsAggr;
1015 ads->ds_ctl1 &= ~AR_MoreAggr;
1016 ads->ds_ctl6 &= ~AR_PadDelim;
1019 void ar5416Clr11nAggr_20(struct ath_hal *ah, struct ath_tx_desc *ds)
1021 struct ar5416_desc *ads = AR5416DESC(ds);
1023 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
1026 void ar5416Set11nBurstDuration_20(struct ath_hal *ah, struct ath_tx_desc *ds,
1027 a_uint32_t burstDuration)
1029 struct ar5416_desc *ads = AR5416DESC(ds);
1031 ads->ds_ctl2 &= ~AR_BurstDur;
1032 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
1035 void ar5416Set11nVirtualMoreFrag_20(struct ath_hal *ah, struct ath_tx_desc *ds,
1038 struct ar5416_desc *ads = AR5416DESC(ds);
1041 ads->ds_ctl0 |= AR_VirtMoreFrag;
1043 ads->ds_ctl0 &= ~AR_VirtMoreFrag;