2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
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37 #include "ah_internal.h"
39 #include "ar5416reg.h"
40 #include "ar5416desc.h"
42 #define N(a) (sizeof(a)/sizeof(a[0]))
43 #define AR_INTR_SPURIOUS 0xffffffff
44 #define ar5416_desc ar5416_desc_20
45 #define AR5416_ABORT_LOOPS 1000
46 #define AR5416_ABORT_WAIT 5
47 #define AR5416DESC AR5416DESC_20
48 #define AR5416DESC_CONST AR5416DESC_CONST_20
54 static const struct ath_hal_private ar5416hal_10 = {{
55 .ah_getRateTable = ar5416GetRateTable,
56 .ah_detach = ar5416Detach,
58 /* Transmit functions */
59 .ah_updateTxTrigLevel = ar5416UpdateTxTrigLevel,
60 .ah_setTxDP = ar5416SetTxDP,
61 .ah_numTxPending = ar5416NumTxPending,
62 .ah_startTxDma = ar5416StartTxDma,
63 .ah_stopTxDma = ar5416StopTxDma,
65 .ah_abortTxDma = ar5416AbortTxDma,
68 .ah_getTsf64 = ar5416GetTsf64,
69 .ah_setRxFilter = ar5416SetRxFilter,
72 .ah_setRxDP = ar5416SetRxDP,
73 .ah_stopDmaReceive = ar5416StopDmaReceive,
74 .ah_enableReceive = ar5416EnableReceive,
75 .ah_stopPcuReceive = ar5416StopPcuReceive,
77 /* Interrupt Functions */
78 .ah_isInterruptPending = ar5416IsInterruptPending,
79 .ah_getPendingInterrupts = ar5416GetPendingInterrupts,
80 .ah_setInterrupts = ar5416SetInterrupts,
84 void ar5416Detach(struct ath_hal *ah)
86 HALASSERT(ah != AH_NULL);
91 ar5416Attach(a_uint32_t devid,HAL_SOFTC sc, adf_os_device_t dev,
92 a_uint32_t flags, HAL_STATUS *status)
94 struct ath_hal_5416 *ahp;
97 ahp = ath_hal_malloc(sizeof (struct ath_hal_5416));
102 ah = &ahp->ah_priv.h;
104 OS_MEMCPY(&ahp->ah_priv, &ar5416hal_10, sizeof(struct ath_hal_private));
109 /* If its a Owl 2.0 chip then change the hal structure to
110 point to the Owl 2.0 ar5416_hal_20 structure */
112 ah->ah_set11nTxDesc = ar5416Set11nTxDesc_20;
113 ah->ah_set11nRateScenario = ar5416Set11nRateScenario_20;
114 ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst_20;
115 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle_20;
116 ah->ah_set11nAggrLast = ar5416Set11nAggrLast_20;
117 ah->ah_clr11nAggr = ar5416Clr11nAggr_20;
118 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration_20;
119 ah->ah_setupRxDesc = ar5416SetupRxDesc_20;
120 ah->ah_procRxDescFast = ar5416ProcRxDescFast_20;
121 ah->ah_setupTxDesc = ar5416SetupTxDesc_20;
122 ah->ah_reqTxIntrDesc = ar5416IntrReqTxDesc_20;
123 ah->ah_fillTxDesc = ar5416FillTxDesc_20;
124 ah->ah_fillKeyTxDesc = ar5416FillKeyTxDesc_20;
125 ah->ah_procTxDesc = ar5416ProcTxDesc_20;
126 ah->ah_set11nVirtualMoreFrag = ar5416Set11nVirtualMoreFrag_20;
132 /**********************/
133 /* Interrupt Handling */
134 /**********************/
136 HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah)
138 a_uint32_t host_isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE);
140 * Some platforms trigger our ISR before applying power to
141 * the card, so make sure.
143 return ((host_isr != AR_INTR_SPURIOUS) && (host_isr & AR_INTR_MAC_IRQ));
146 HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
150 HAL_BOOL fatal_int = AH_FALSE;
151 a_uint32_t sync_cause;
153 if (OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
154 if ((OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) != AR_RTC_STATUS_ON) {
163 isr = OS_REG_READ(ah, AR_ISR_RAC);
164 if (isr == 0xffffffff) {
169 *masked = isr & HAL_INT_COMMON;
171 #ifdef AR5416_INT_MITIGATION
172 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) {
173 *masked |= HAL_INT_RX;
175 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) {
176 *masked |= HAL_INT_TX;
180 if (isr & AR_ISR_BCNMISC) {
183 s2_s = OS_REG_READ(ah, AR_ISR_S2_S);
185 if (s2_s & AR_ISR_S2_GTT) {
186 *masked |= HAL_INT_GTT;
189 if (s2_s & AR_ISR_S2_CST) {
190 *masked |= HAL_INT_CST;
194 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
195 *masked |= HAL_INT_RX;
196 if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) {
197 struct ath_hal_5416 *ahp = AH5416(ah);
198 a_uint32_t s0_s, s1_s;
200 *masked |= HAL_INT_TX;
201 s0_s = OS_REG_READ(ah, AR_ISR_S0_S);
202 s1_s = OS_REG_READ(ah, AR_ISR_S1_S);
203 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
204 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
205 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
206 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
210 sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
211 fatal_int = ((sync_cause != AR_INTR_SPURIOUS) &&
212 (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))) ?
215 if (AH_TRUE == fatal_int) {
216 OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
217 (void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
224 ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
226 struct ath_hal_5416 *ahp = AH5416(ah);
227 a_uint32_t omask = ahp->ah_maskReg;
230 if (omask & HAL_INT_GLOBAL) {
231 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
232 (void) OS_REG_READ(ah, AR_IER);
235 mask = ints & HAL_INT_COMMON;
236 if (ints & HAL_INT_TX) {
237 #ifdef AR5416_INT_MITIGATION
238 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
241 mask |= AR_IMR_TXDESC;
243 mask |= AR_IMR_TXERR;
244 mask |= AR_IMR_TXEOL;
246 if (ints & HAL_INT_RX) {
247 mask |= AR_IMR_RXERR;
248 #ifdef AR5416_INT_MITIGATION
249 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
251 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
255 if (ints & (HAL_INT_GTT | HAL_INT_CST)) {
256 mask |= AR_IMR_BCNMISC;
259 OS_REG_WRITE(ah, AR_IMR, mask);
260 (void) OS_REG_READ(ah, AR_IMR);
261 ahp->ah_maskReg = ints;
263 /* Re-enable interrupts if they were enabled before. */
264 if (ints & HAL_INT_GLOBAL) {
265 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
266 /* See explanation above... */
267 (void) OS_REG_READ(ah, AR_IER);
270 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
271 OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
272 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ALL);
281 u_int64_t ar5416GetTsf64(struct ath_hal *ah)
285 tsf = OS_REG_READ(ah, AR_TSF_U32);
286 tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32);
294 void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp)
296 OS_REG_WRITE(ah, AR_RXDP, rxdp);
297 HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
300 void ar5416SetMulticastFilter(struct ath_hal *ah, a_uint32_t filter0, a_uint32_t filter1)
302 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
303 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
306 HAL_BOOL ar5416ClrMulticastFilterIndex(struct ath_hal *ah, a_uint32_t ix)
313 val = OS_REG_READ(ah, AR_MCAST_FIL1);
314 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
316 val = OS_REG_READ(ah, AR_MCAST_FIL0);
317 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
322 HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah)
324 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
325 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
332 HAL_BOOL ar5416SetMulticastFilterIndex(struct ath_hal *ah, a_uint32_t ix)
339 val = OS_REG_READ(ah, AR_MCAST_FIL1);
340 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));
342 val = OS_REG_READ(ah, AR_MCAST_FIL0);
343 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));
348 void ar5416SetRxFilter(struct ath_hal *ah, a_uint32_t bits)
352 OS_REG_WRITE(ah, AR_RX_FILTER, (bits & 0xff) | AR_RX_COMPR_BAR);
354 if (bits & HAL_RX_FILTER_PHYRADAR)
355 phybits |= AR_PHY_ERR_RADAR;
356 if (bits & HAL_RX_FILTER_PHYERR)
357 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
358 OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
360 OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
362 OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
366 void ar5416EnableReceive(struct ath_hal *ah)
368 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
371 void ar5416StopPcuReceive(struct ath_hal *ah)
373 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
376 HAL_BOOL ar5416SetupRxDesc_20(struct ath_hal *ah, struct ath_rx_desc *ds,
377 a_uint32_t size, a_uint32_t flags)
379 struct ar5416_desc *ads = AR5416DESC(ds);
381 HALASSERT((size &~ AR_BufLen) == 0);
383 ads->ds_ctl1 = size & AR_BufLen;
384 if (flags & HAL_RXDESC_INTREQ)
385 ads->ds_ctl1 |= AR_RxIntrReq;
387 /* this should be enough */
388 ads->ds_rxstatus8 &= ~AR_RxDone;
393 HAL_STATUS ar5416ProcRxDescFast_20(struct ath_hal *ah, struct ath_rx_desc *ds,
394 a_uint32_t pa, struct ath_desc *nds,
395 struct ath_rx_status *rx_stats)
397 struct ar5416_desc ads;
398 struct ar5416_desc *adsp = AR5416DESC(ds);
399 struct ar5416_desc *ands = AR5416DESC(nds);
401 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
402 return HAL_EINPROGRESS;
404 * Given the use of a self-linked tail be very sure that the hw is
405 * done with this descriptor; the hw may have done this descriptor
406 * once and picked it up again...make sure the hw has moved on.
408 if ((ands->ds_rxstatus8 & AR_RxDone) == 0
409 && OS_REG_READ(ah, AR_RXDP) == pa)
410 return HAL_EINPROGRESS;
413 * Now we need to get the stats from the descriptor. Since desc are
414 * uncached, lets make a copy of the stats first. Note that, since we
415 * touch most of the rx stats, a memcpy would always be more efficient
417 * Next we fill in all values in a caller passed stack variable.
418 * This reduces the number of uncached accesses.
419 * Do this copy here, after the check so that when the checks fail, we
420 * dont end up copying the entire stats uselessly.
422 ads.u.rx = adsp->u.rx;
424 rx_stats->rs_status = 0;
425 rx_stats->rs_flags = 0;
427 rx_stats->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
428 rx_stats->rs_tstamp = ads.AR_RcvTimestamp;
430 /* XXX what about KeyCacheMiss? */
431 rx_stats->rs_rssi_combined =
432 MS(ads.ds_rxstatus4, AR_RxRSSICombined);
433 rx_stats->rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00);
434 rx_stats->rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01);
435 rx_stats->rs_rssi_ctl2 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt02);
436 rx_stats->rs_rssi_ext0 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt10);
437 rx_stats->rs_rssi_ext1 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt11);
438 rx_stats->rs_rssi_ext2 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt12);
439 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
440 rx_stats->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
442 rx_stats->rs_keyix = HAL_RXKEYIX_INVALID;
443 /* NB: caller expected to do rate table mapping */
444 rx_stats->rs_rate = RXSTATUS_RATE(ah, (&ads));
445 rx_stats->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
447 rx_stats->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
448 rx_stats->rs_moreaggr = (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
449 rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_GI) ? HAL_RX_GI : 0;
450 rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_2040) ? HAL_RX_2040 : 0;
452 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
453 rx_stats->rs_flags |= HAL_RX_DELIM_CRC_PRE;
454 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
455 rx_stats->rs_flags |= HAL_RX_DELIM_CRC_POST;
456 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
457 rx_stats->rs_flags |= HAL_RX_DECRYPT_BUSY;
459 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
461 * These four bits should not be set together. The
462 * 5416 spec states a Michael error can only occur if
463 * DecryptCRCErr not set (and TKIP is used). Experience
464 * indicates however that you can also get Michael errors
465 * when a CRC error is detected, but these are specious.
466 * Consequently we filter them out here so we don't
467 * confuse and/or complicate drivers.
469 if (ads.ds_rxstatus8 & AR_CRCErr)
470 rx_stats->rs_status |= HAL_RXERR_CRC;
471 else if (ads.ds_rxstatus8 & AR_PHYErr) {
474 rx_stats->rs_status |= HAL_RXERR_PHY;
475 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
476 rx_stats->rs_phyerr = phyerr;
477 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
478 rx_stats->rs_status |= HAL_RXERR_DECRYPT;
479 else if (ads.ds_rxstatus8 & AR_MichaelErr)
480 rx_stats->rs_status |= HAL_RXERR_MIC;
482 rx_stats->evm0=ads.AR_RxEVM0;
483 rx_stats->evm1=ads.AR_RxEVM1;
484 rx_stats->evm2=ads.AR_RxEVM2;
493 HAL_BOOL ar5416UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
495 struct ath_hal_5416 *ahp = AH5416(ah);
496 a_uint32_t txcfg, curLevel, newLevel;
500 * Disable interrupts while futzing with the fifo level.
502 omask = ar5416SetInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL);
504 txcfg = OS_REG_READ(ah, AR_TXCFG);
505 curLevel = MS(txcfg, AR_FTRIG);
509 if (curLevel < MAX_TX_FIFO_THRESHOLD)
511 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
513 if (newLevel != curLevel)
514 OS_REG_WRITE(ah, AR_TXCFG,
515 (txcfg &~ AR_FTRIG) | SM(newLevel, AR_FTRIG));
517 /* re-enable chip interrupts */
518 ar5416SetInterrupts(ah, omask);
520 return (newLevel != curLevel);
523 HAL_BOOL ar5416SetTxDP(struct ath_hal *ah, a_uint32_t q, a_uint32_t txdp)
525 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
526 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
529 * Make sure that TXE is deasserted before setting the TXDP. If TXE
530 * is still asserted, setting TXDP will have no effect.
532 HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0);
534 OS_REG_WRITE(ah, AR_QTXDP(q), txdp);
539 HAL_BOOL ar5416StartTxDma(struct ath_hal *ah, a_uint32_t q)
541 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
542 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
544 /* Check to be sure we're not enabling a q that has its TXD bit set. */
545 HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1 << q)) == 0);
547 OS_REG_WRITE(ah, AR_Q_TXE, 1 << q);
552 a_uint32_t ar5416NumTxPending(struct ath_hal *ah, a_uint32_t q)
556 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
557 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
559 npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
562 * Pending frame count (PFC) can momentarily go to zero
563 * while TXE remains asserted. In other words a PFC of
564 * zero is not sufficient to say that the queue has stopped.
566 if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q))
570 if (npend && (AH5416(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) {
571 if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) {
572 isrPrintf("RTSD on CAB queue\n");
573 /* Clear the ReadyTime shutdown status bits */
574 OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q);
581 HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah)
586 * set txd on all queues
588 OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
593 OS_REG_SET_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF));
594 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
595 OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
598 * wait on all tx queues
600 for (q = 0; q < AR_NUM_QCU; q++) {
601 for (i = 0; i < AR5416_ABORT_LOOPS; i++) {
602 if (!ar5416NumTxPending(ah, q))
605 OS_DELAY(AR5416_ABORT_WAIT);
607 if (i == AR5416_ABORT_LOOPS) {
613 * clear tx abort bits
615 OS_REG_CLR_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF));
616 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
617 OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
622 OS_REG_WRITE(ah, AR_Q_TXD, 0);
627 HAL_BOOL ar5416StopTxDma(struct ath_hal*ah, a_uint32_t q)
631 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
633 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
635 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
636 for (i = 1000; i != 0; i--) {
637 if (ar5416NumTxPending(ah, q) == 0)
639 OS_DELAY(100); /* XXX get actual value */
642 OS_REG_WRITE(ah, AR_Q_TXD, 0);
646 void ar5416IntrReqTxDesc_20(struct ath_hal *ah, struct ath_desc *ds)
648 struct ar5416_desc *ads = AR5416DESC(ds);
649 ads->ds_ctl0 |= AR_TxIntrReq;
652 HAL_BOOL ar5416SetupTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
657 a_uint32_t txRate0, a_uint32_t txTries0,
661 a_uint32_t rtsctsRate,
662 a_uint32_t rtsctsDuration,
663 a_uint32_t compicvLen,
664 a_uint32_t compivLen,
667 #define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
669 struct ar5416_desc *ads = AR5416DESC(ds);
673 ads->ds_txstatus9 &= ~AR_TxDone;
675 HALASSERT(txTries0 != 0);
676 HALASSERT(isValidPktType(type));
677 HALASSERT(isValidTxRate(txRate0));
678 HALASSERT((flags & RTSCTS) != RTSCTS);
683 ads->ds_ctl0 = (pktLen & AR_FrameLen)
684 | (txPower << AR_XmitPower_S)
685 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
686 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
687 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0);
689 ads->ds_ctl1 = (type << AR_FrameType_S)
690 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0);
691 ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0);
692 ads->ds_ctl3 = (txRate0 << AR_XmitRate0_S);
694 ads->ds_ctl7 = SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel0)
695 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel1)
696 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel2)
697 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel3);
699 if (keyIx != HAL_TXKEYIX_INVALID) {
700 /* XXX validate key index */
701 ads->ds_ctl1 |= SM(keyIx, AR_DestIdx);
702 ads->ds_ctl0 |= AR_DestIdxValid;
705 if (flags & RTSCTS) {
706 if (!isValidTxRate(rtsctsRate)) {
709 /* XXX validate rtsctsDuration */
710 ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0)
711 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0);
712 ads->ds_ctl2 |= SM(rtsctsDuration, AR_BurstDur);
713 ads->ds_ctl3 |= (rtsctsRate << AR_RTSCTSRate_S);
720 HAL_BOOL ar5416FillTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
721 a_uint32_t segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
722 const struct ath_tx_desc *ds0)
724 struct ar5416_desc *ads = AR5416DESC(ds);
726 HALASSERT((segLen &~ AR_BufLen) == 0);
730 * First descriptor, don't clobber xmit control data
731 * setup by ar5416SetupTxDesc.
733 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
734 } else if (lastSeg) {
736 * Last descriptor in a multi-descriptor frame,
737 * copy the multi-rate transmit parameters from
738 * the first frame for processing on completion.
741 ads->ds_ctl1 = segLen;
742 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
743 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
746 * Intermediate descriptor in a multi-descriptor frame.
749 ads->ds_ctl1 = segLen | AR_TxMore;
753 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
758 HAL_BOOL ar5416FillKeyTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
759 HAL_KEY_TYPE keyType)
761 struct ar5416_desc *ads = AR5416DESC(ds);
763 ads->ds_ctl6 = SM(keyType, AR_EncrType);
767 HAL_STATUS ar5416ProcTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *gds)
769 struct ar5416_desc *ads = AR5416DESC(gds);
770 struct ath_tx_desc *ds = (struct ath_tx_desc *)gds;
772 if ((ads->ds_txstatus9 & AR_TxDone) == 0)
773 return HAL_EINPROGRESS;
775 ads->ds_txstatus9 &= ~AR_TxDone;
777 /* Update software copies of the HW status */
778 ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
779 ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp;
780 ds->ds_txstat.ts_status = 0;
781 ds->ds_txstat.ts_flags = 0;
783 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
784 ds->ds_txstat.ts_status |= HAL_TXERR_XRETRY;
785 if (ads->ds_txstatus1 & AR_Filtered)
786 ds->ds_txstat.ts_status |= HAL_TXERR_FILT;
787 if (ads->ds_txstatus1 & AR_FIFOUnderrun)
788 ds->ds_txstat.ts_status |= HAL_TXERR_FIFO;
789 if (ads->ds_txstatus9 & AR_TxOpExceeded)
790 ds->ds_txstat.ts_status |= HAL_TXERR_XTXOP;
791 if (ads->ds_txstatus1 & AR_TxTimerExpired)
792 ds->ds_txstat.ts_status |= HAL_TXERR_TIMER_EXPIRED;
794 if (ads->ds_txstatus1 & AR_DescCfgErr)
795 ds->ds_txstat.ts_flags |= HAL_TX_DESC_CFG_ERR;
796 if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
797 ds->ds_txstat.ts_flags |= HAL_TX_DATA_UNDERRUN;
798 ar5416UpdateTxTrigLevel(ah, AH_TRUE);
800 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
801 ds->ds_txstat.ts_flags |= HAL_TX_DELIM_UNDERRUN;
802 ar5416UpdateTxTrigLevel(ah, AH_TRUE);
804 if (ads->ds_txstatus0 & AR_TxBaStatus) {
805 ds->ds_txstat.ts_flags |= HAL_TX_BA;
806 ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
807 ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
811 * Extract the transmit rate used and mark the rate as
812 * ``alternate'' if it wasn't the series 0 rate.
814 ds->ds_txstat.ts_rate = MS(ads->ds_txstatus9, AR_FinalTxIdx);
815 ds->ds_txstat.ts_rssi_combined =
816 MS(ads->ds_txstatus5, AR_TxRSSICombined);
817 ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
818 ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
819 ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
820 ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
821 ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
822 ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
823 ds->ds_txstat.evm0 = ads->AR_TxEVM0;
824 ds->ds_txstat.evm1 = ads->AR_TxEVM1;
825 ds->ds_txstat.evm2 = ads->AR_TxEVM2;
826 ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
827 ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
828 ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
829 ds->ds_txstat.ts_antenna = 0; /* ignored for owl */
834 void ar5416Set11nTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
835 a_uint32_t pktLen, HAL_PKT_TYPE type, a_uint32_t txPower,
836 a_uint32_t keyIx, HAL_KEY_TYPE keyType,
839 struct ar5416_desc *ads = AR5416DESC(ds);
841 HALASSERT(isValidPktType(type));
842 HALASSERT(isValidKeyType(keyType));
847 ads->ds_ctl0 = (pktLen & AR_FrameLen)
848 | (flags & HAL_TXDESC_VMF ? AR_VirtMoreFrag : 0)
849 | SM(txPower, AR_XmitPower)
850 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0)
851 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
852 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
853 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0)
854 | (keyIx != HAL_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
855 | (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0);
857 ads->ds_ctl1 = (keyIx != HAL_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
858 | SM(type, AR_FrameType)
859 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0)
860 | (flags & HAL_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
861 | (flags & HAL_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
863 ads->ds_ctl6 = SM(keyType, AR_EncrType);
868 void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_tx_desc *ds,
869 a_uint32_t durUpdateEn, a_uint32_t rtsctsRate,
870 a_uint32_t rtsctsDuration,
871 HAL_11N_RATE_SERIES series[], a_uint32_t nseries,
874 struct ar5416_desc *ads = AR5416DESC(ds);
877 HALASSERT(nseries == 4);
881 * Rate control settings override
883 ds_ctl0 = ads->ds_ctl0;
885 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
886 if (flags & HAL_TXDESC_RTSENA) {
887 ds_ctl0 &= ~AR_CTSEnable;
888 ds_ctl0 |= AR_RTSEnable;
890 ds_ctl0 &= ~AR_RTSEnable;
891 ds_ctl0 |= AR_CTSEnable;
894 ds_ctl0 = (ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
897 ads->ds_ctl0 = ds_ctl0;
899 ads->ds_ctl2 = set11nTries(series, 0)
900 | set11nTries(series, 1)
901 | set11nTries(series, 2)
902 | set11nTries(series, 3)
903 | (durUpdateEn ? AR_DurUpdateEn : 0);
905 ads->ds_ctl3 = set11nRate(series, 0)
906 | set11nRate(series, 1)
907 | set11nRate(series, 2)
908 | set11nRate(series, 3);
910 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
911 | set11nPktDurRTSCTS(series, 1);
913 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
914 | set11nPktDurRTSCTS(series, 3);
916 ads->ds_ctl7 = set11nRateFlags(series, 0)
917 | set11nRateFlags(series, 1)
918 | set11nRateFlags(series, 2)
919 | set11nRateFlags(series, 3)
920 | SM(rtsctsRate, AR_RTSCTSRate);
925 void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_tx_desc *ds,
926 a_uint32_t durUpdateEn, a_uint32_t rtsctsRate,
927 a_uint32_t rtsctsDuration,
928 HAL_11N_RATE_SERIES series[], a_uint32_t nseries,
931 struct ar5416_desc *ads = AR5416DESC(ds);
934 HALASSERT(nseries == 4);
938 * Rate control settings override
940 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
941 ds_ctl0 = ads->ds_ctl0;
943 if (flags & HAL_TXDESC_RTSENA) {
944 ds_ctl0 &= ~AR_CTSEnable;
945 ds_ctl0 |= AR_RTSEnable;
947 ds_ctl0 &= ~AR_RTSEnable;
948 ds_ctl0 |= AR_CTSEnable;
951 ads->ds_ctl0 = ds_ctl0;
954 ads->ds_ctl2 = set11nTries(series, 0)
955 | set11nTries(series, 1)
956 | set11nTries(series, 2)
957 | set11nTries(series, 3)
958 | (durUpdateEn ? AR_DurUpdateEn : 0);
960 ads->ds_ctl3 = set11nRate(series, 0)
961 | set11nRate(series, 1)
962 | set11nRate(series, 2)
963 | set11nRate(series, 3);
965 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
966 | set11nPktDurRTSCTS(series, 1);
968 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
969 | set11nPktDurRTSCTS(series, 3);
971 ads->ds_ctl7 = set11nRateFlags(series, 0)
972 | set11nRateFlags(series, 1)
973 | set11nRateFlags(series, 2)
974 | set11nRateFlags(series, 3)
975 | SM(rtsctsRate, AR_RTSCTSRate);
980 void ar5416Set11nAggrFirst_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uint32_t aggrLen,
981 a_uint32_t numDelims)
983 struct ar5416_desc *ads = AR5416DESC(ds);
985 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
987 ads->ds_ctl6 &= ~(AR_AggrLen | AR_PadDelim);
988 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen) |
989 SM(numDelims, AR_PadDelim);
992 void ar5416Set11nAggrMiddle_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uint32_t numDelims)
994 struct ar5416_desc *ads = AR5416DESC(ds);
997 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
1000 * We use a stack variable to manipulate ctl6 to reduce uncached
1001 * read modify, modfiy, write.
1003 ctl6 = ads->ds_ctl6;
1004 ctl6 &= ~AR_PadDelim;
1005 ctl6 |= SM(numDelims, AR_PadDelim);
1006 ads->ds_ctl6 = ctl6;
1009 void ar5416Set11nAggrLast_20(struct ath_hal *ah, struct ath_tx_desc *ds)
1011 struct ar5416_desc *ads = AR5416DESC(ds);
1013 ads->ds_ctl1 |= AR_IsAggr;
1014 ads->ds_ctl1 &= ~AR_MoreAggr;
1015 ads->ds_ctl6 &= ~AR_PadDelim;
1018 void ar5416Clr11nAggr_20(struct ath_hal *ah, struct ath_tx_desc *ds)
1020 struct ar5416_desc *ads = AR5416DESC(ds);
1022 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
1025 void ar5416Set11nBurstDuration_20(struct ath_hal *ah, struct ath_tx_desc *ds,
1026 a_uint32_t burstDuration)
1028 struct ar5416_desc *ads = AR5416DESC(ds);
1030 ads->ds_ctl2 &= ~AR_BurstDur;
1031 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
1034 void ar5416Set11nVirtualMoreFrag_20(struct ath_hal *ah, struct ath_tx_desc *ds,
1037 struct ar5416_desc *ads = AR5416DESC(ds);
1040 ads->ds_ctl0 |= AR_VirtMoreFrag;
1042 ads->ds_ctl0 &= ~AR_VirtMoreFrag;