2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
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37 #include "ah_internal.h"
39 #include "ar5416reg.h"
40 #include "ar5416desc.h"
42 #define N(a) (sizeof(a)/sizeof(a[0]))
43 #define AR_INTR_SPURIOUS 0xffffffff
44 #define ar5416_desc ar5416_desc_20
45 #define AR5416_ABORT_LOOPS 1000
46 #define AR5416_ABORT_WAIT 5
47 #define AR5416DESC AR5416DESC_20
48 #define AR5416DESC_CONST AR5416DESC_CONST_20
54 static const struct ath_hal_private ar5416hal_10 = {{
55 .ah_getRateTable = ar5416GetRateTable,
56 .ah_detach = ar5416Detach,
58 /* Transmit functions */
59 .ah_updateTxTrigLevel = ar5416UpdateTxTrigLevel,
60 .ah_setTxDP = ar5416SetTxDP,
61 .ah_numTxPending = ar5416NumTxPending,
62 .ah_startTxDma = ar5416StartTxDma,
63 .ah_stopTxDma = ar5416StopTxDma,
65 .ah_getTxIntrQueue = ar5416GetTxIntrQueue,
66 .ah_abortTxDma = ar5416AbortTxDma,
69 .ah_getTsf32 = ar5416GetTsf32,
70 .ah_getTsf64 = ar5416GetTsf64,
71 .ah_resetTsf = ar5416ResetTsf,
72 .ah_setRxFilter = ar5416SetRxFilter,
75 .ah_getRxDP = ar5416GetRxDP,
76 .ah_setRxDP = ar5416SetRxDP,
77 .ah_stopDmaReceive = ar5416StopDmaReceive,
78 .ah_enableReceive = ar5416EnableReceive,
79 .ah_startPcuReceive = ar5416StartPcuReceive,
80 .ah_stopPcuReceive = ar5416StopPcuReceive,
82 /* Interrupt Functions */
83 .ah_isInterruptPending = ar5416IsInterruptPending,
84 .ah_getPendingInterrupts = ar5416GetPendingInterrupts,
85 .ah_getInterrupts = ar5416GetInterrupts,
86 .ah_setInterrupts = ar5416SetInterrupts,
90 void ar5416Detach(struct ath_hal *ah)
92 HALASSERT(ah != AH_NULL);
97 ar5416Attach(a_uint32_t devid,HAL_SOFTC sc, adf_os_device_t dev,
98 a_uint32_t flags, HAL_STATUS *status)
100 struct ath_hal_5416 *ahp;
103 ahp = ath_hal_malloc(sizeof (struct ath_hal_5416));
104 if (ahp == AH_NULL) {
105 *status = HAL_ENOMEM;
108 ah = &ahp->ah_priv.h;
110 OS_MEMCPY(&ahp->ah_priv, &ar5416hal_10, sizeof(struct ath_hal_private));
115 /* If its a Owl 2.0 chip then change the hal structure to
116 point to the Owl 2.0 ar5416_hal_20 structure */
118 ah->ah_set11nTxDesc = ar5416Set11nTxDesc_20;
119 ah->ah_set11nRateScenario = ar5416Set11nRateScenario_20;
120 ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst_20;
121 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle_20;
122 ah->ah_set11nAggrLast = ar5416Set11nAggrLast_20;
123 ah->ah_clr11nAggr = ar5416Clr11nAggr_20;
124 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration_20;
125 ah->ah_setupRxDesc = ar5416SetupRxDesc_20;
126 ah->ah_procRxDescFast = ar5416ProcRxDescFast_20;
127 ah->ah_updateCTSForBursting = NULL;
128 ah->ah_setupTxDesc = ar5416SetupTxDesc_20;
129 ah->ah_reqTxIntrDesc = ar5416IntrReqTxDesc_20;
130 ah->ah_fillTxDesc = ar5416FillTxDesc_20;
131 ah->ah_fillKeyTxDesc = ar5416FillKeyTxDesc_20;
132 ah->ah_procTxDesc = ar5416ProcTxDesc_20;
133 ah->ah_set11nVirtualMoreFrag = ar5416Set11nVirtualMoreFrag_20;
139 /**********************/
140 /* Interrupt Handling */
141 /**********************/
143 HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah)
145 a_uint32_t host_isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE);
147 * Some platforms trigger our ISR before applying power to
148 * the card, so make sure.
150 return ((host_isr != AR_INTR_SPURIOUS) && (host_isr & AR_INTR_MAC_IRQ));
153 HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
157 HAL_BOOL fatal_int = AH_FALSE;
158 a_uint32_t sync_cause;
160 if (OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
161 if ((OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) != AR_RTC_STATUS_ON) {
170 isr = OS_REG_READ(ah, AR_ISR_RAC);
171 if (isr == 0xffffffff) {
176 *masked = isr & HAL_INT_COMMON;
178 #ifdef AR5416_INT_MITIGATION
179 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) {
180 *masked |= HAL_INT_RX;
182 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) {
183 *masked |= HAL_INT_TX;
187 if (isr & AR_ISR_BCNMISC) {
190 s2_s = OS_REG_READ(ah, AR_ISR_S2_S);
192 if (s2_s & AR_ISR_S2_GTT) {
193 *masked |= HAL_INT_GTT;
196 if (s2_s & AR_ISR_S2_CST) {
197 *masked |= HAL_INT_CST;
201 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
202 *masked |= HAL_INT_RX;
203 if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) {
204 struct ath_hal_5416 *ahp = AH5416(ah);
205 a_uint32_t s0_s, s1_s;
207 *masked |= HAL_INT_TX;
208 s0_s = OS_REG_READ(ah, AR_ISR_S0_S);
209 s1_s = OS_REG_READ(ah, AR_ISR_S1_S);
210 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
211 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
212 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
213 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
217 sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
218 fatal_int = ((sync_cause != AR_INTR_SPURIOUS) &&
219 (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))) ?
222 if (AH_TRUE == fatal_int) {
223 OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
224 (void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
230 HAL_INT ar5416GetInterrupts(struct ath_hal *ah)
232 return AH5416(ah)->ah_maskReg;
236 ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
238 struct ath_hal_5416 *ahp = AH5416(ah);
239 a_uint32_t omask = ahp->ah_maskReg;
242 if (omask & HAL_INT_GLOBAL) {
243 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
244 (void) OS_REG_READ(ah, AR_IER);
247 mask = ints & HAL_INT_COMMON;
248 if (ints & HAL_INT_TX) {
249 #ifdef AR5416_INT_MITIGATION
250 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
253 mask |= AR_IMR_TXDESC;
255 mask |= AR_IMR_TXERR;
256 mask |= AR_IMR_TXEOL;
258 if (ints & HAL_INT_RX) {
259 mask |= AR_IMR_RXERR;
260 #ifdef AR5416_INT_MITIGATION
261 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
263 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
267 if (ints & (HAL_INT_GTT | HAL_INT_CST)) {
268 mask |= AR_IMR_BCNMISC;
271 OS_REG_WRITE(ah, AR_IMR, mask);
272 (void) OS_REG_READ(ah, AR_IMR);
273 ahp->ah_maskReg = ints;
275 /* Re-enable interrupts if they were enabled before. */
276 if (ints & HAL_INT_GLOBAL) {
277 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
278 /* See explanation above... */
279 (void) OS_REG_READ(ah, AR_IER);
282 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
283 OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
284 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ALL);
293 u_int64_t ar5416GetTsf64(struct ath_hal *ah)
297 tsf = OS_REG_READ(ah, AR_TSF_U32);
298 tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32);
303 a_uint32_t ar5416GetTsf32(struct ath_hal *ah)
305 return OS_REG_READ(ah, AR_TSF_L32);
308 void ar5416ResetTsf(struct ath_hal *ah)
314 while (OS_REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
321 OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
328 a_uint32_t ar5416GetRxDP(struct ath_hal *ath)
330 return OS_REG_READ(ath, AR_RXDP);
334 void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp)
336 OS_REG_WRITE(ah, AR_RXDP, rxdp);
337 HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
340 void ar5416SetMulticastFilter(struct ath_hal *ah, a_uint32_t filter0, a_uint32_t filter1)
342 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
343 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
346 HAL_BOOL ar5416ClrMulticastFilterIndex(struct ath_hal *ah, a_uint32_t ix)
353 val = OS_REG_READ(ah, AR_MCAST_FIL1);
354 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
356 val = OS_REG_READ(ah, AR_MCAST_FIL0);
357 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
362 HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah)
364 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
365 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
372 HAL_BOOL ar5416SetMulticastFilterIndex(struct ath_hal *ah, a_uint32_t ix)
379 val = OS_REG_READ(ah, AR_MCAST_FIL1);
380 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));
382 val = OS_REG_READ(ah, AR_MCAST_FIL0);
383 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));
388 void ar5416StartPcuReceive(struct ath_hal *ah)
390 OS_REG_CLR_BIT(ah, AR_DIAG_SW,
391 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
394 void ar5416SetRxFilter(struct ath_hal *ah, a_uint32_t bits)
398 OS_REG_WRITE(ah, AR_RX_FILTER, (bits & 0xff) | AR_RX_COMPR_BAR);
400 if (bits & HAL_RX_FILTER_PHYRADAR)
401 phybits |= AR_PHY_ERR_RADAR;
402 if (bits & HAL_RX_FILTER_PHYERR)
403 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
404 OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
406 OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
408 OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
412 void ar5416EnableReceive(struct ath_hal *ah)
414 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
417 void ar5416StopPcuReceive(struct ath_hal *ah)
419 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
422 HAL_BOOL ar5416SetupRxDesc_20(struct ath_hal *ah, struct ath_rx_desc *ds,
423 a_uint32_t size, a_uint32_t flags)
425 struct ar5416_desc *ads = AR5416DESC(ds);
427 HALASSERT((size &~ AR_BufLen) == 0);
429 ads->ds_ctl1 = size & AR_BufLen;
430 if (flags & HAL_RXDESC_INTREQ)
431 ads->ds_ctl1 |= AR_RxIntrReq;
433 /* this should be enough */
434 ads->ds_rxstatus8 &= ~AR_RxDone;
439 HAL_STATUS ar5416ProcRxDescFast_20(struct ath_hal *ah, struct ath_rx_desc *ds,
440 a_uint32_t pa, struct ath_desc *nds,
441 struct ath_rx_status *rx_stats)
443 struct ar5416_desc ads;
444 struct ar5416_desc *adsp = AR5416DESC(ds);
445 struct ar5416_desc *ands = AR5416DESC(nds);
447 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
448 return HAL_EINPROGRESS;
450 * Given the use of a self-linked tail be very sure that the hw is
451 * done with this descriptor; the hw may have done this descriptor
452 * once and picked it up again...make sure the hw has moved on.
454 if ((ands->ds_rxstatus8 & AR_RxDone) == 0
455 && OS_REG_READ(ah, AR_RXDP) == pa)
456 return HAL_EINPROGRESS;
459 * Now we need to get the stats from the descriptor. Since desc are
460 * uncached, lets make a copy of the stats first. Note that, since we
461 * touch most of the rx stats, a memcpy would always be more efficient
463 * Next we fill in all values in a caller passed stack variable.
464 * This reduces the number of uncached accesses.
465 * Do this copy here, after the check so that when the checks fail, we
466 * dont end up copying the entire stats uselessly.
468 ads.u.rx = adsp->u.rx;
470 rx_stats->rs_status = 0;
471 rx_stats->rs_flags = 0;
473 rx_stats->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
474 rx_stats->rs_tstamp = ads.AR_RcvTimestamp;
476 /* XXX what about KeyCacheMiss? */
477 rx_stats->rs_rssi_combined =
478 MS(ads.ds_rxstatus4, AR_RxRSSICombined);
479 rx_stats->rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00);
480 rx_stats->rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01);
481 rx_stats->rs_rssi_ctl2 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt02);
482 rx_stats->rs_rssi_ext0 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt10);
483 rx_stats->rs_rssi_ext1 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt11);
484 rx_stats->rs_rssi_ext2 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt12);
485 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
486 rx_stats->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
488 rx_stats->rs_keyix = HAL_RXKEYIX_INVALID;
489 /* NB: caller expected to do rate table mapping */
490 rx_stats->rs_rate = RXSTATUS_RATE(ah, (&ads));
491 rx_stats->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
493 rx_stats->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
494 rx_stats->rs_moreaggr = (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
495 rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_GI) ? HAL_RX_GI : 0;
496 rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_2040) ? HAL_RX_2040 : 0;
498 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
499 rx_stats->rs_flags |= HAL_RX_DELIM_CRC_PRE;
500 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
501 rx_stats->rs_flags |= HAL_RX_DELIM_CRC_POST;
502 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
503 rx_stats->rs_flags |= HAL_RX_DECRYPT_BUSY;
505 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
507 * These four bits should not be set together. The
508 * 5416 spec states a Michael error can only occur if
509 * DecryptCRCErr not set (and TKIP is used). Experience
510 * indicates however that you can also get Michael errors
511 * when a CRC error is detected, but these are specious.
512 * Consequently we filter them out here so we don't
513 * confuse and/or complicate drivers.
515 if (ads.ds_rxstatus8 & AR_CRCErr)
516 rx_stats->rs_status |= HAL_RXERR_CRC;
517 else if (ads.ds_rxstatus8 & AR_PHYErr) {
520 rx_stats->rs_status |= HAL_RXERR_PHY;
521 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
522 rx_stats->rs_phyerr = phyerr;
523 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
524 rx_stats->rs_status |= HAL_RXERR_DECRYPT;
525 else if (ads.ds_rxstatus8 & AR_MichaelErr)
526 rx_stats->rs_status |= HAL_RXERR_MIC;
528 rx_stats->evm0=ads.AR_RxEVM0;
529 rx_stats->evm1=ads.AR_RxEVM1;
530 rx_stats->evm2=ads.AR_RxEVM2;
539 HAL_BOOL ar5416UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
541 struct ath_hal_5416 *ahp = AH5416(ah);
542 a_uint32_t txcfg, curLevel, newLevel;
546 * Disable interrupts while futzing with the fifo level.
548 omask = ar5416SetInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL);
550 txcfg = OS_REG_READ(ah, AR_TXCFG);
551 curLevel = MS(txcfg, AR_FTRIG);
555 if (curLevel < MAX_TX_FIFO_THRESHOLD)
557 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
559 if (newLevel != curLevel)
560 OS_REG_WRITE(ah, AR_TXCFG,
561 (txcfg &~ AR_FTRIG) | SM(newLevel, AR_FTRIG));
563 /* re-enable chip interrupts */
564 ar5416SetInterrupts(ah, omask);
566 return (newLevel != curLevel);
569 HAL_BOOL ar5416SetTxDP(struct ath_hal *ah, a_uint32_t q, a_uint32_t txdp)
571 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
572 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
575 * Make sure that TXE is deasserted before setting the TXDP. If TXE
576 * is still asserted, setting TXDP will have no effect.
578 HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0);
580 OS_REG_WRITE(ah, AR_QTXDP(q), txdp);
585 HAL_BOOL ar5416StartTxDma(struct ath_hal *ah, a_uint32_t q)
587 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
588 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
590 /* Check to be sure we're not enabling a q that has its TXD bit set. */
591 HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1 << q)) == 0);
593 OS_REG_WRITE(ah, AR_Q_TXE, 1 << q);
598 a_uint32_t ar5416NumTxPending(struct ath_hal *ah, a_uint32_t q)
602 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
603 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
605 npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
608 * Pending frame count (PFC) can momentarily go to zero
609 * while TXE remains asserted. In other words a PFC of
610 * zero is not sufficient to say that the queue has stopped.
612 if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q))
616 if (npend && (AH5416(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) {
617 if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) {
618 isrPrintf("RTSD on CAB queue\n");
619 /* Clear the ReadyTime shutdown status bits */
620 OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q);
627 HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah)
632 * set txd on all queues
634 OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
639 OS_REG_SET_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF));
640 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
641 OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
644 * wait on all tx queues
646 for (q = 0; q < AR_NUM_QCU; q++) {
647 for (i = 0; i < AR5416_ABORT_LOOPS; i++) {
648 if (!ar5416NumTxPending(ah, q))
651 OS_DELAY(AR5416_ABORT_WAIT);
653 if (i == AR5416_ABORT_LOOPS) {
659 * clear tx abort bits
661 OS_REG_CLR_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF));
662 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
663 OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
668 OS_REG_WRITE(ah, AR_Q_TXD, 0);
673 HAL_BOOL ar5416StopTxDma(struct ath_hal*ah, a_uint32_t q)
677 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
679 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
681 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
682 for (i = 1000; i != 0; i--) {
683 if (ar5416NumTxPending(ah, q) == 0)
685 OS_DELAY(100); /* XXX get actual value */
688 OS_REG_WRITE(ah, AR_Q_TXD, 0);
692 void ar5416GetTxIntrQueue(struct ath_hal *ah, a_uint32_t *txqs)
694 struct ath_hal_5416 *ahp = AH5416(ah);
695 *txqs &= ahp->ah_intrTxqs;
696 ahp->ah_intrTxqs &= ~(*txqs);
699 void ar5416IntrReqTxDesc_20(struct ath_hal *ah, struct ath_desc *ds)
701 struct ar5416_desc *ads = AR5416DESC(ds);
702 ads->ds_ctl0 |= AR_TxIntrReq;
705 HAL_BOOL ar5416SetupTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
710 a_uint32_t txRate0, a_uint32_t txTries0,
714 a_uint32_t rtsctsRate,
715 a_uint32_t rtsctsDuration,
716 a_uint32_t compicvLen,
717 a_uint32_t compivLen,
720 #define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
722 struct ar5416_desc *ads = AR5416DESC(ds);
726 ads->ds_txstatus9 &= ~AR_TxDone;
728 HALASSERT(txTries0 != 0);
729 HALASSERT(isValidPktType(type));
730 HALASSERT(isValidTxRate(txRate0));
731 HALASSERT((flags & RTSCTS) != RTSCTS);
736 ads->ds_ctl0 = (pktLen & AR_FrameLen)
737 | (txPower << AR_XmitPower_S)
738 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
739 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
740 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0);
742 ads->ds_ctl1 = (type << AR_FrameType_S)
743 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0);
744 ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0);
745 ads->ds_ctl3 = (txRate0 << AR_XmitRate0_S);
747 ads->ds_ctl7 = SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel0)
748 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel1)
749 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel2)
750 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel3);
752 if (keyIx != HAL_TXKEYIX_INVALID) {
753 /* XXX validate key index */
754 ads->ds_ctl1 |= SM(keyIx, AR_DestIdx);
755 ads->ds_ctl0 |= AR_DestIdxValid;
758 if (flags & RTSCTS) {
759 if (!isValidTxRate(rtsctsRate)) {
762 /* XXX validate rtsctsDuration */
763 ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0)
764 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0);
765 ads->ds_ctl2 |= SM(rtsctsDuration, AR_BurstDur);
766 ads->ds_ctl3 |= (rtsctsRate << AR_RTSCTSRate_S);
773 HAL_BOOL ar5416FillTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
774 a_uint32_t segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
775 const struct ath_tx_desc *ds0)
777 struct ar5416_desc *ads = AR5416DESC(ds);
779 HALASSERT((segLen &~ AR_BufLen) == 0);
783 * First descriptor, don't clobber xmit control data
784 * setup by ar5416SetupTxDesc.
786 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
787 } else if (lastSeg) {
789 * Last descriptor in a multi-descriptor frame,
790 * copy the multi-rate transmit parameters from
791 * the first frame for processing on completion.
794 ads->ds_ctl1 = segLen;
795 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
796 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
799 * Intermediate descriptor in a multi-descriptor frame.
802 ads->ds_ctl1 = segLen | AR_TxMore;
806 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
811 HAL_BOOL ar5416FillKeyTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
812 HAL_KEY_TYPE keyType)
814 struct ar5416_desc *ads = AR5416DESC(ds);
816 ads->ds_ctl6 = SM(keyType, AR_EncrType);
820 HAL_STATUS ar5416ProcTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *gds)
822 struct ar5416_desc *ads = AR5416DESC(gds);
823 struct ath_tx_desc *ds = (struct ath_tx_desc *)gds;
825 if ((ads->ds_txstatus9 & AR_TxDone) == 0)
826 return HAL_EINPROGRESS;
828 ads->ds_txstatus9 &= ~AR_TxDone;
830 /* Update software copies of the HW status */
831 ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
832 ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp;
833 ds->ds_txstat.ts_status = 0;
834 ds->ds_txstat.ts_flags = 0;
836 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
837 ds->ds_txstat.ts_status |= HAL_TXERR_XRETRY;
838 if (ads->ds_txstatus1 & AR_Filtered)
839 ds->ds_txstat.ts_status |= HAL_TXERR_FILT;
840 if (ads->ds_txstatus1 & AR_FIFOUnderrun)
841 ds->ds_txstat.ts_status |= HAL_TXERR_FIFO;
842 if (ads->ds_txstatus9 & AR_TxOpExceeded)
843 ds->ds_txstat.ts_status |= HAL_TXERR_XTXOP;
844 if (ads->ds_txstatus1 & AR_TxTimerExpired)
845 ds->ds_txstat.ts_status |= HAL_TXERR_TIMER_EXPIRED;
847 if (ads->ds_txstatus1 & AR_DescCfgErr)
848 ds->ds_txstat.ts_flags |= HAL_TX_DESC_CFG_ERR;
849 if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
850 ds->ds_txstat.ts_flags |= HAL_TX_DATA_UNDERRUN;
851 ar5416UpdateTxTrigLevel(ah, AH_TRUE);
853 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
854 ds->ds_txstat.ts_flags |= HAL_TX_DELIM_UNDERRUN;
855 ar5416UpdateTxTrigLevel(ah, AH_TRUE);
857 if (ads->ds_txstatus0 & AR_TxBaStatus) {
858 ds->ds_txstat.ts_flags |= HAL_TX_BA;
859 ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
860 ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
864 * Extract the transmit rate used and mark the rate as
865 * ``alternate'' if it wasn't the series 0 rate.
867 ds->ds_txstat.ts_rate = MS(ads->ds_txstatus9, AR_FinalTxIdx);
868 ds->ds_txstat.ts_rssi_combined =
869 MS(ads->ds_txstatus5, AR_TxRSSICombined);
870 ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
871 ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
872 ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
873 ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
874 ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
875 ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
876 ds->ds_txstat.evm0 = ads->AR_TxEVM0;
877 ds->ds_txstat.evm1 = ads->AR_TxEVM1;
878 ds->ds_txstat.evm2 = ads->AR_TxEVM2;
879 ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
880 ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
881 ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
882 ds->ds_txstat.ts_antenna = 0; /* ignored for owl */
887 void ar5416Set11nTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
888 a_uint32_t pktLen, HAL_PKT_TYPE type, a_uint32_t txPower,
889 a_uint32_t keyIx, HAL_KEY_TYPE keyType,
892 struct ar5416_desc *ads = AR5416DESC(ds);
894 HALASSERT(isValidPktType(type));
895 HALASSERT(isValidKeyType(keyType));
900 ads->ds_ctl0 = (pktLen & AR_FrameLen)
901 | (flags & HAL_TXDESC_VMF ? AR_VirtMoreFrag : 0)
902 | SM(txPower, AR_XmitPower)
903 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0)
904 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
905 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
906 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0)
907 | (keyIx != HAL_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
908 | (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0);
910 ads->ds_ctl1 = (keyIx != HAL_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
911 | SM(type, AR_FrameType)
912 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0)
913 | (flags & HAL_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
914 | (flags & HAL_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
916 ads->ds_ctl6 = SM(keyType, AR_EncrType);
921 void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_tx_desc *ds,
922 a_uint32_t durUpdateEn, a_uint32_t rtsctsRate,
923 a_uint32_t rtsctsDuration,
924 HAL_11N_RATE_SERIES series[], a_uint32_t nseries,
927 struct ar5416_desc *ads = AR5416DESC(ds);
930 HALASSERT(nseries == 4);
934 * Rate control settings override
936 ds_ctl0 = ads->ds_ctl0;
938 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
939 if (flags & HAL_TXDESC_RTSENA) {
940 ds_ctl0 &= ~AR_CTSEnable;
941 ds_ctl0 |= AR_RTSEnable;
943 ds_ctl0 &= ~AR_RTSEnable;
944 ds_ctl0 |= AR_CTSEnable;
947 ds_ctl0 = (ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
950 ads->ds_ctl0 = ds_ctl0;
952 ads->ds_ctl2 = set11nTries(series, 0)
953 | set11nTries(series, 1)
954 | set11nTries(series, 2)
955 | set11nTries(series, 3)
956 | (durUpdateEn ? AR_DurUpdateEn : 0);
958 ads->ds_ctl3 = set11nRate(series, 0)
959 | set11nRate(series, 1)
960 | set11nRate(series, 2)
961 | set11nRate(series, 3);
963 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
964 | set11nPktDurRTSCTS(series, 1);
966 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
967 | set11nPktDurRTSCTS(series, 3);
969 ads->ds_ctl7 = set11nRateFlags(series, 0)
970 | set11nRateFlags(series, 1)
971 | set11nRateFlags(series, 2)
972 | set11nRateFlags(series, 3)
973 | SM(rtsctsRate, AR_RTSCTSRate);
978 void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_tx_desc *ds,
979 a_uint32_t durUpdateEn, a_uint32_t rtsctsRate,
980 a_uint32_t rtsctsDuration,
981 HAL_11N_RATE_SERIES series[], a_uint32_t nseries,
984 struct ar5416_desc *ads = AR5416DESC(ds);
987 HALASSERT(nseries == 4);
991 * Rate control settings override
993 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
994 ds_ctl0 = ads->ds_ctl0;
996 if (flags & HAL_TXDESC_RTSENA) {
997 ds_ctl0 &= ~AR_CTSEnable;
998 ds_ctl0 |= AR_RTSEnable;
1000 ds_ctl0 &= ~AR_RTSEnable;
1001 ds_ctl0 |= AR_CTSEnable;
1004 ads->ds_ctl0 = ds_ctl0;
1007 ads->ds_ctl2 = set11nTries(series, 0)
1008 | set11nTries(series, 1)
1009 | set11nTries(series, 2)
1010 | set11nTries(series, 3)
1011 | (durUpdateEn ? AR_DurUpdateEn : 0);
1013 ads->ds_ctl3 = set11nRate(series, 0)
1014 | set11nRate(series, 1)
1015 | set11nRate(series, 2)
1016 | set11nRate(series, 3);
1018 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
1019 | set11nPktDurRTSCTS(series, 1);
1021 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
1022 | set11nPktDurRTSCTS(series, 3);
1024 ads->ds_ctl7 = set11nRateFlags(series, 0)
1025 | set11nRateFlags(series, 1)
1026 | set11nRateFlags(series, 2)
1027 | set11nRateFlags(series, 3)
1028 | SM(rtsctsRate, AR_RTSCTSRate);
1033 void ar5416Set11nAggrFirst_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uint32_t aggrLen,
1034 a_uint32_t numDelims)
1036 struct ar5416_desc *ads = AR5416DESC(ds);
1038 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
1040 ads->ds_ctl6 &= ~(AR_AggrLen | AR_PadDelim);
1041 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen) |
1042 SM(numDelims, AR_PadDelim);
1045 void ar5416Set11nAggrMiddle_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uint32_t numDelims)
1047 struct ar5416_desc *ads = AR5416DESC(ds);
1050 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
1053 * We use a stack variable to manipulate ctl6 to reduce uncached
1054 * read modify, modfiy, write.
1056 ctl6 = ads->ds_ctl6;
1057 ctl6 &= ~AR_PadDelim;
1058 ctl6 |= SM(numDelims, AR_PadDelim);
1059 ads->ds_ctl6 = ctl6;
1062 void ar5416Set11nAggrLast_20(struct ath_hal *ah, struct ath_tx_desc *ds)
1064 struct ar5416_desc *ads = AR5416DESC(ds);
1066 ads->ds_ctl1 |= AR_IsAggr;
1067 ads->ds_ctl1 &= ~AR_MoreAggr;
1068 ads->ds_ctl6 &= ~AR_PadDelim;
1071 void ar5416Clr11nAggr_20(struct ath_hal *ah, struct ath_tx_desc *ds)
1073 struct ar5416_desc *ads = AR5416DESC(ds);
1075 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
1078 void ar5416Set11nBurstDuration_20(struct ath_hal *ah, struct ath_tx_desc *ds,
1079 a_uint32_t burstDuration)
1081 struct ar5416_desc *ads = AR5416DESC(ds);
1083 ads->ds_ctl2 &= ~AR_BurstDur;
1084 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
1087 void ar5416Set11nVirtualMoreFrag_20(struct ath_hal *ah, struct ath_tx_desc *ds,
1090 struct ar5416_desc *ads = AR5416DESC(ds);
1093 ads->ds_ctl0 |= AR_VirtMoreFrag;
1095 ads->ds_ctl0 &= ~AR_VirtMoreFrag;