2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
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37 #include "ah_internal.h"
39 #include "ar5416reg.h"
40 #include "ar5416desc.h"
42 #define N(a) (sizeof(a)/sizeof(a[0]))
43 #define AR_INTR_SPURIOUS 0xffffffff
44 #define ar5416_desc ar5416_desc_20
45 #define AR5416_ABORT_LOOPS 1000
46 #define AR5416_ABORT_WAIT 5
47 #define AR5416DESC AR5416DESC_20
48 #define AR5416DESC_CONST AR5416DESC_CONST_20
54 static const struct ath_hal_private ar5416hal_10 = {{
55 .ah_getRateTable = ar5416GetRateTable,
56 .ah_detach = ar5416Detach,
58 /* Transmit functions */
59 .ah_updateTxTrigLevel = ar5416UpdateTxTrigLevel,
60 .ah_setTxDP = ar5416SetTxDP,
61 .ah_numTxPending = ar5416NumTxPending,
62 .ah_startTxDma = ar5416StartTxDma,
63 .ah_stopTxDma = ar5416StopTxDma,
65 .ah_abortTxDma = ar5416AbortTxDma,
68 .ah_getTsf64 = ar5416GetTsf64,
69 .ah_setRxFilter = ar5416SetRxFilter,
72 .ah_setRxDP = ar5416SetRxDP,
73 .ah_stopDmaReceive = ar5416StopDmaReceive,
74 .ah_enableReceive = ar5416EnableReceive,
75 .ah_stopPcuReceive = ar5416StopPcuReceive,
77 /* Interrupt Functions */
78 .ah_isInterruptPending = ar5416IsInterruptPending,
79 .ah_getPendingInterrupts = ar5416GetPendingInterrupts,
80 .ah_setInterrupts = ar5416SetInterrupts,
84 void ar5416Detach(struct ath_hal *ah)
86 HALASSERT(ah != AH_NULL);
91 ar5416Attach(HAL_SOFTC sc, adf_os_device_t dev, HAL_STATUS *status)
93 struct ath_hal_5416 *ahp;
96 ahp = ath_hal_malloc(sizeof (struct ath_hal_5416));
101 ah = &ahp->ah_priv.h;
103 OS_MEMCPY(&ahp->ah_priv, &ar5416hal_10, sizeof(struct ath_hal_private));
108 ah->ah_set11nTxDesc = ar5416Set11nTxDesc_20;
109 ah->ah_set11nRateScenario = ar5416Set11nRateScenario_20;
110 ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst_20;
111 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle_20;
112 ah->ah_set11nAggrLast = ar5416Set11nAggrLast_20;
113 ah->ah_clr11nAggr = ar5416Clr11nAggr_20;
114 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration_20;
115 ah->ah_setupRxDesc = ar5416SetupRxDesc_20;
116 ah->ah_procRxDescFast = ar5416ProcRxDescFast_20;
117 ah->ah_setupTxDesc = ar5416SetupTxDesc_20;
118 ah->ah_fillTxDesc = ar5416FillTxDesc_20;
119 ah->ah_fillKeyTxDesc = ar5416FillKeyTxDesc_20;
120 ah->ah_procTxDesc = ar5416ProcTxDesc_20;
121 ah->ah_set11nVirtualMoreFrag = ar5416Set11nVirtualMoreFrag_20;
126 /**********************/
127 /* Interrupt Handling */
128 /**********************/
130 HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah)
132 a_uint32_t host_isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE);
134 * Some platforms trigger our ISR before applying power to
135 * the card, so make sure.
137 return ((host_isr != AR_INTR_SPURIOUS) && (host_isr & AR_INTR_MAC_IRQ));
140 HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
144 HAL_BOOL fatal_int = AH_FALSE;
145 a_uint32_t sync_cause;
147 if (OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
148 if ((OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) != AR_RTC_STATUS_ON) {
157 isr = OS_REG_READ(ah, AR_ISR_RAC);
158 if (isr == 0xffffffff) {
163 *masked = isr & HAL_INT_COMMON;
165 #ifdef AR5416_INT_MITIGATION
166 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) {
167 *masked |= HAL_INT_RX;
169 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) {
170 *masked |= HAL_INT_TX;
174 if (isr & AR_ISR_BCNMISC) {
177 s2_s = OS_REG_READ(ah, AR_ISR_S2_S);
179 if (s2_s & AR_ISR_S2_GTT) {
180 *masked |= HAL_INT_GTT;
183 if (s2_s & AR_ISR_S2_CST) {
184 *masked |= HAL_INT_CST;
188 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
189 *masked |= HAL_INT_RX;
190 if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) {
191 struct ath_hal_5416 *ahp = AH5416(ah);
192 a_uint32_t s0_s, s1_s;
194 *masked |= HAL_INT_TX;
195 s0_s = OS_REG_READ(ah, AR_ISR_S0_S);
196 s1_s = OS_REG_READ(ah, AR_ISR_S1_S);
197 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
198 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
199 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
200 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
204 sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
205 fatal_int = ((sync_cause != AR_INTR_SPURIOUS) &&
206 (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))) ?
209 if (AH_TRUE == fatal_int) {
210 OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
211 (void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
218 ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
220 struct ath_hal_5416 *ahp = AH5416(ah);
221 a_uint32_t omask = ahp->ah_maskReg;
224 if (omask & HAL_INT_GLOBAL) {
225 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
226 (void) OS_REG_READ(ah, AR_IER);
229 mask = ints & HAL_INT_COMMON;
230 if (ints & HAL_INT_TX) {
231 #ifdef AR5416_INT_MITIGATION
232 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
235 mask |= AR_IMR_TXDESC;
237 mask |= AR_IMR_TXERR;
238 mask |= AR_IMR_TXEOL;
240 if (ints & HAL_INT_RX) {
241 mask |= AR_IMR_RXERR;
242 #ifdef AR5416_INT_MITIGATION
243 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
245 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
249 if (ints & (HAL_INT_GTT | HAL_INT_CST)) {
250 mask |= AR_IMR_BCNMISC;
253 OS_REG_WRITE(ah, AR_IMR, mask);
254 (void) OS_REG_READ(ah, AR_IMR);
255 ahp->ah_maskReg = ints;
257 /* Re-enable interrupts if they were enabled before. */
258 if (ints & HAL_INT_GLOBAL) {
259 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
260 /* See explanation above... */
261 (void) OS_REG_READ(ah, AR_IER);
264 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
265 OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
266 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ALL);
275 u_int64_t ar5416GetTsf64(struct ath_hal *ah)
279 tsf = OS_REG_READ(ah, AR_TSF_U32);
280 tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32);
288 void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp)
290 OS_REG_WRITE(ah, AR_RXDP, rxdp);
291 HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
294 HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah)
296 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
297 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
304 void ar5416SetRxFilter(struct ath_hal *ah, a_uint32_t bits)
308 OS_REG_WRITE(ah, AR_RX_FILTER, (bits & 0xff) | AR_RX_COMPR_BAR);
310 if (bits & HAL_RX_FILTER_PHYRADAR)
311 phybits |= AR_PHY_ERR_RADAR;
312 if (bits & HAL_RX_FILTER_PHYERR)
313 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
314 OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
316 OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
318 OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
322 void ar5416EnableReceive(struct ath_hal *ah)
324 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
327 void ar5416StopPcuReceive(struct ath_hal *ah)
329 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
332 HAL_BOOL ar5416SetupRxDesc_20(struct ath_rx_desc *ds,
333 a_uint32_t size, a_uint32_t flags)
335 struct ar5416_desc *ads = AR5416DESC(ds);
337 HALASSERT((size &~ AR_BufLen) == 0);
339 ads->ds_ctl1 = size & AR_BufLen;
340 if (flags & HAL_RXDESC_INTREQ)
341 ads->ds_ctl1 |= AR_RxIntrReq;
343 /* this should be enough */
344 ads->ds_rxstatus8 &= ~AR_RxDone;
349 HAL_STATUS ar5416ProcRxDescFast_20(struct ath_hal *ah, struct ath_rx_desc *ds,
350 a_uint32_t pa, struct ath_desc *nds,
351 struct ath_rx_status *rx_stats)
353 struct ar5416_desc ads;
354 struct ar5416_desc *adsp = AR5416DESC(ds);
355 struct ar5416_desc *ands = AR5416DESC(nds);
357 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
358 return HAL_EINPROGRESS;
360 * Given the use of a self-linked tail be very sure that the hw is
361 * done with this descriptor; the hw may have done this descriptor
362 * once and picked it up again...make sure the hw has moved on.
364 if ((ands->ds_rxstatus8 & AR_RxDone) == 0
365 && OS_REG_READ(ah, AR_RXDP) == pa)
366 return HAL_EINPROGRESS;
369 * Now we need to get the stats from the descriptor. Since desc are
370 * uncached, lets make a copy of the stats first. Note that, since we
371 * touch most of the rx stats, a memcpy would always be more efficient
373 * Next we fill in all values in a caller passed stack variable.
374 * This reduces the number of uncached accesses.
375 * Do this copy here, after the check so that when the checks fail, we
376 * dont end up copying the entire stats uselessly.
378 ads.u.rx = adsp->u.rx;
380 rx_stats->rs_status = 0;
381 rx_stats->rs_flags = 0;
383 rx_stats->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
384 rx_stats->rs_tstamp = ads.AR_RcvTimestamp;
386 /* XXX what about KeyCacheMiss? */
387 rx_stats->rs_rssi_combined =
388 MS(ads.ds_rxstatus4, AR_RxRSSICombined);
389 rx_stats->rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00);
390 rx_stats->rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01);
391 rx_stats->rs_rssi_ctl2 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt02);
392 rx_stats->rs_rssi_ext0 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt10);
393 rx_stats->rs_rssi_ext1 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt11);
394 rx_stats->rs_rssi_ext2 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt12);
395 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
396 rx_stats->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
398 rx_stats->rs_keyix = HAL_RXKEYIX_INVALID;
399 /* NB: caller expected to do rate table mapping */
400 rx_stats->rs_rate = RXSTATUS_RATE(ah, (&ads));
401 rx_stats->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
403 rx_stats->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
404 rx_stats->rs_moreaggr = (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
405 rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_GI) ? HAL_RX_GI : 0;
406 rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_2040) ? HAL_RX_2040 : 0;
408 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
409 rx_stats->rs_flags |= HAL_RX_DELIM_CRC_PRE;
410 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
411 rx_stats->rs_flags |= HAL_RX_DELIM_CRC_POST;
412 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
413 rx_stats->rs_flags |= HAL_RX_DECRYPT_BUSY;
415 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
417 * These four bits should not be set together. The
418 * 5416 spec states a Michael error can only occur if
419 * DecryptCRCErr not set (and TKIP is used). Experience
420 * indicates however that you can also get Michael errors
421 * when a CRC error is detected, but these are specious.
422 * Consequently we filter them out here so we don't
423 * confuse and/or complicate drivers.
425 if (ads.ds_rxstatus8 & AR_CRCErr)
426 rx_stats->rs_status |= HAL_RXERR_CRC;
427 else if (ads.ds_rxstatus8 & AR_PHYErr) {
430 rx_stats->rs_status |= HAL_RXERR_PHY;
431 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
432 rx_stats->rs_phyerr = phyerr;
433 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
434 rx_stats->rs_status |= HAL_RXERR_DECRYPT;
435 else if (ads.ds_rxstatus8 & AR_MichaelErr)
436 rx_stats->rs_status |= HAL_RXERR_MIC;
438 rx_stats->evm0=ads.AR_RxEVM0;
439 rx_stats->evm1=ads.AR_RxEVM1;
440 rx_stats->evm2=ads.AR_RxEVM2;
449 HAL_BOOL ar5416UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
451 struct ath_hal_5416 *ahp = AH5416(ah);
452 a_uint32_t txcfg, curLevel, newLevel;
456 * Disable interrupts while futzing with the fifo level.
458 omask = ar5416SetInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL);
460 txcfg = OS_REG_READ(ah, AR_TXCFG);
461 curLevel = MS(txcfg, AR_FTRIG);
465 if (curLevel < MAX_TX_FIFO_THRESHOLD)
467 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
469 if (newLevel != curLevel)
470 OS_REG_WRITE(ah, AR_TXCFG,
471 (txcfg &~ AR_FTRIG) | SM(newLevel, AR_FTRIG));
473 /* re-enable chip interrupts */
474 ar5416SetInterrupts(ah, omask);
476 return (newLevel != curLevel);
479 HAL_BOOL ar5416SetTxDP(struct ath_hal *ah, a_uint32_t q, a_uint32_t txdp)
481 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
482 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
485 * Make sure that TXE is deasserted before setting the TXDP. If TXE
486 * is still asserted, setting TXDP will have no effect.
488 HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0);
490 OS_REG_WRITE(ah, AR_QTXDP(q), txdp);
495 HAL_BOOL ar5416StartTxDma(struct ath_hal *ah, a_uint32_t q)
497 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
498 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
500 /* Check to be sure we're not enabling a q that has its TXD bit set. */
501 HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1 << q)) == 0);
503 OS_REG_WRITE(ah, AR_Q_TXE, 1 << q);
508 a_uint32_t ar5416NumTxPending(struct ath_hal *ah, a_uint32_t q)
512 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
513 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
515 npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
518 * Pending frame count (PFC) can momentarily go to zero
519 * while TXE remains asserted. In other words a PFC of
520 * zero is not sufficient to say that the queue has stopped.
522 if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q))
526 if (npend && (AH5416(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) {
527 if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) {
528 isrPrintf("RTSD on CAB queue\n");
529 /* Clear the ReadyTime shutdown status bits */
530 OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q);
537 HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah)
542 * set txd on all queues
544 OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
549 OS_REG_SET_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF));
550 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
551 OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
554 * wait on all tx queues
556 for (q = 0; q < AR_NUM_QCU; q++) {
557 for (i = 0; i < AR5416_ABORT_LOOPS; i++) {
558 if (!ar5416NumTxPending(ah, q))
561 OS_DELAY(AR5416_ABORT_WAIT);
563 if (i == AR5416_ABORT_LOOPS) {
569 * clear tx abort bits
571 OS_REG_CLR_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF));
572 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
573 OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
578 OS_REG_WRITE(ah, AR_Q_TXD, 0);
583 HAL_BOOL ar5416StopTxDma(struct ath_hal*ah, a_uint32_t q)
587 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
589 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
591 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
592 for (i = 1000; i != 0; i--) {
593 if (ar5416NumTxPending(ah, q) == 0)
595 OS_DELAY(100); /* XXX get actual value */
598 OS_REG_WRITE(ah, AR_Q_TXD, 0);
602 HAL_BOOL ar5416SetupTxDesc_20(struct ath_tx_desc *ds,
607 a_uint32_t txRate0, a_uint32_t txTries0,
610 a_uint32_t rtsctsRate,
611 a_uint32_t rtsctsDuration)
613 #define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
615 struct ar5416_desc *ads = AR5416DESC(ds);
619 ads->ds_txstatus9 &= ~AR_TxDone;
621 HALASSERT(txTries0 != 0);
622 HALASSERT(isValidPktType(type));
623 HALASSERT(isValidTxRate(txRate0));
624 HALASSERT((flags & RTSCTS) != RTSCTS);
629 ads->ds_ctl0 = (pktLen & AR_FrameLen)
630 | (txPower << AR_XmitPower_S)
631 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
632 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
633 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0);
635 ads->ds_ctl1 = (type << AR_FrameType_S)
636 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0);
637 ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0);
638 ads->ds_ctl3 = (txRate0 << AR_XmitRate0_S);
640 ads->ds_ctl7 = SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel0)
641 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel1)
642 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel2)
643 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel3);
645 if (keyIx != HAL_TXKEYIX_INVALID) {
646 /* XXX validate key index */
647 ads->ds_ctl1 |= SM(keyIx, AR_DestIdx);
648 ads->ds_ctl0 |= AR_DestIdxValid;
651 if (flags & RTSCTS) {
652 if (!isValidTxRate(rtsctsRate)) {
655 /* XXX validate rtsctsDuration */
656 ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0)
657 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0);
658 ads->ds_ctl2 |= SM(rtsctsDuration, AR_BurstDur);
659 ads->ds_ctl3 |= (rtsctsRate << AR_RTSCTSRate_S);
666 HAL_BOOL ar5416FillTxDesc_20(struct ath_tx_desc *ds,
667 a_uint32_t segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
668 const struct ath_tx_desc *ds0)
670 struct ar5416_desc *ads = AR5416DESC(ds);
672 HALASSERT((segLen &~ AR_BufLen) == 0);
676 * First descriptor, don't clobber xmit control data
677 * setup by ar5416SetupTxDesc.
679 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
680 } else if (lastSeg) {
682 * Last descriptor in a multi-descriptor frame,
683 * copy the multi-rate transmit parameters from
684 * the first frame for processing on completion.
687 ads->ds_ctl1 = segLen;
688 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
689 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
692 * Intermediate descriptor in a multi-descriptor frame.
695 ads->ds_ctl1 = segLen | AR_TxMore;
699 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
704 HAL_BOOL ar5416FillKeyTxDesc_20(struct ath_tx_desc *ds,
705 HAL_KEY_TYPE keyType)
707 struct ar5416_desc *ads = AR5416DESC(ds);
709 ads->ds_ctl6 = SM(keyType, AR_EncrType);
713 HAL_STATUS ar5416ProcTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *gds)
715 struct ar5416_desc *ads = AR5416DESC(gds);
716 struct ath_tx_desc *ds = (struct ath_tx_desc *)gds;
718 if ((ads->ds_txstatus9 & AR_TxDone) == 0)
719 return HAL_EINPROGRESS;
721 ads->ds_txstatus9 &= ~AR_TxDone;
723 /* Update software copies of the HW status */
724 ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
725 ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp;
726 ds->ds_txstat.ts_status = 0;
727 ds->ds_txstat.ts_flags = 0;
729 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
730 ds->ds_txstat.ts_status |= HAL_TXERR_XRETRY;
731 if (ads->ds_txstatus1 & AR_Filtered)
732 ds->ds_txstat.ts_status |= HAL_TXERR_FILT;
733 if (ads->ds_txstatus1 & AR_FIFOUnderrun)
734 ds->ds_txstat.ts_status |= HAL_TXERR_FIFO;
735 if (ads->ds_txstatus9 & AR_TxOpExceeded)
736 ds->ds_txstat.ts_status |= HAL_TXERR_XTXOP;
737 if (ads->ds_txstatus1 & AR_TxTimerExpired)
738 ds->ds_txstat.ts_status |= HAL_TXERR_TIMER_EXPIRED;
740 if (ads->ds_txstatus1 & AR_DescCfgErr)
741 ds->ds_txstat.ts_flags |= HAL_TX_DESC_CFG_ERR;
742 if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
743 ds->ds_txstat.ts_flags |= HAL_TX_DATA_UNDERRUN;
744 ar5416UpdateTxTrigLevel(ah, AH_TRUE);
746 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
747 ds->ds_txstat.ts_flags |= HAL_TX_DELIM_UNDERRUN;
748 ar5416UpdateTxTrigLevel(ah, AH_TRUE);
750 if (ads->ds_txstatus0 & AR_TxBaStatus) {
751 ds->ds_txstat.ts_flags |= HAL_TX_BA;
752 ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
753 ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
757 * Extract the transmit rate used and mark the rate as
758 * ``alternate'' if it wasn't the series 0 rate.
760 ds->ds_txstat.ts_rate = MS(ads->ds_txstatus9, AR_FinalTxIdx);
761 ds->ds_txstat.ts_rssi_combined =
762 MS(ads->ds_txstatus5, AR_TxRSSICombined);
763 ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
764 ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
765 ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
766 ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
767 ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
768 ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
769 ds->ds_txstat.evm0 = ads->AR_TxEVM0;
770 ds->ds_txstat.evm1 = ads->AR_TxEVM1;
771 ds->ds_txstat.evm2 = ads->AR_TxEVM2;
772 ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
773 ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
774 ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
775 ds->ds_txstat.ts_antenna = 0; /* ignored for owl */
780 void ar5416Set11nTxDesc_20(struct ath_tx_desc *ds,
781 a_uint32_t pktLen, HAL_PKT_TYPE type, a_uint32_t txPower,
782 a_uint32_t keyIx, HAL_KEY_TYPE keyType,
785 struct ar5416_desc *ads = AR5416DESC(ds);
787 HALASSERT(isValidPktType(type));
788 HALASSERT(isValidKeyType(keyType));
793 ads->ds_ctl0 = (pktLen & AR_FrameLen)
794 | (flags & HAL_TXDESC_VMF ? AR_VirtMoreFrag : 0)
795 | SM(txPower, AR_XmitPower)
796 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0)
797 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
798 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
799 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0)
800 | (keyIx != HAL_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
801 | (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0);
803 ads->ds_ctl1 = (keyIx != HAL_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
804 | SM(type, AR_FrameType)
805 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0)
806 | (flags & HAL_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
807 | (flags & HAL_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
809 ads->ds_ctl6 = SM(keyType, AR_EncrType);
812 void ar5416Set11nRateScenario_20(struct ath_tx_desc *ds,
813 a_uint32_t durUpdateEn, a_uint32_t rtsctsRate,
814 HAL_11N_RATE_SERIES series[], a_uint32_t nseries,
817 struct ar5416_desc *ads = AR5416DESC(ds);
820 HALASSERT(nseries == 4);
824 * Rate control settings override
826 ds_ctl0 = ads->ds_ctl0;
828 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
829 if (flags & HAL_TXDESC_RTSENA) {
830 ds_ctl0 &= ~AR_CTSEnable;
831 ds_ctl0 |= AR_RTSEnable;
833 ds_ctl0 &= ~AR_RTSEnable;
834 ds_ctl0 |= AR_CTSEnable;
837 /* this line is only difference between merlin and k2
838 * Current one is for merlin */
839 ds_ctl0 = (ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
842 ads->ds_ctl0 = ds_ctl0;
844 ads->ds_ctl2 = set11nTries(series, 0)
845 | set11nTries(series, 1)
846 | set11nTries(series, 2)
847 | set11nTries(series, 3)
848 | (durUpdateEn ? AR_DurUpdateEn : 0);
850 ads->ds_ctl3 = set11nRate(series, 0)
851 | set11nRate(series, 1)
852 | set11nRate(series, 2)
853 | set11nRate(series, 3);
855 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
856 | set11nPktDurRTSCTS(series, 1);
858 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
859 | set11nPktDurRTSCTS(series, 3);
861 ads->ds_ctl7 = set11nRateFlags(series, 0)
862 | set11nRateFlags(series, 1)
863 | set11nRateFlags(series, 2)
864 | set11nRateFlags(series, 3)
865 | SM(rtsctsRate, AR_RTSCTSRate);
868 void ar5416Set11nAggrFirst_20(struct ath_tx_desc *ds, a_uint32_t aggrLen,
869 a_uint32_t numDelims)
871 struct ar5416_desc *ads = AR5416DESC(ds);
873 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
875 ads->ds_ctl6 &= ~(AR_AggrLen | AR_PadDelim);
876 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen) |
877 SM(numDelims, AR_PadDelim);
880 void ar5416Set11nAggrMiddle_20(struct ath_tx_desc *ds, a_uint32_t numDelims)
882 struct ar5416_desc *ads = AR5416DESC(ds);
885 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
888 * We use a stack variable to manipulate ctl6 to reduce uncached
889 * read modify, modfiy, write.
892 ctl6 &= ~AR_PadDelim;
893 ctl6 |= SM(numDelims, AR_PadDelim);
897 void ar5416Set11nAggrLast_20(struct ath_tx_desc *ds)
899 struct ar5416_desc *ads = AR5416DESC(ds);
901 ads->ds_ctl1 |= AR_IsAggr;
902 ads->ds_ctl1 &= ~AR_MoreAggr;
903 ads->ds_ctl6 &= ~AR_PadDelim;
906 void ar5416Clr11nAggr_20(struct ath_tx_desc *ds)
908 struct ar5416_desc *ads = AR5416DESC(ds);
910 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
913 void ar5416Set11nBurstDuration_20(struct ath_tx_desc *ds,
914 a_uint32_t burstDuration)
916 struct ar5416_desc *ads = AR5416DESC(ds);
918 ads->ds_ctl2 &= ~AR_BurstDur;
919 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
922 void ar5416Set11nVirtualMoreFrag_20(struct ath_tx_desc *ds,
925 struct ar5416_desc *ads = AR5416DESC(ds);
928 ads->ds_ctl0 |= AR_VirtMoreFrag;
930 ads->ds_ctl0 &= ~AR_VirtMoreFrag;