2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
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14 * documentation and/or other materials provided with the
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22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
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33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include "ah_internal.h"
40 #include "ar5416reg.h"
41 #include "ar5416phy.h"
42 #include "ar5416desc.h"
44 #define N(a) (sizeof(a)/sizeof(a[0]))
45 #define AR_INTR_SPURIOUS 0xffffffff
46 #define ar5416_desc ar5416_desc_20
47 #define AR5416_ABORT_LOOPS 1000
48 #define AR5416_ABORT_WAIT 5
49 #define AR5416DESC AR5416DESC_20
50 #define AR5416DESC_CONST AR5416DESC_CONST_20
56 static const struct ath_hal_private ar5416hal_10 = {{
57 .ah_getRateTable = ar5416GetRateTable,
58 .ah_detach = ar5416Detach,
60 /* Transmit functions */
61 .ah_updateTxTrigLevel = ar5416UpdateTxTrigLevel,
62 .ah_getTxDP = ar5416GetTxDP,
63 .ah_setTxDP = ar5416SetTxDP,
64 .ah_numTxPending = ar5416NumTxPending,
65 .ah_startTxDma = ar5416StartTxDma,
66 .ah_stopTxDma = ar5416StopTxDma,
68 .ah_getTxIntrQueue = ar5416GetTxIntrQueue,
69 .ah_abortTxDma = ar5416AbortTxDma,
72 .ah_getCapability = ar5416GetCapability,
73 .ah_getTsf32 = ar5416GetTsf32,
74 .ah_getTsf64 = ar5416GetTsf64,
75 .ah_resetTsf = ar5416ResetTsf,
76 .ah_setRxFilter = ar5416SetRxFilter,
79 .ah_getRxDP = ar5416GetRxDP,
80 .ah_setRxDP = ar5416SetRxDP,
81 .ah_stopDmaReceive = ar5416StopDmaReceive,
82 .ah_enableReceive = ar5416EnableReceive,
83 .ah_startPcuReceive = ar5416StartPcuReceive,
84 .ah_stopPcuReceive = ar5416StopPcuReceive,
86 /* Interrupt Functions */
87 .ah_isInterruptPending = ar5416IsInterruptPending,
88 .ah_getPendingInterrupts = ar5416GetPendingInterrupts,
89 .ah_getInterrupts = ar5416GetInterrupts,
90 .ah_setInterrupts = ar5416SetInterrupts,
94 void ar5416Detach(struct ath_hal *ah)
96 HALASSERT(ah != AH_NULL);
101 ar5416Attach(a_uint32_t devid,HAL_SOFTC sc, adf_os_device_t dev,
102 a_uint32_t flags, HAL_STATUS *status)
104 struct ath_hal_5416 *ahp;
107 ahp = ath_hal_malloc(sizeof (struct ath_hal_5416));
108 if (ahp == AH_NULL) {
109 *status = HAL_ENOMEM;
112 ah = &ahp->ah_priv.h;
114 OS_MEMCPY(&ahp->ah_priv, &ar5416hal_10, sizeof(struct ath_hal_private));
119 /* If its a Owl 2.0 chip then change the hal structure to
120 point to the Owl 2.0 ar5416_hal_20 structure */
122 ah->ah_set11nTxDesc = ar5416Set11nTxDesc_20;
123 ah->ah_set11nRateScenario = ar5416Set11nRateScenario_20;
124 ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst_20;
125 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle_20;
126 ah->ah_set11nAggrLast = ar5416Set11nAggrLast_20;
127 ah->ah_clr11nAggr = ar5416Clr11nAggr_20;
128 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration_20;
129 ah->ah_setupRxDesc = ar5416SetupRxDesc_20;
130 ah->ah_procRxDescFast = ar5416ProcRxDescFast_20;
131 ah->ah_updateCTSForBursting = NULL;
132 ah->ah_setupTxDesc = ar5416SetupTxDesc_20;
133 ah->ah_reqTxIntrDesc = ar5416IntrReqTxDesc_20;
134 ah->ah_fillTxDesc = ar5416FillTxDesc_20;
135 ah->ah_fillKeyTxDesc = ar5416FillKeyTxDesc_20;
136 ah->ah_procTxDesc = ar5416ProcTxDesc_20;
137 ah->ah_set11nVirtualMoreFrag = ar5416Set11nVirtualMoreFrag_20;
143 /**********************/
144 /* Interrupt Handling */
145 /**********************/
147 HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah)
149 a_uint32_t host_isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE);
151 * Some platforms trigger our ISR before applying power to
152 * the card, so make sure.
154 return ((host_isr != AR_INTR_SPURIOUS) && (host_isr & AR_INTR_MAC_IRQ));
157 HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
161 HAL_BOOL fatal_int = AH_FALSE;
162 a_uint32_t sync_cause;
164 if (OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
165 if ((OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) != AR_RTC_STATUS_ON) {
174 isr = OS_REG_READ(ah, AR_ISR_RAC);
175 if (isr == 0xffffffff) {
180 *masked = isr & HAL_INT_COMMON;
182 #ifdef AR5416_INT_MITIGATION
183 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) {
184 *masked |= HAL_INT_RX;
186 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) {
187 *masked |= HAL_INT_TX;
191 if (isr & AR_ISR_BCNMISC) {
194 s2_s = OS_REG_READ(ah, AR_ISR_S2_S);
196 if (s2_s & AR_ISR_S2_GTT) {
197 *masked |= HAL_INT_GTT;
200 if (s2_s & AR_ISR_S2_CST) {
201 *masked |= HAL_INT_CST;
205 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
206 *masked |= HAL_INT_RX;
207 if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) {
208 struct ath_hal_5416 *ahp = AH5416(ah);
209 a_uint32_t s0_s, s1_s;
211 *masked |= HAL_INT_TX;
212 s0_s = OS_REG_READ(ah, AR_ISR_S0_S);
213 s1_s = OS_REG_READ(ah, AR_ISR_S1_S);
214 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
215 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
216 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
217 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
221 sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
222 fatal_int = ((sync_cause != AR_INTR_SPURIOUS) &&
223 (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))) ?
226 if (AH_TRUE == fatal_int) {
227 OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
228 (void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
234 HAL_INT ar5416GetInterrupts(struct ath_hal *ah)
236 return AH5416(ah)->ah_maskReg;
240 ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
242 struct ath_hal_5416 *ahp = AH5416(ah);
243 a_uint32_t omask = ahp->ah_maskReg;
246 if (omask & HAL_INT_GLOBAL) {
247 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
248 (void) OS_REG_READ(ah, AR_IER);
251 mask = ints & HAL_INT_COMMON;
252 if (ints & HAL_INT_TX) {
253 #ifdef AR5416_INT_MITIGATION
254 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
257 mask |= AR_IMR_TXDESC;
259 mask |= AR_IMR_TXERR;
260 mask |= AR_IMR_TXEOL;
262 if (ints & HAL_INT_RX) {
263 mask |= AR_IMR_RXERR;
264 #ifdef AR5416_INT_MITIGATION
265 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
267 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
271 if (ints & (HAL_INT_GTT | HAL_INT_CST)) {
272 mask |= AR_IMR_BCNMISC;
275 OS_REG_WRITE(ah, AR_IMR, mask);
276 (void) OS_REG_READ(ah, AR_IMR);
277 ahp->ah_maskReg = ints;
279 /* Re-enable interrupts if they were enabled before. */
280 if (ints & HAL_INT_GLOBAL) {
281 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
282 /* See explanation above... */
283 (void) OS_REG_READ(ah, AR_IER);
286 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
287 OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
288 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ALL);
297 HAL_STATUS ar5416GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
298 a_uint32_t capability, a_uint32_t *result)
301 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
302 #ifndef MAGPIE_MERLIN // K2
303 pCap->halRxStbcSupport = 1; /* K2 supports STBC Rx only */
304 pCap->halTxStbcSupport = 0;
306 pCap->halRxStbcSupport = 1; /* number of streams for STBC recieve. */
307 pCap->halTxStbcSupport = 1;
312 case HAL_CAP_RX_STBC:
314 *result = pCap->halRxStbcSupport;
317 case HAL_CAP_TX_STBC:
319 *result = pCap->halTxStbcSupport;
324 return ath_hal_getcapability(ah, type, capability, result);
332 u_int64_t ar5416GetTsf64(struct ath_hal *ah)
336 tsf = OS_REG_READ(ah, AR_TSF_U32);
337 tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32);
342 a_uint32_t ar5416GetTsf32(struct ath_hal *ah)
344 return OS_REG_READ(ah, AR_TSF_L32);
347 void ar5416ResetTsf(struct ath_hal *ah)
353 while (OS_REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
360 OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
367 a_uint32_t ar5416GetRxDP(struct ath_hal *ath)
369 return OS_REG_READ(ath, AR_RXDP);
373 void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp)
375 OS_REG_WRITE(ah, AR_RXDP, rxdp);
376 HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
379 void ar5416SetMulticastFilter(struct ath_hal *ah, a_uint32_t filter0, a_uint32_t filter1)
381 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
382 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
385 HAL_BOOL ar5416ClrMulticastFilterIndex(struct ath_hal *ah, a_uint32_t ix)
392 val = OS_REG_READ(ah, AR_MCAST_FIL1);
393 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
395 val = OS_REG_READ(ah, AR_MCAST_FIL0);
396 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
401 HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah)
403 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
404 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
411 HAL_BOOL ar5416SetMulticastFilterIndex(struct ath_hal *ah, a_uint32_t ix)
418 val = OS_REG_READ(ah, AR_MCAST_FIL1);
419 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));
421 val = OS_REG_READ(ah, AR_MCAST_FIL0);
422 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));
427 void ar5416StartPcuReceive(struct ath_hal *ah)
429 OS_REG_CLR_BIT(ah, AR_DIAG_SW,
430 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
433 void ar5416SetRxFilter(struct ath_hal *ah, a_uint32_t bits)
437 OS_REG_WRITE(ah, AR_RX_FILTER, (bits & 0xff) | AR_RX_COMPR_BAR);
439 if (bits & HAL_RX_FILTER_PHYRADAR)
440 phybits |= AR_PHY_ERR_RADAR;
441 if (bits & HAL_RX_FILTER_PHYERR)
442 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
443 OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
445 OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
447 OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
451 void ar5416EnableReceive(struct ath_hal *ah)
453 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
456 void ar5416StopPcuReceive(struct ath_hal *ah)
458 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
461 HAL_BOOL ar5416SetupRxDesc_20(struct ath_hal *ah, struct ath_rx_desc *ds,
462 a_uint32_t size, a_uint32_t flags)
464 struct ar5416_desc *ads = AR5416DESC(ds);
466 HALASSERT((size &~ AR_BufLen) == 0);
468 ads->ds_ctl1 = size & AR_BufLen;
469 if (flags & HAL_RXDESC_INTREQ)
470 ads->ds_ctl1 |= AR_RxIntrReq;
472 /* this should be enough */
473 ads->ds_rxstatus8 &= ~AR_RxDone;
478 HAL_STATUS ar5416ProcRxDescFast_20(struct ath_hal *ah, struct ath_rx_desc *ds,
479 a_uint32_t pa, struct ath_desc *nds,
480 struct ath_rx_status *rx_stats)
482 struct ar5416_desc ads;
483 struct ar5416_desc *adsp = AR5416DESC(ds);
484 struct ar5416_desc *ands = AR5416DESC(nds);
486 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
487 return HAL_EINPROGRESS;
489 * Given the use of a self-linked tail be very sure that the hw is
490 * done with this descriptor; the hw may have done this descriptor
491 * once and picked it up again...make sure the hw has moved on.
493 if ((ands->ds_rxstatus8 & AR_RxDone) == 0
494 && OS_REG_READ(ah, AR_RXDP) == pa)
495 return HAL_EINPROGRESS;
498 * Now we need to get the stats from the descriptor. Since desc are
499 * uncached, lets make a copy of the stats first. Note that, since we
500 * touch most of the rx stats, a memcpy would always be more efficient
502 * Next we fill in all values in a caller passed stack variable.
503 * This reduces the number of uncached accesses.
504 * Do this copy here, after the check so that when the checks fail, we
505 * dont end up copying the entire stats uselessly.
507 ads.u.rx = adsp->u.rx;
509 rx_stats->rs_status = 0;
510 rx_stats->rs_flags = 0;
512 rx_stats->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
513 rx_stats->rs_tstamp = ads.AR_RcvTimestamp;
515 /* XXX what about KeyCacheMiss? */
516 rx_stats->rs_rssi_combined =
517 MS(ads.ds_rxstatus4, AR_RxRSSICombined);
518 rx_stats->rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00);
519 rx_stats->rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01);
520 rx_stats->rs_rssi_ctl2 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt02);
521 rx_stats->rs_rssi_ext0 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt10);
522 rx_stats->rs_rssi_ext1 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt11);
523 rx_stats->rs_rssi_ext2 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt12);
524 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
525 rx_stats->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
527 rx_stats->rs_keyix = HAL_RXKEYIX_INVALID;
528 /* NB: caller expected to do rate table mapping */
529 rx_stats->rs_rate = RXSTATUS_RATE(ah, (&ads));
530 rx_stats->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
532 rx_stats->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
533 rx_stats->rs_moreaggr = (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
534 rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_GI) ? HAL_RX_GI : 0;
535 rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_2040) ? HAL_RX_2040 : 0;
537 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
538 rx_stats->rs_flags |= HAL_RX_DELIM_CRC_PRE;
539 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
540 rx_stats->rs_flags |= HAL_RX_DELIM_CRC_POST;
541 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
542 rx_stats->rs_flags |= HAL_RX_DECRYPT_BUSY;
544 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
546 * These four bits should not be set together. The
547 * 5416 spec states a Michael error can only occur if
548 * DecryptCRCErr not set (and TKIP is used). Experience
549 * indicates however that you can also get Michael errors
550 * when a CRC error is detected, but these are specious.
551 * Consequently we filter them out here so we don't
552 * confuse and/or complicate drivers.
554 if (ads.ds_rxstatus8 & AR_CRCErr)
555 rx_stats->rs_status |= HAL_RXERR_CRC;
556 else if (ads.ds_rxstatus8 & AR_PHYErr) {
559 rx_stats->rs_status |= HAL_RXERR_PHY;
560 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
561 rx_stats->rs_phyerr = phyerr;
562 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
563 rx_stats->rs_status |= HAL_RXERR_DECRYPT;
564 else if (ads.ds_rxstatus8 & AR_MichaelErr)
565 rx_stats->rs_status |= HAL_RXERR_MIC;
567 rx_stats->evm0=ads.AR_RxEVM0;
568 rx_stats->evm1=ads.AR_RxEVM1;
569 rx_stats->evm2=ads.AR_RxEVM2;
578 HAL_BOOL ar5416UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
580 struct ath_hal_5416 *ahp = AH5416(ah);
581 a_uint32_t txcfg, curLevel, newLevel;
585 * Disable interrupts while futzing with the fifo level.
587 omask = ar5416SetInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL);
589 txcfg = OS_REG_READ(ah, AR_TXCFG);
590 curLevel = MS(txcfg, AR_FTRIG);
594 if (curLevel < MAX_TX_FIFO_THRESHOLD)
596 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
598 if (newLevel != curLevel)
599 OS_REG_WRITE(ah, AR_TXCFG,
600 (txcfg &~ AR_FTRIG) | SM(newLevel, AR_FTRIG));
602 /* re-enable chip interrupts */
603 ar5416SetInterrupts(ah, omask);
605 return (newLevel != curLevel);
608 a_uint32_t ar5416GetTxDP(struct ath_hal *ah, a_uint32_t q)
610 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
611 return OS_REG_READ(ah, AR_QTXDP(q));
614 HAL_BOOL ar5416SetTxDP(struct ath_hal *ah, a_uint32_t q, a_uint32_t txdp)
616 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
617 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
620 * Make sure that TXE is deasserted before setting the TXDP. If TXE
621 * is still asserted, setting TXDP will have no effect.
623 HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0);
625 OS_REG_WRITE(ah, AR_QTXDP(q), txdp);
630 HAL_BOOL ar5416StartTxDma(struct ath_hal *ah, a_uint32_t q)
632 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
633 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
635 /* Check to be sure we're not enabling a q that has its TXD bit set. */
636 HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1 << q)) == 0);
638 OS_REG_WRITE(ah, AR_Q_TXE, 1 << q);
643 a_uint32_t ar5416NumTxPending(struct ath_hal *ah, a_uint32_t q)
647 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
648 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
650 npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
653 * Pending frame count (PFC) can momentarily go to zero
654 * while TXE remains asserted. In other words a PFC of
655 * zero is not sufficient to say that the queue has stopped.
657 if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q))
661 if (npend && (AH5416(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) {
662 if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) {
663 isrPrintf("RTSD on CAB queue\n");
664 /* Clear the ReadyTime shutdown status bits */
665 OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q);
672 HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah)
677 * set txd on all queues
679 OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
684 OS_REG_SET_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF));
685 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
686 OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
689 * wait on all tx queues
691 for (q = 0; q < AR_NUM_QCU; q++) {
692 for (i = 0; i < AR5416_ABORT_LOOPS; i++) {
693 if (!ar5416NumTxPending(ah, q))
696 OS_DELAY(AR5416_ABORT_WAIT);
698 if (i == AR5416_ABORT_LOOPS) {
704 * clear tx abort bits
706 OS_REG_CLR_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF));
707 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
708 OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
713 OS_REG_WRITE(ah, AR_Q_TXD, 0);
718 HAL_BOOL ar5416StopTxDma(struct ath_hal*ah, a_uint32_t q)
722 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
724 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
726 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
727 for (i = 1000; i != 0; i--) {
728 if (ar5416NumTxPending(ah, q) == 0)
730 OS_DELAY(100); /* XXX get actual value */
733 OS_REG_WRITE(ah, AR_Q_TXD, 0);
737 void ar5416GetTxIntrQueue(struct ath_hal *ah, a_uint32_t *txqs)
739 struct ath_hal_5416 *ahp = AH5416(ah);
740 *txqs &= ahp->ah_intrTxqs;
741 ahp->ah_intrTxqs &= ~(*txqs);
744 void ar5416IntrReqTxDesc_20(struct ath_hal *ah, struct ath_desc *ds)
746 struct ar5416_desc *ads = AR5416DESC(ds);
747 ads->ds_ctl0 |= AR_TxIntrReq;
750 HAL_BOOL ar5416SetupTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
755 a_uint32_t txRate0, a_uint32_t txTries0,
759 a_uint32_t rtsctsRate,
760 a_uint32_t rtsctsDuration,
761 a_uint32_t compicvLen,
762 a_uint32_t compivLen,
765 #define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
767 struct ar5416_desc *ads = AR5416DESC(ds);
771 ads->ds_txstatus9 &= ~AR_TxDone;
773 HALASSERT(txTries0 != 0);
774 HALASSERT(isValidPktType(type));
775 HALASSERT(isValidTxRate(txRate0));
776 HALASSERT((flags & RTSCTS) != RTSCTS);
781 ads->ds_ctl0 = (pktLen & AR_FrameLen)
782 | (txPower << AR_XmitPower_S)
783 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
784 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
785 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0);
787 ads->ds_ctl1 = (type << AR_FrameType_S)
788 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0);
789 ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0);
790 ads->ds_ctl3 = (txRate0 << AR_XmitRate0_S);
792 ads->ds_ctl7 = SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel0)
793 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel1)
794 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel2)
795 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel3);
797 if (keyIx != HAL_TXKEYIX_INVALID) {
798 /* XXX validate key index */
799 ads->ds_ctl1 |= SM(keyIx, AR_DestIdx);
800 ads->ds_ctl0 |= AR_DestIdxValid;
803 if (flags & RTSCTS) {
804 if (!isValidTxRate(rtsctsRate)) {
807 /* XXX validate rtsctsDuration */
808 ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0)
809 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0);
810 ads->ds_ctl2 |= SM(rtsctsDuration, AR_BurstDur);
811 ads->ds_ctl3 |= (rtsctsRate << AR_RTSCTSRate_S);
818 HAL_BOOL ar5416FillTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
819 a_uint32_t segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
820 const struct ath_tx_desc *ds0)
822 struct ar5416_desc *ads = AR5416DESC(ds);
824 HALASSERT((segLen &~ AR_BufLen) == 0);
828 * First descriptor, don't clobber xmit control data
829 * setup by ar5416SetupTxDesc.
831 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
832 } else if (lastSeg) {
834 * Last descriptor in a multi-descriptor frame,
835 * copy the multi-rate transmit parameters from
836 * the first frame for processing on completion.
839 ads->ds_ctl1 = segLen;
840 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
841 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
844 * Intermediate descriptor in a multi-descriptor frame.
847 ads->ds_ctl1 = segLen | AR_TxMore;
851 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
856 HAL_BOOL ar5416FillKeyTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
857 HAL_KEY_TYPE keyType)
859 struct ar5416_desc *ads = AR5416DESC(ds);
861 ads->ds_ctl6 = SM(keyType, AR_EncrType);
865 HAL_STATUS ar5416ProcTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *gds)
867 struct ar5416_desc *ads = AR5416DESC(gds);
868 struct ath_tx_desc *ds = (struct ath_tx_desc *)gds;
870 if ((ads->ds_txstatus9 & AR_TxDone) == 0)
871 return HAL_EINPROGRESS;
873 ads->ds_txstatus9 &= ~AR_TxDone;
875 /* Update software copies of the HW status */
876 ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
877 ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp;
878 ds->ds_txstat.ts_status = 0;
879 ds->ds_txstat.ts_flags = 0;
881 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
882 ds->ds_txstat.ts_status |= HAL_TXERR_XRETRY;
883 if (ads->ds_txstatus1 & AR_Filtered)
884 ds->ds_txstat.ts_status |= HAL_TXERR_FILT;
885 if (ads->ds_txstatus1 & AR_FIFOUnderrun)
886 ds->ds_txstat.ts_status |= HAL_TXERR_FIFO;
887 if (ads->ds_txstatus9 & AR_TxOpExceeded)
888 ds->ds_txstat.ts_status |= HAL_TXERR_XTXOP;
889 if (ads->ds_txstatus1 & AR_TxTimerExpired)
890 ds->ds_txstat.ts_status |= HAL_TXERR_TIMER_EXPIRED;
892 if (ads->ds_txstatus1 & AR_DescCfgErr)
893 ds->ds_txstat.ts_flags |= HAL_TX_DESC_CFG_ERR;
894 if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
895 ds->ds_txstat.ts_flags |= HAL_TX_DATA_UNDERRUN;
896 ar5416UpdateTxTrigLevel(ah, AH_TRUE);
898 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
899 ds->ds_txstat.ts_flags |= HAL_TX_DELIM_UNDERRUN;
900 ar5416UpdateTxTrigLevel(ah, AH_TRUE);
902 if (ads->ds_txstatus0 & AR_TxBaStatus) {
903 ds->ds_txstat.ts_flags |= HAL_TX_BA;
904 ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
905 ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
909 * Extract the transmit rate used and mark the rate as
910 * ``alternate'' if it wasn't the series 0 rate.
912 ds->ds_txstat.ts_rate = MS(ads->ds_txstatus9, AR_FinalTxIdx);
913 ds->ds_txstat.ts_rssi_combined =
914 MS(ads->ds_txstatus5, AR_TxRSSICombined);
915 ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
916 ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
917 ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
918 ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
919 ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
920 ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
921 ds->ds_txstat.evm0 = ads->AR_TxEVM0;
922 ds->ds_txstat.evm1 = ads->AR_TxEVM1;
923 ds->ds_txstat.evm2 = ads->AR_TxEVM2;
924 ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
925 ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
926 ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
927 ds->ds_txstat.ts_antenna = 0; /* ignored for owl */
932 void ar5416Set11nTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *ds,
933 a_uint32_t pktLen, HAL_PKT_TYPE type, a_uint32_t txPower,
934 a_uint32_t keyIx, HAL_KEY_TYPE keyType,
937 struct ar5416_desc *ads = AR5416DESC(ds);
939 HALASSERT(isValidPktType(type));
940 HALASSERT(isValidKeyType(keyType));
945 ads->ds_ctl0 = (pktLen & AR_FrameLen)
946 | (flags & HAL_TXDESC_VMF ? AR_VirtMoreFrag : 0)
947 | SM(txPower, AR_XmitPower)
948 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0)
949 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
950 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
951 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0)
952 | (keyIx != HAL_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
953 | (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0);
955 ads->ds_ctl1 = (keyIx != HAL_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
956 | SM(type, AR_FrameType)
957 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0)
958 | (flags & HAL_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
959 | (flags & HAL_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
961 ads->ds_ctl6 = SM(keyType, AR_EncrType);
966 void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_tx_desc *ds,
967 a_uint32_t durUpdateEn, a_uint32_t rtsctsRate,
968 a_uint32_t rtsctsDuration,
969 HAL_11N_RATE_SERIES series[], a_uint32_t nseries,
972 struct ar5416_desc *ads = AR5416DESC(ds);
975 HALASSERT(nseries == 4);
979 * Rate control settings override
981 ds_ctl0 = ads->ds_ctl0;
983 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
984 if (flags & HAL_TXDESC_RTSENA) {
985 ds_ctl0 &= ~AR_CTSEnable;
986 ds_ctl0 |= AR_RTSEnable;
988 ds_ctl0 &= ~AR_RTSEnable;
989 ds_ctl0 |= AR_CTSEnable;
992 ds_ctl0 = (ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
995 ads->ds_ctl0 = ds_ctl0;
997 ads->ds_ctl2 = set11nTries(series, 0)
998 | set11nTries(series, 1)
999 | set11nTries(series, 2)
1000 | set11nTries(series, 3)
1001 | (durUpdateEn ? AR_DurUpdateEn : 0);
1003 ads->ds_ctl3 = set11nRate(series, 0)
1004 | set11nRate(series, 1)
1005 | set11nRate(series, 2)
1006 | set11nRate(series, 3);
1008 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
1009 | set11nPktDurRTSCTS(series, 1);
1011 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
1012 | set11nPktDurRTSCTS(series, 3);
1014 ads->ds_ctl7 = set11nRateFlags(series, 0)
1015 | set11nRateFlags(series, 1)
1016 | set11nRateFlags(series, 2)
1017 | set11nRateFlags(series, 3)
1018 | SM(rtsctsRate, AR_RTSCTSRate);
1023 void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_tx_desc *ds,
1024 a_uint32_t durUpdateEn, a_uint32_t rtsctsRate,
1025 a_uint32_t rtsctsDuration,
1026 HAL_11N_RATE_SERIES series[], a_uint32_t nseries,
1029 struct ar5416_desc *ads = AR5416DESC(ds);
1032 HALASSERT(nseries == 4);
1036 * Rate control settings override
1038 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
1039 ds_ctl0 = ads->ds_ctl0;
1041 if (flags & HAL_TXDESC_RTSENA) {
1042 ds_ctl0 &= ~AR_CTSEnable;
1043 ds_ctl0 |= AR_RTSEnable;
1045 ds_ctl0 &= ~AR_RTSEnable;
1046 ds_ctl0 |= AR_CTSEnable;
1049 ads->ds_ctl0 = ds_ctl0;
1052 ads->ds_ctl2 = set11nTries(series, 0)
1053 | set11nTries(series, 1)
1054 | set11nTries(series, 2)
1055 | set11nTries(series, 3)
1056 | (durUpdateEn ? AR_DurUpdateEn : 0);
1058 ads->ds_ctl3 = set11nRate(series, 0)
1059 | set11nRate(series, 1)
1060 | set11nRate(series, 2)
1061 | set11nRate(series, 3);
1063 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
1064 | set11nPktDurRTSCTS(series, 1);
1066 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
1067 | set11nPktDurRTSCTS(series, 3);
1069 ads->ds_ctl7 = set11nRateFlags(series, 0)
1070 | set11nRateFlags(series, 1)
1071 | set11nRateFlags(series, 2)
1072 | set11nRateFlags(series, 3)
1073 | SM(rtsctsRate, AR_RTSCTSRate);
1078 void ar5416Set11nAggrFirst_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uint32_t aggrLen,
1079 a_uint32_t numDelims)
1081 struct ar5416_desc *ads = AR5416DESC(ds);
1083 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
1085 ads->ds_ctl6 &= ~(AR_AggrLen | AR_PadDelim);
1086 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen) |
1087 SM(numDelims, AR_PadDelim);
1090 void ar5416Set11nAggrMiddle_20(struct ath_hal *ah, struct ath_tx_desc *ds, a_uint32_t numDelims)
1092 struct ar5416_desc *ads = AR5416DESC(ds);
1095 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
1098 * We use a stack variable to manipulate ctl6 to reduce uncached
1099 * read modify, modfiy, write.
1101 ctl6 = ads->ds_ctl6;
1102 ctl6 &= ~AR_PadDelim;
1103 ctl6 |= SM(numDelims, AR_PadDelim);
1104 ads->ds_ctl6 = ctl6;
1107 void ar5416Set11nAggrLast_20(struct ath_hal *ah, struct ath_tx_desc *ds)
1109 struct ar5416_desc *ads = AR5416DESC(ds);
1111 ads->ds_ctl1 |= AR_IsAggr;
1112 ads->ds_ctl1 &= ~AR_MoreAggr;
1113 ads->ds_ctl6 &= ~AR_PadDelim;
1116 void ar5416Clr11nAggr_20(struct ath_hal *ah, struct ath_tx_desc *ds)
1118 struct ar5416_desc *ads = AR5416DESC(ds);
1120 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
1123 void ar5416Set11nBurstDuration_20(struct ath_hal *ah, struct ath_tx_desc *ds,
1124 a_uint32_t burstDuration)
1126 struct ar5416_desc *ads = AR5416DESC(ds);
1128 ads->ds_ctl2 &= ~AR_BurstDur;
1129 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
1132 void ar5416Set11nVirtualMoreFrag_20(struct ath_hal *ah, struct ath_tx_desc *ds,
1135 struct ar5416_desc *ads = AR5416DESC(ds);
1138 ads->ds_ctl0 |= AR_VirtMoreFrag;
1140 ads->ds_ctl0 &= ~AR_VirtMoreFrag;