2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
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6 * modification, are permitted (subject to the limitations in the
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13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
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19 * from this software without specific prior written permission.
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22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
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33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include "ah_internal.h"
40 #include "ar5416reg.h"
41 #include "ar5416phy.h"
42 #include "ar5416desc.h"
44 #define N(a) (sizeof(a)/sizeof(a[0]))
45 #define AR_INTR_SPURIOUS 0xffffffff
46 #define ar5416_desc ar5416_desc_20
47 #define AR5416_ABORT_LOOPS 1000
48 #define AR5416_ABORT_WAIT 5
49 #define AR5416DESC AR5416DESC_20
50 #define AR5416DESC_CONST AR5416DESC_CONST_20
56 static const struct ath_hal_private ar5416hal_10 = {{
57 .ah_getRateTable = ar5416GetRateTable,
58 .ah_detach = ar5416Detach,
60 /* Transmit functions */
61 .ah_updateTxTrigLevel = ar5416UpdateTxTrigLevel,
62 .ah_getTxDP = ar5416GetTxDP,
63 .ah_setTxDP = ar5416SetTxDP,
64 .ah_numTxPending = ar5416NumTxPending,
65 .ah_startTxDma = ar5416StartTxDma,
66 .ah_stopTxDma = ar5416StopTxDma,
68 .ah_getTxIntrQueue = ar5416GetTxIntrQueue,
69 .ah_abortTxDma = ar5416AbortTxDma,
72 .ah_getCapability = ar5416GetCapability,
73 .ah_getTsf32 = ar5416GetTsf32,
74 .ah_getTsf64 = ar5416GetTsf64,
75 .ah_resetTsf = ar5416ResetTsf,
76 .ah_setRxFilter = ar5416SetRxFilter,
79 .ah_getRxDP = ar5416GetRxDP,
80 .ah_setRxDP = ar5416SetRxDP,
81 .ah_stopDmaReceive = ar5416StopDmaReceive,
82 .ah_enableReceive = ar5416EnableReceive,
83 .ah_startPcuReceive = ar5416StartPcuReceive,
84 .ah_stopPcuReceive = ar5416StopPcuReceive,
86 /* Interrupt Functions */
87 .ah_isInterruptPending = ar5416IsInterruptPending,
88 .ah_getPendingInterrupts = ar5416GetPendingInterrupts,
89 .ah_getInterrupts = ar5416GetInterrupts,
90 .ah_setInterrupts = ar5416SetInterrupts,
94 void ar5416Detach(struct ath_hal *ah)
96 HALASSERT(ah != AH_NULL);
101 ar5416Attach(a_uint32_t devid,HAL_SOFTC sc, adf_os_device_t dev,
102 HAL_BUS_HANDLE sh, a_uint32_t flags, HAL_STATUS *status)
104 struct ath_hal_5416 *ahp;
107 ahp = ath_hal_malloc(sizeof (struct ath_hal_5416));
108 if (ahp == AH_NULL) {
109 *status = HAL_ENOMEM;
112 ah = &ahp->ah_priv.h;
114 OS_MEMCPY(&ahp->ah_priv, &ar5416hal_10, sizeof(struct ath_hal_private));
120 /* If its a Owl 2.0 chip then change the hal structure to
121 point to the Owl 2.0 ar5416_hal_20 structure */
123 ah->ah_set11nTxDesc = ar5416Set11nTxDesc_20;
124 ah->ah_set11nRateScenario = ar5416Set11nRateScenario_20;
125 ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst_20;
126 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle_20;
127 ah->ah_set11nAggrLast = ar5416Set11nAggrLast_20;
128 ah->ah_clr11nAggr = ar5416Clr11nAggr_20;
129 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration_20;
130 ah->ah_setupRxDesc = ar5416SetupRxDesc_20;
131 ah->ah_procRxDescFast = ar5416ProcRxDescFast_20;
132 ah->ah_updateCTSForBursting = NULL;
133 ah->ah_setupTxDesc = ar5416SetupTxDesc_20;
134 ah->ah_reqTxIntrDesc = ar5416IntrReqTxDesc_20;
135 ah->ah_fillTxDesc = ar5416FillTxDesc_20;
136 ah->ah_fillKeyTxDesc = ar5416FillKeyTxDesc_20;
137 ah->ah_procTxDesc = ar5416ProcTxDesc_20;
138 ah->ah_set11nVirtualMoreFrag = ar5416Set11nVirtualMoreFrag_20;
144 /**********************/
145 /* Interrupt Handling */
146 /**********************/
148 HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah)
150 a_uint32_t host_isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE);
152 * Some platforms trigger our ISR before applying power to
153 * the card, so make sure.
155 return ((host_isr != AR_INTR_SPURIOUS) && (host_isr & AR_INTR_MAC_IRQ));
158 HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
162 HAL_BOOL fatal_int = AH_FALSE;
163 a_uint32_t sync_cause;
165 if (OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
166 if ((OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) != AR_RTC_STATUS_ON) {
175 isr = OS_REG_READ(ah, AR_ISR_RAC);
176 if (isr == 0xffffffff) {
181 *masked = isr & HAL_INT_COMMON;
183 #ifdef AR5416_INT_MITIGATION
184 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) {
185 *masked |= HAL_INT_RX;
187 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) {
188 *masked |= HAL_INT_TX;
192 if (isr & AR_ISR_BCNMISC) {
195 s2_s = OS_REG_READ(ah, AR_ISR_S2_S);
197 if (s2_s & AR_ISR_S2_GTT) {
198 *masked |= HAL_INT_GTT;
201 if (s2_s & AR_ISR_S2_CST) {
202 *masked |= HAL_INT_CST;
206 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
207 *masked |= HAL_INT_RX;
208 if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) {
209 struct ath_hal_5416 *ahp = AH5416(ah);
210 a_uint32_t s0_s, s1_s;
212 *masked |= HAL_INT_TX;
213 s0_s = OS_REG_READ(ah, AR_ISR_S0_S);
214 s1_s = OS_REG_READ(ah, AR_ISR_S1_S);
215 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
216 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
217 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
218 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
222 sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
223 fatal_int = ((sync_cause != AR_INTR_SPURIOUS) &&
224 (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))) ?
227 if (AH_TRUE == fatal_int) {
228 OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
229 (void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
235 HAL_INT ar5416GetInterrupts(struct ath_hal *ah)
237 return AH5416(ah)->ah_maskReg;
241 ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
243 struct ath_hal_5416 *ahp = AH5416(ah);
244 a_uint32_t omask = ahp->ah_maskReg;
247 if (omask & HAL_INT_GLOBAL) {
248 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
249 (void) OS_REG_READ(ah, AR_IER);
252 mask = ints & HAL_INT_COMMON;
253 if (ints & HAL_INT_TX) {
254 #ifdef AR5416_INT_MITIGATION
255 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
258 mask |= AR_IMR_TXDESC;
260 mask |= AR_IMR_TXERR;
261 mask |= AR_IMR_TXEOL;
263 if (ints & HAL_INT_RX) {
264 mask |= AR_IMR_RXERR;
265 #ifdef AR5416_INT_MITIGATION
266 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
268 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
272 if (ints & (HAL_INT_GTT | HAL_INT_CST)) {
273 mask |= AR_IMR_BCNMISC;
276 OS_REG_WRITE(ah, AR_IMR, mask);
277 (void) OS_REG_READ(ah, AR_IMR);
278 ahp->ah_maskReg = ints;
280 /* Re-enable interrupts if they were enabled before. */
281 if (ints & HAL_INT_GLOBAL) {
282 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
283 /* See explanation above... */
284 (void) OS_REG_READ(ah, AR_IER);
287 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
288 OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
289 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ALL);
298 HAL_STATUS ar5416GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
299 a_uint32_t capability, a_uint32_t *result)
302 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
303 #ifndef MAGPIE_MERLIN // K2
304 pCap->halRxStbcSupport = 1; /* K2 supports STBC Rx only */
305 pCap->halTxStbcSupport = 0;
307 pCap->halRxStbcSupport = 1; /* number of streams for STBC recieve. */
308 pCap->halTxStbcSupport = 1;
313 case HAL_CAP_RX_STBC:
315 *result = pCap->halRxStbcSupport;
318 case HAL_CAP_TX_STBC:
320 *result = pCap->halTxStbcSupport;
325 return ath_hal_getcapability(ah, type, capability, result);
333 u_int64_t ar5416GetTsf64(struct ath_hal *ah)
337 tsf = OS_REG_READ(ah, AR_TSF_U32);
338 tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32);
343 a_uint32_t ar5416GetTsf32(struct ath_hal *ah)
345 return OS_REG_READ(ah, AR_TSF_L32);
348 void ar5416ResetTsf(struct ath_hal *ah)
354 while (OS_REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
361 OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
368 a_uint32_t ar5416GetRxDP(struct ath_hal *ath)
370 return OS_REG_READ(ath, AR_RXDP);
374 void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp)
376 OS_REG_WRITE(ah, AR_RXDP, rxdp);
377 HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
380 void ar5416SetMulticastFilter(struct ath_hal *ah, a_uint32_t filter0, a_uint32_t filter1)
382 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
383 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
386 HAL_BOOL ar5416ClrMulticastFilterIndex(struct ath_hal *ah, a_uint32_t ix)
393 val = OS_REG_READ(ah, AR_MCAST_FIL1);
394 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
396 val = OS_REG_READ(ah, AR_MCAST_FIL0);
397 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
402 HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah)
404 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
405 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
412 HAL_BOOL ar5416SetMulticastFilterIndex(struct ath_hal *ah, a_uint32_t ix)
419 val = OS_REG_READ(ah, AR_MCAST_FIL1);
420 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));
422 val = OS_REG_READ(ah, AR_MCAST_FIL0);
423 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));
428 void ar5416StartPcuReceive(struct ath_hal *ah)
430 OS_REG_CLR_BIT(ah, AR_DIAG_SW,
431 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
434 void ar5416SetRxFilter(struct ath_hal *ah, a_uint32_t bits)
438 OS_REG_WRITE(ah, AR_RX_FILTER, (bits & 0xff) | AR_RX_COMPR_BAR);
440 if (bits & HAL_RX_FILTER_PHYRADAR)
441 phybits |= AR_PHY_ERR_RADAR;
442 if (bits & HAL_RX_FILTER_PHYERR)
443 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
444 OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
446 OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
448 OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
452 void ar5416EnableReceive(struct ath_hal *ah)
454 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
457 void ar5416StopPcuReceive(struct ath_hal *ah)
459 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
462 HAL_BOOL ar5416SetupRxDesc_20(struct ath_hal *ah, struct ath_desc *ds,
463 a_uint32_t size, a_uint32_t flags)
465 struct ar5416_desc *ads = AR5416DESC(ds);
467 HALASSERT((size &~ AR_BufLen) == 0);
469 ads->ds_ctl1 = size & AR_BufLen;
470 if (flags & HAL_RXDESC_INTREQ)
471 ads->ds_ctl1 |= AR_RxIntrReq;
473 /* this should be enough */
474 ads->ds_rxstatus8 &= ~AR_RxDone;
479 HAL_STATUS ar5416ProcRxDescFast_20(struct ath_hal *ah, struct ath_desc *ds,
480 a_uint32_t pa, struct ath_desc *nds,
481 struct ath_rx_status *rx_stats)
483 struct ar5416_desc ads;
484 struct ar5416_desc *adsp = AR5416DESC(ds);
485 struct ar5416_desc *ands = AR5416DESC(nds);
487 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
488 return HAL_EINPROGRESS;
490 * Given the use of a self-linked tail be very sure that the hw is
491 * done with this descriptor; the hw may have done this descriptor
492 * once and picked it up again...make sure the hw has moved on.
494 if ((ands->ds_rxstatus8 & AR_RxDone) == 0
495 && OS_REG_READ(ah, AR_RXDP) == pa)
496 return HAL_EINPROGRESS;
499 * Now we need to get the stats from the descriptor. Since desc are
500 * uncached, lets make a copy of the stats first. Note that, since we
501 * touch most of the rx stats, a memcpy would always be more efficient
503 * Next we fill in all values in a caller passed stack variable.
504 * This reduces the number of uncached accesses.
505 * Do this copy here, after the check so that when the checks fail, we
506 * dont end up copying the entire stats uselessly.
508 ads.u.rx = adsp->u.rx;
510 rx_stats->rs_status = 0;
511 rx_stats->rs_flags = 0;
513 rx_stats->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
514 rx_stats->rs_tstamp = ads.AR_RcvTimestamp;
516 /* XXX what about KeyCacheMiss? */
517 rx_stats->rs_rssi_combined =
518 MS(ads.ds_rxstatus4, AR_RxRSSICombined);
519 rx_stats->rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00);
520 rx_stats->rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01);
521 rx_stats->rs_rssi_ctl2 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt02);
522 rx_stats->rs_rssi_ext0 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt10);
523 rx_stats->rs_rssi_ext1 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt11);
524 rx_stats->rs_rssi_ext2 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt12);
525 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
526 rx_stats->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
528 rx_stats->rs_keyix = HAL_RXKEYIX_INVALID;
529 /* NB: caller expected to do rate table mapping */
530 rx_stats->rs_rate = RXSTATUS_RATE(ah, (&ads));
531 rx_stats->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
533 rx_stats->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
534 rx_stats->rs_moreaggr = (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
535 rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_GI) ? HAL_RX_GI : 0;
536 rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_2040) ? HAL_RX_2040 : 0;
538 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
539 rx_stats->rs_flags |= HAL_RX_DELIM_CRC_PRE;
540 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
541 rx_stats->rs_flags |= HAL_RX_DELIM_CRC_POST;
542 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
543 rx_stats->rs_flags |= HAL_RX_DECRYPT_BUSY;
545 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
547 * These four bits should not be set together. The
548 * 5416 spec states a Michael error can only occur if
549 * DecryptCRCErr not set (and TKIP is used). Experience
550 * indicates however that you can also get Michael errors
551 * when a CRC error is detected, but these are specious.
552 * Consequently we filter them out here so we don't
553 * confuse and/or complicate drivers.
555 if (ads.ds_rxstatus8 & AR_CRCErr)
556 rx_stats->rs_status |= HAL_RXERR_CRC;
557 else if (ads.ds_rxstatus8 & AR_PHYErr) {
560 rx_stats->rs_status |= HAL_RXERR_PHY;
561 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
562 rx_stats->rs_phyerr = phyerr;
563 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
564 rx_stats->rs_status |= HAL_RXERR_DECRYPT;
565 else if (ads.ds_rxstatus8 & AR_MichaelErr)
566 rx_stats->rs_status |= HAL_RXERR_MIC;
568 rx_stats->evm0=ads.AR_RxEVM0;
569 rx_stats->evm1=ads.AR_RxEVM1;
570 rx_stats->evm2=ads.AR_RxEVM2;
579 HAL_BOOL ar5416UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
581 struct ath_hal_5416 *ahp = AH5416(ah);
582 a_uint32_t txcfg, curLevel, newLevel;
586 * Disable interrupts while futzing with the fifo level.
588 omask = ar5416SetInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL);
590 txcfg = OS_REG_READ(ah, AR_TXCFG);
591 curLevel = MS(txcfg, AR_FTRIG);
595 if (curLevel < MAX_TX_FIFO_THRESHOLD)
597 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
599 if (newLevel != curLevel)
600 OS_REG_WRITE(ah, AR_TXCFG,
601 (txcfg &~ AR_FTRIG) | SM(newLevel, AR_FTRIG));
603 /* re-enable chip interrupts */
604 ar5416SetInterrupts(ah, omask);
606 return (newLevel != curLevel);
609 a_uint32_t ar5416GetTxDP(struct ath_hal *ah, a_uint32_t q)
611 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
612 return OS_REG_READ(ah, AR_QTXDP(q));
615 HAL_BOOL ar5416SetTxDP(struct ath_hal *ah, a_uint32_t q, a_uint32_t txdp)
617 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
618 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
621 * Make sure that TXE is deasserted before setting the TXDP. If TXE
622 * is still asserted, setting TXDP will have no effect.
624 HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0);
626 OS_REG_WRITE(ah, AR_QTXDP(q), txdp);
631 HAL_BOOL ar5416StartTxDma(struct ath_hal *ah, a_uint32_t q)
633 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
634 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
636 /* Check to be sure we're not enabling a q that has its TXD bit set. */
637 HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1 << q)) == 0);
639 OS_REG_WRITE(ah, AR_Q_TXE, 1 << q);
644 a_uint32_t ar5416NumTxPending(struct ath_hal *ah, a_uint32_t q)
648 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
649 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
651 npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
654 * Pending frame count (PFC) can momentarily go to zero
655 * while TXE remains asserted. In other words a PFC of
656 * zero is not sufficient to say that the queue has stopped.
658 if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q))
662 if (npend && (AH5416(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) {
663 if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) {
664 isrPrintf("RTSD on CAB queue\n");
665 /* Clear the ReadyTime shutdown status bits */
666 OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q);
673 HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah)
678 * set txd on all queues
680 OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
685 OS_REG_SET_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF));
686 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
687 OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
690 * wait on all tx queues
692 for (q = 0; q < AR_NUM_QCU; q++) {
693 for (i = 0; i < AR5416_ABORT_LOOPS; i++) {
694 if (!ar5416NumTxPending(ah, q))
697 OS_DELAY(AR5416_ABORT_WAIT);
699 if (i == AR5416_ABORT_LOOPS) {
705 * clear tx abort bits
707 OS_REG_CLR_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF));
708 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
709 OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
714 OS_REG_WRITE(ah, AR_Q_TXD, 0);
719 HAL_BOOL ar5416StopTxDma(struct ath_hal*ah, a_uint32_t q)
723 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
725 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
727 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
728 for (i = 1000; i != 0; i--) {
729 if (ar5416NumTxPending(ah, q) == 0)
731 OS_DELAY(100); /* XXX get actual value */
734 OS_REG_WRITE(ah, AR_Q_TXD, 0);
738 void ar5416GetTxIntrQueue(struct ath_hal *ah, a_uint32_t *txqs)
740 struct ath_hal_5416 *ahp = AH5416(ah);
741 *txqs &= ahp->ah_intrTxqs;
742 ahp->ah_intrTxqs &= ~(*txqs);
745 void ar5416IntrReqTxDesc_20(struct ath_hal *ah, struct ath_desc *ds)
747 struct ar5416_desc *ads = AR5416DESC(ds);
748 ads->ds_ctl0 |= AR_TxIntrReq;
751 HAL_BOOL ar5416SetupTxDesc_20(struct ath_hal *ah, struct ath_desc *ds,
756 a_uint32_t txRate0, a_uint32_t txTries0,
760 a_uint32_t rtsctsRate,
761 a_uint32_t rtsctsDuration,
762 a_uint32_t compicvLen,
763 a_uint32_t compivLen,
766 #define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
768 struct ar5416_desc *ads = AR5416DESC(ds);
772 ads->ds_txstatus9 &= ~AR_TxDone;
774 HALASSERT(txTries0 != 0);
775 HALASSERT(isValidPktType(type));
776 HALASSERT(isValidTxRate(txRate0));
777 HALASSERT((flags & RTSCTS) != RTSCTS);
782 ads->ds_ctl0 = (pktLen & AR_FrameLen)
783 | (txPower << AR_XmitPower_S)
784 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
785 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
786 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0);
788 ads->ds_ctl1 = (type << AR_FrameType_S)
789 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0);
790 ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0);
791 ads->ds_ctl3 = (txRate0 << AR_XmitRate0_S);
793 ads->ds_ctl7 = SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel0)
794 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel1)
795 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel2)
796 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel3);
798 if (keyIx != HAL_TXKEYIX_INVALID) {
799 /* XXX validate key index */
800 ads->ds_ctl1 |= SM(keyIx, AR_DestIdx);
801 ads->ds_ctl0 |= AR_DestIdxValid;
804 if (flags & RTSCTS) {
805 if (!isValidTxRate(rtsctsRate)) {
808 /* XXX validate rtsctsDuration */
809 ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0)
810 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0);
811 ads->ds_ctl2 |= SM(rtsctsDuration, AR_BurstDur);
812 ads->ds_ctl3 |= (rtsctsRate << AR_RTSCTSRate_S);
819 HAL_BOOL ar5416FillTxDesc_20(struct ath_hal *ah, struct ath_desc *ds,
820 a_uint32_t segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
821 const struct ath_desc *ds0)
823 struct ar5416_desc *ads = AR5416DESC(ds);
825 HALASSERT((segLen &~ AR_BufLen) == 0);
829 * First descriptor, don't clobber xmit control data
830 * setup by ar5416SetupTxDesc.
832 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
833 } else if (lastSeg) {
835 * Last descriptor in a multi-descriptor frame,
836 * copy the multi-rate transmit parameters from
837 * the first frame for processing on completion.
840 ads->ds_ctl1 = segLen;
841 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
842 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
845 * Intermediate descriptor in a multi-descriptor frame.
848 ads->ds_ctl1 = segLen | AR_TxMore;
852 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
857 HAL_BOOL ar5416FillKeyTxDesc_20(struct ath_hal *ah, struct ath_desc *ds,
858 HAL_KEY_TYPE keyType)
860 struct ar5416_desc *ads = AR5416DESC(ds);
862 ads->ds_ctl6 = SM(keyType, AR_EncrType);
866 HAL_STATUS ar5416ProcTxDesc_20(struct ath_hal *ah, struct ath_desc *gds)
868 struct ar5416_desc *ads = AR5416DESC(gds);
869 struct ath_tx_desc *ds = (struct ath_tx_desc *)gds;
871 if ((ads->ds_txstatus9 & AR_TxDone) == 0)
872 return HAL_EINPROGRESS;
874 ads->ds_txstatus9 &= ~AR_TxDone;
876 /* Update software copies of the HW status */
877 ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
878 ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp;
879 ds->ds_txstat.ts_status = 0;
880 ds->ds_txstat.ts_flags = 0;
882 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
883 ds->ds_txstat.ts_status |= HAL_TXERR_XRETRY;
884 if (ads->ds_txstatus1 & AR_Filtered)
885 ds->ds_txstat.ts_status |= HAL_TXERR_FILT;
886 if (ads->ds_txstatus1 & AR_FIFOUnderrun)
887 ds->ds_txstat.ts_status |= HAL_TXERR_FIFO;
888 if (ads->ds_txstatus9 & AR_TxOpExceeded)
889 ds->ds_txstat.ts_status |= HAL_TXERR_XTXOP;
890 if (ads->ds_txstatus1 & AR_TxTimerExpired)
891 ds->ds_txstat.ts_status |= HAL_TXERR_TIMER_EXPIRED;
893 if (ads->ds_txstatus1 & AR_DescCfgErr)
894 ds->ds_txstat.ts_flags |= HAL_TX_DESC_CFG_ERR;
895 if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
896 ds->ds_txstat.ts_flags |= HAL_TX_DATA_UNDERRUN;
897 ar5416UpdateTxTrigLevel(ah, AH_TRUE);
899 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
900 ds->ds_txstat.ts_flags |= HAL_TX_DELIM_UNDERRUN;
901 ar5416UpdateTxTrigLevel(ah, AH_TRUE);
903 if (ads->ds_txstatus0 & AR_TxBaStatus) {
904 ds->ds_txstat.ts_flags |= HAL_TX_BA;
905 ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
906 ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
910 * Extract the transmit rate used and mark the rate as
911 * ``alternate'' if it wasn't the series 0 rate.
913 ds->ds_txstat.ts_rate = MS(ads->ds_txstatus9, AR_FinalTxIdx);
914 ds->ds_txstat.ts_rssi_combined =
915 MS(ads->ds_txstatus5, AR_TxRSSICombined);
916 ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
917 ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
918 ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
919 ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
920 ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
921 ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
922 ds->ds_txstat.evm0 = ads->AR_TxEVM0;
923 ds->ds_txstat.evm1 = ads->AR_TxEVM1;
924 ds->ds_txstat.evm2 = ads->AR_TxEVM2;
925 ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
926 ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
927 ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
928 ds->ds_txstat.ts_antenna = 0; /* ignored for owl */
933 void ar5416Set11nTxDesc_20(struct ath_hal *ah, struct ath_desc *ds,
934 a_uint32_t pktLen, HAL_PKT_TYPE type, a_uint32_t txPower,
935 a_uint32_t keyIx, HAL_KEY_TYPE keyType,
938 struct ar5416_desc *ads = AR5416DESC(ds);
940 HALASSERT(isValidPktType(type));
941 HALASSERT(isValidKeyType(keyType));
946 ads->ds_ctl0 = (pktLen & AR_FrameLen)
947 | (flags & HAL_TXDESC_VMF ? AR_VirtMoreFrag : 0)
948 | SM(txPower, AR_XmitPower)
949 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0)
950 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
951 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
952 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0)
953 | (keyIx != HAL_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
954 | (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0);
956 ads->ds_ctl1 = (keyIx != HAL_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
957 | SM(type, AR_FrameType)
958 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0)
959 | (flags & HAL_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
960 | (flags & HAL_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
962 ads->ds_ctl6 = SM(keyType, AR_EncrType);
967 void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_desc *ds,
968 a_uint32_t durUpdateEn, a_uint32_t rtsctsRate,
969 a_uint32_t rtsctsDuration,
970 HAL_11N_RATE_SERIES series[], a_uint32_t nseries,
973 struct ar5416_desc *ads = AR5416DESC(ds);
976 HALASSERT(nseries == 4);
980 * Rate control settings override
982 ds_ctl0 = ads->ds_ctl0;
984 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
985 if (flags & HAL_TXDESC_RTSENA) {
986 ds_ctl0 &= ~AR_CTSEnable;
987 ds_ctl0 |= AR_RTSEnable;
989 ds_ctl0 &= ~AR_RTSEnable;
990 ds_ctl0 |= AR_CTSEnable;
993 ds_ctl0 = (ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
996 ads->ds_ctl0 = ds_ctl0;
998 ads->ds_ctl2 = set11nTries(series, 0)
999 | set11nTries(series, 1)
1000 | set11nTries(series, 2)
1001 | set11nTries(series, 3)
1002 | (durUpdateEn ? AR_DurUpdateEn : 0);
1004 ads->ds_ctl3 = set11nRate(series, 0)
1005 | set11nRate(series, 1)
1006 | set11nRate(series, 2)
1007 | set11nRate(series, 3);
1009 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
1010 | set11nPktDurRTSCTS(series, 1);
1012 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
1013 | set11nPktDurRTSCTS(series, 3);
1015 ads->ds_ctl7 = set11nRateFlags(series, 0)
1016 | set11nRateFlags(series, 1)
1017 | set11nRateFlags(series, 2)
1018 | set11nRateFlags(series, 3)
1019 | SM(rtsctsRate, AR_RTSCTSRate);
1024 void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_desc *ds,
1025 a_uint32_t durUpdateEn, a_uint32_t rtsctsRate,
1026 a_uint32_t rtsctsDuration,
1027 HAL_11N_RATE_SERIES series[], a_uint32_t nseries,
1030 struct ar5416_desc *ads = AR5416DESC(ds);
1033 HALASSERT(nseries == 4);
1037 * Rate control settings override
1039 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
1040 ds_ctl0 = ads->ds_ctl0;
1042 if (flags & HAL_TXDESC_RTSENA) {
1043 ds_ctl0 &= ~AR_CTSEnable;
1044 ds_ctl0 |= AR_RTSEnable;
1046 ds_ctl0 &= ~AR_RTSEnable;
1047 ds_ctl0 |= AR_CTSEnable;
1050 ads->ds_ctl0 = ds_ctl0;
1053 ads->ds_ctl2 = set11nTries(series, 0)
1054 | set11nTries(series, 1)
1055 | set11nTries(series, 2)
1056 | set11nTries(series, 3)
1057 | (durUpdateEn ? AR_DurUpdateEn : 0);
1059 ads->ds_ctl3 = set11nRate(series, 0)
1060 | set11nRate(series, 1)
1061 | set11nRate(series, 2)
1062 | set11nRate(series, 3);
1064 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
1065 | set11nPktDurRTSCTS(series, 1);
1067 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
1068 | set11nPktDurRTSCTS(series, 3);
1070 ads->ds_ctl7 = set11nRateFlags(series, 0)
1071 | set11nRateFlags(series, 1)
1072 | set11nRateFlags(series, 2)
1073 | set11nRateFlags(series, 3)
1074 | SM(rtsctsRate, AR_RTSCTSRate);
1079 void ar5416Set11nAggrFirst_20(struct ath_hal *ah, struct ath_desc *ds, a_uint32_t aggrLen,
1080 a_uint32_t numDelims)
1082 struct ar5416_desc *ads = AR5416DESC(ds);
1084 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
1086 ads->ds_ctl6 &= ~(AR_AggrLen | AR_PadDelim);
1087 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen) |
1088 SM(numDelims, AR_PadDelim);
1091 void ar5416Set11nAggrMiddle_20(struct ath_hal *ah, struct ath_desc *ds, a_uint32_t numDelims)
1093 struct ar5416_desc *ads = AR5416DESC(ds);
1096 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
1099 * We use a stack variable to manipulate ctl6 to reduce uncached
1100 * read modify, modfiy, write.
1102 ctl6 = ads->ds_ctl6;
1103 ctl6 &= ~AR_PadDelim;
1104 ctl6 |= SM(numDelims, AR_PadDelim);
1105 ads->ds_ctl6 = ctl6;
1108 void ar5416Set11nAggrLast_20(struct ath_hal *ah, struct ath_desc *ds)
1110 struct ar5416_desc *ads = AR5416DESC(ds);
1112 ads->ds_ctl1 |= AR_IsAggr;
1113 ads->ds_ctl1 &= ~AR_MoreAggr;
1114 ads->ds_ctl6 &= ~AR_PadDelim;
1117 void ar5416Clr11nAggr_20(struct ath_hal *ah, struct ath_desc *ds)
1119 struct ar5416_desc *ads = AR5416DESC(ds);
1121 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
1124 void ar5416Set11nBurstDuration_20(struct ath_hal *ah, struct ath_desc *ds,
1125 a_uint32_t burstDuration)
1127 struct ar5416_desc *ads = AR5416DESC(ds);
1129 ads->ds_ctl2 &= ~AR_BurstDur;
1130 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
1133 void ar5416Set11nVirtualMoreFrag_20(struct ath_hal *ah, struct ath_desc *ds,
1136 struct ar5416_desc *ads = AR5416DESC(ds);
1139 ads->ds_ctl0 |= AR_VirtMoreFrag;
1141 ads->ds_ctl0 &= ~AR_VirtMoreFrag;