2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include "ah_internal.h"
39 #include "ar5416reg.h"
40 #include "ar5416desc.h"
42 #define N(a) (sizeof(a)/sizeof(a[0]))
43 #define AR_INTR_SPURIOUS 0xffffffff
44 #define ar5416_desc ar5416_desc_20
45 #define AR5416_ABORT_LOOPS 1000
46 #define AR5416_ABORT_WAIT 5
47 #define AR5416DESC AR5416DESC_20
48 #define AR5416DESC_CONST AR5416DESC_CONST_20
54 static const struct ath_hal_private ar5416hal_10 = {{
55 .ah_getRateTable = ar5416GetRateTable,
56 .ah_detach = ar5416Detach,
58 /* Transmit functions */
59 .ah_updateTxTrigLevel = ar5416UpdateTxTrigLevel,
60 .ah_setTxDP = ar5416SetTxDP,
61 .ah_numTxPending = ar5416NumTxPending,
62 .ah_startTxDma = ar5416StartTxDma,
63 .ah_stopTxDma = ar5416StopTxDma,
65 .ah_abortTxDma = ar5416AbortTxDma,
68 .ah_getTsf64 = ar5416GetTsf64,
69 .ah_setRxFilter = ar5416SetRxFilter,
72 .ah_setRxDP = ar5416SetRxDP,
73 .ah_stopDmaReceive = ar5416StopDmaReceive,
74 .ah_enableReceive = ar5416EnableReceive,
75 .ah_stopPcuReceive = ar5416StopPcuReceive,
77 /* Interrupt Functions */
78 .ah_isInterruptPending = ar5416IsInterruptPending,
79 .ah_getPendingInterrupts = ar5416GetPendingInterrupts,
80 .ah_setInterrupts = ar5416SetInterrupts,
84 void ar5416Detach(struct ath_hal *ah)
86 HALASSERT(ah != AH_NULL);
91 ar5416Attach(HAL_SOFTC sc, adf_os_device_t dev, HAL_STATUS *status)
93 struct ath_hal_5416 *ahp;
96 ahp = ath_hal_malloc(sizeof (struct ath_hal_5416));
101 ah = &ahp->ah_priv.h;
103 OS_MEMCPY(&ahp->ah_priv, &ar5416hal_10, sizeof(struct ath_hal_private));
108 ah->ah_set11nTxDesc = ar5416Set11nTxDesc_20;
109 ah->ah_set11nRateScenario = ar5416Set11nRateScenario_20;
110 ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst_20;
111 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle_20;
112 ah->ah_set11nAggrLast = ar5416Set11nAggrLast_20;
113 ah->ah_clr11nAggr = ar5416Clr11nAggr_20;
114 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration_20;
115 ah->ah_setupRxDesc = ar5416SetupRxDesc_20;
116 ah->ah_procRxDescFast = ar5416ProcRxDescFast_20;
117 ah->ah_setupTxDesc = ar5416SetupTxDesc_20;
118 ah->ah_fillTxDesc = ar5416FillTxDesc_20;
119 ah->ah_fillKeyTxDesc = ar5416FillKeyTxDesc_20;
120 ah->ah_procTxDesc = ar5416ProcTxDesc_20;
121 ah->ah_set11nVirtualMoreFrag = ar5416Set11nVirtualMoreFrag_20;
126 /**********************/
127 /* Interrupt Handling */
128 /**********************/
130 HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah)
132 a_uint32_t host_isr =
133 ioread32_mac(AR_INTR_ASYNC_CAUSE);
135 * Some platforms trigger our ISR before applying power to
136 * the card, so make sure.
138 return ((host_isr != AR_INTR_SPURIOUS) && (host_isr & AR_INTR_MAC_IRQ));
141 HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
145 HAL_BOOL fatal_int = AH_FALSE;
146 a_uint32_t sync_cause;
148 if (ioread32_mac(AR_INTR_ASYNC_CAUSE)
150 if ((ioread32_mac(AR_RTC_STATUS)
151 & AR_RTC_STATUS_M) != AR_RTC_STATUS_ON) {
160 isr = ioread32_mac(AR_ISR_RAC);
161 if (isr == 0xffffffff) {
166 *masked = isr & HAL_INT_COMMON;
168 #ifdef AR5416_INT_MITIGATION
169 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) {
170 *masked |= HAL_INT_RX;
172 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) {
173 *masked |= HAL_INT_TX;
177 if (isr & AR_ISR_BCNMISC) {
180 s2_s = ioread32_mac(AR_ISR_S2_S);
182 if (s2_s & AR_ISR_S2_GTT) {
183 *masked |= HAL_INT_GTT;
186 if (s2_s & AR_ISR_S2_CST) {
187 *masked |= HAL_INT_CST;
191 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
192 *masked |= HAL_INT_RX;
193 if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) {
194 struct ath_hal_5416 *ahp = AH5416(ah);
195 a_uint32_t s0_s, s1_s;
197 *masked |= HAL_INT_TX;
198 s0_s = ioread32_mac(AR_ISR_S0_S);
199 s1_s = ioread32_mac(AR_ISR_S1_S);
200 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
201 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
202 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
203 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
207 sync_cause = ioread32_mac(AR_INTR_SYNC_CAUSE);
208 fatal_int = ((sync_cause != AR_INTR_SPURIOUS) &&
209 (sync_cause & (AR_INTR_SYNC_HOST1_FATAL
210 | AR_INTR_SYNC_HOST1_PERR))) ? AH_TRUE : AH_FALSE;
212 if (AH_TRUE == fatal_int) {
213 iowrite32_mac(AR_INTR_SYNC_CAUSE_CLR, sync_cause);
214 (void) ioread32_mac(AR_INTR_SYNC_CAUSE_CLR);
221 ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
223 struct ath_hal_5416 *ahp = AH5416(ah);
224 a_uint32_t omask = ahp->ah_maskReg;
227 if (omask & HAL_INT_GLOBAL) {
228 iowrite32_mac(AR_IER, AR_IER_DISABLE);
229 (void) ioread32_mac(AR_IER);
232 mask = ints & HAL_INT_COMMON;
233 if (ints & HAL_INT_TX) {
234 #ifdef AR5416_INT_MITIGATION
235 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
238 mask |= AR_IMR_TXDESC;
240 mask |= AR_IMR_TXERR;
241 mask |= AR_IMR_TXEOL;
243 if (ints & HAL_INT_RX) {
244 mask |= AR_IMR_RXERR;
245 #ifdef AR5416_INT_MITIGATION
246 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
248 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
252 if (ints & (HAL_INT_GTT | HAL_INT_CST)) {
253 mask |= AR_IMR_BCNMISC;
256 iowrite32_mac(AR_IMR, mask);
257 (void) ioread32_mac(AR_IMR);
258 ahp->ah_maskReg = ints;
260 /* Re-enable interrupts if they were enabled before. */
261 if (ints & HAL_INT_GLOBAL) {
262 iowrite32_mac(AR_IER, AR_IER_ENABLE);
263 /* See explanation above... */
264 (void) ioread32_mac(AR_IER);
267 iowrite32_mac(AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
268 iowrite32_mac(AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
269 iowrite32_mac(AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ALL);
278 u_int64_t ar5416GetTsf64(struct ath_hal *ah)
282 tsf = ioread32_mac(AR_TSF_U32);
283 tsf = (tsf << 32) | ioread32_mac(AR_TSF_L32);
291 void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp)
293 iowrite32_mac(AR_RXDP, rxdp);
294 HALASSERT(ioread32_mac(AR_RXDP) == rxdp);
297 HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah)
299 iowrite32_mac(AR_CR, AR_CR_RXD); /* Set receive disable bit */
300 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
307 void ar5416SetRxFilter(struct ath_hal *ah, a_uint32_t bits)
311 iowrite32_mac(AR_RX_FILTER, (bits & 0xff) | AR_RX_COMPR_BAR);
313 if (bits & HAL_RX_FILTER_PHYRADAR)
314 phybits |= AR_PHY_ERR_RADAR;
315 if (bits & HAL_RX_FILTER_PHYERR)
316 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
317 iowrite32_mac(AR_PHY_ERR, phybits);
319 iowrite32_mac(AR_RXCFG,
320 ioread32_mac(AR_RXCFG)
323 iowrite32_mac(AR_RXCFG,
324 ioread32_mac(AR_RXCFG)
329 void ar5416EnableReceive(struct ath_hal *ah)
331 iowrite32_mac(AR_CR, AR_CR_RXE);
334 void ar5416StopPcuReceive(struct ath_hal *ah)
336 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
339 HAL_BOOL ar5416SetupRxDesc_20(struct ath_rx_desc *ds,
340 a_uint32_t size, a_uint32_t flags)
342 struct ar5416_desc *ads = AR5416DESC(ds);
344 HALASSERT((size &~ AR_BufLen) == 0);
346 ads->ds_ctl1 = size & AR_BufLen;
347 if (flags & HAL_RXDESC_INTREQ)
348 ads->ds_ctl1 |= AR_RxIntrReq;
350 /* this should be enough */
351 ads->ds_rxstatus8 &= ~AR_RxDone;
356 HAL_STATUS ar5416ProcRxDescFast_20(struct ath_hal *ah, struct ath_rx_desc *ds,
357 a_uint32_t pa, struct ath_desc *nds,
358 struct ath_rx_status *rx_stats)
360 struct ar5416_desc ads;
361 struct ar5416_desc *adsp = AR5416DESC(ds);
362 struct ar5416_desc *ands = AR5416DESC(nds);
364 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
365 return HAL_EINPROGRESS;
367 * Given the use of a self-linked tail be very sure that the hw is
368 * done with this descriptor; the hw may have done this descriptor
369 * once and picked it up again...make sure the hw has moved on.
371 if ((ands->ds_rxstatus8 & AR_RxDone) == 0
372 && ioread32_mac(AR_RXDP) == pa)
373 return HAL_EINPROGRESS;
376 * Now we need to get the stats from the descriptor. Since desc are
377 * uncached, lets make a copy of the stats first. Note that, since we
378 * touch most of the rx stats, a memcpy would always be more efficient
380 * Next we fill in all values in a caller passed stack variable.
381 * This reduces the number of uncached accesses.
382 * Do this copy here, after the check so that when the checks fail, we
383 * dont end up copying the entire stats uselessly.
385 ads.u.rx = adsp->u.rx;
387 rx_stats->rs_status = 0;
388 rx_stats->rs_flags = 0;
390 rx_stats->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
391 rx_stats->rs_tstamp = ads.AR_RcvTimestamp;
393 /* XXX what about KeyCacheMiss? */
394 rx_stats->rs_rssi_combined =
395 MS(ads.ds_rxstatus4, AR_RxRSSICombined);
396 rx_stats->rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00);
397 rx_stats->rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01);
398 rx_stats->rs_rssi_ctl2 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt02);
399 rx_stats->rs_rssi_ext0 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt10);
400 rx_stats->rs_rssi_ext1 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt11);
401 rx_stats->rs_rssi_ext2 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt12);
402 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
403 rx_stats->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
405 rx_stats->rs_keyix = HAL_RXKEYIX_INVALID;
406 /* NB: caller expected to do rate table mapping */
407 rx_stats->rs_rate = RXSTATUS_RATE(ah, (&ads));
408 rx_stats->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
410 rx_stats->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
411 rx_stats->rs_moreaggr = (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
412 rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_GI) ? HAL_RX_GI : 0;
413 rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_2040) ? HAL_RX_2040 : 0;
415 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
416 rx_stats->rs_flags |= HAL_RX_DELIM_CRC_PRE;
417 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
418 rx_stats->rs_flags |= HAL_RX_DELIM_CRC_POST;
419 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
420 rx_stats->rs_flags |= HAL_RX_DECRYPT_BUSY;
422 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
424 * These four bits should not be set together. The
425 * 5416 spec states a Michael error can only occur if
426 * DecryptCRCErr not set (and TKIP is used). Experience
427 * indicates however that you can also get Michael errors
428 * when a CRC error is detected, but these are specious.
429 * Consequently we filter them out here so we don't
430 * confuse and/or complicate drivers.
432 if (ads.ds_rxstatus8 & AR_CRCErr)
433 rx_stats->rs_status |= HAL_RXERR_CRC;
434 else if (ads.ds_rxstatus8 & AR_PHYErr) {
437 rx_stats->rs_status |= HAL_RXERR_PHY;
438 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
439 rx_stats->rs_phyerr = phyerr;
440 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
441 rx_stats->rs_status |= HAL_RXERR_DECRYPT;
442 else if (ads.ds_rxstatus8 & AR_MichaelErr)
443 rx_stats->rs_status |= HAL_RXERR_MIC;
445 rx_stats->evm0=ads.AR_RxEVM0;
446 rx_stats->evm1=ads.AR_RxEVM1;
447 rx_stats->evm2=ads.AR_RxEVM2;
456 HAL_BOOL ar5416UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
458 struct ath_hal_5416 *ahp = AH5416(ah);
459 a_uint32_t txcfg, curLevel, newLevel;
463 * Disable interrupts while futzing with the fifo level.
465 omask = ar5416SetInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL);
467 txcfg = ioread32_mac(AR_TXCFG);
468 curLevel = MS(txcfg, AR_FTRIG);
472 if (curLevel < MAX_TX_FIFO_THRESHOLD)
474 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
476 if (newLevel != curLevel)
477 iowrite32_mac(AR_TXCFG,
478 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
480 /* re-enable chip interrupts */
481 ar5416SetInterrupts(ah, omask);
483 return (newLevel != curLevel);
486 HAL_BOOL ar5416SetTxDP(struct ath_hal *ah, a_uint32_t q, a_uint32_t txdp)
488 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
489 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
492 * Make sure that TXE is deasserted before setting the TXDP. If TXE
493 * is still asserted, setting TXDP will have no effect.
495 HALASSERT((ioread32_mac(AR_Q_TXE) & (1 << q)) == 0);
497 iowrite32_mac(AR_QTXDP(q), txdp);
502 HAL_BOOL ar5416StartTxDma(struct ath_hal *ah, a_uint32_t q)
504 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
505 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
507 /* Check to be sure we're not enabling a q that has its TXD bit set. */
508 HALASSERT((ioread32_mac(AR_Q_TXD) & (1 << q)) == 0);
510 iowrite32_mac(AR_Q_TXE, 1 << q);
515 a_uint32_t ar5416NumTxPending(struct ath_hal *ah, a_uint32_t q)
519 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
520 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
522 npend = ioread32_mac(AR_QSTS(q))
523 & AR_Q_STS_PEND_FR_CNT;
526 * Pending frame count (PFC) can momentarily go to zero
527 * while TXE remains asserted. In other words a PFC of
528 * zero is not sufficient to say that the queue has stopped.
530 if (ioread32_mac(AR_Q_TXE) & (1 << q))
534 if (npend && (AH5416(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) {
535 if (ioread32_mac(AR_Q_RDYTIMESHDN)
537 isrPrintf("RTSD on CAB queue\n");
538 /* Clear the ReadyTime shutdown status bits */
539 iowrite32_mac(AR_Q_RDYTIMESHDN, 1 << q);
546 HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah)
551 * set txd on all queues
553 iowrite32_mac(AR_Q_TXD, AR_Q_TXD_M);
558 OS_REG_SET_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF));
559 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
560 OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
563 * wait on all tx queues
565 for (q = 0; q < AR_NUM_QCU; q++) {
566 for (i = 0; i < AR5416_ABORT_LOOPS; i++) {
567 if (!ar5416NumTxPending(ah, q))
570 OS_DELAY(AR5416_ABORT_WAIT);
572 if (i == AR5416_ABORT_LOOPS) {
578 * clear tx abort bits
580 OS_REG_CLR_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF));
581 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
582 OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
587 iowrite32_mac(AR_Q_TXD, 0);
592 HAL_BOOL ar5416StopTxDma(struct ath_hal*ah, a_uint32_t q)
596 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
598 HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
600 iowrite32_mac(AR_Q_TXD, 1 << q);
601 for (i = 1000; i != 0; i--) {
602 if (ar5416NumTxPending(ah, q) == 0)
604 OS_DELAY(100); /* XXX get actual value */
607 iowrite32_mac(AR_Q_TXD, 0);
611 HAL_BOOL ar5416SetupTxDesc_20(struct ath_tx_desc *ds,
616 a_uint32_t txRate0, a_uint32_t txTries0,
619 a_uint32_t rtsctsRate,
620 a_uint32_t rtsctsDuration)
622 #define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
624 struct ar5416_desc *ads = AR5416DESC(ds);
628 ads->ds_txstatus9 &= ~AR_TxDone;
630 HALASSERT(txTries0 != 0);
631 HALASSERT(isValidPktType(type));
632 HALASSERT(isValidTxRate(txRate0));
633 HALASSERT((flags & RTSCTS) != RTSCTS);
638 ads->ds_ctl0 = (pktLen & AR_FrameLen)
639 | (txPower << AR_XmitPower_S)
640 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
641 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
642 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0);
644 ads->ds_ctl1 = (type << AR_FrameType_S)
645 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0);
646 ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0);
647 ads->ds_ctl3 = (txRate0 << AR_XmitRate0_S);
649 ads->ds_ctl7 = SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel0)
650 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel1)
651 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel2)
652 | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel3);
654 if (keyIx != HAL_TXKEYIX_INVALID) {
655 /* XXX validate key index */
656 ads->ds_ctl1 |= SM(keyIx, AR_DestIdx);
657 ads->ds_ctl0 |= AR_DestIdxValid;
660 if (flags & RTSCTS) {
661 if (!isValidTxRate(rtsctsRate)) {
664 /* XXX validate rtsctsDuration */
665 ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0)
666 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0);
667 ads->ds_ctl2 |= SM(rtsctsDuration, AR_BurstDur);
668 ads->ds_ctl3 |= (rtsctsRate << AR_RTSCTSRate_S);
675 HAL_BOOL ar5416FillTxDesc_20(struct ath_tx_desc *ds,
676 a_uint32_t segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
677 const struct ath_tx_desc *ds0)
679 struct ar5416_desc *ads = AR5416DESC(ds);
681 HALASSERT((segLen &~ AR_BufLen) == 0);
685 * First descriptor, don't clobber xmit control data
686 * setup by ar5416SetupTxDesc.
688 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
689 } else if (lastSeg) {
691 * Last descriptor in a multi-descriptor frame,
692 * copy the multi-rate transmit parameters from
693 * the first frame for processing on completion.
696 ads->ds_ctl1 = segLen;
697 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
698 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
701 * Intermediate descriptor in a multi-descriptor frame.
704 ads->ds_ctl1 = segLen | AR_TxMore;
708 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
713 HAL_BOOL ar5416FillKeyTxDesc_20(struct ath_tx_desc *ds,
714 HAL_KEY_TYPE keyType)
716 struct ar5416_desc *ads = AR5416DESC(ds);
718 ads->ds_ctl6 = SM(keyType, AR_EncrType);
722 HAL_STATUS ar5416ProcTxDesc_20(struct ath_hal *ah, struct ath_tx_desc *gds)
724 struct ar5416_desc *ads = AR5416DESC(gds);
725 struct ath_tx_desc *ds = (struct ath_tx_desc *)gds;
727 if ((ads->ds_txstatus9 & AR_TxDone) == 0)
728 return HAL_EINPROGRESS;
730 ads->ds_txstatus9 &= ~AR_TxDone;
732 /* Update software copies of the HW status */
733 ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
734 ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp;
735 ds->ds_txstat.ts_status = 0;
736 ds->ds_txstat.ts_flags = 0;
738 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
739 ds->ds_txstat.ts_status |= HAL_TXERR_XRETRY;
740 if (ads->ds_txstatus1 & AR_Filtered)
741 ds->ds_txstat.ts_status |= HAL_TXERR_FILT;
742 if (ads->ds_txstatus1 & AR_FIFOUnderrun)
743 ds->ds_txstat.ts_status |= HAL_TXERR_FIFO;
744 if (ads->ds_txstatus9 & AR_TxOpExceeded)
745 ds->ds_txstat.ts_status |= HAL_TXERR_XTXOP;
746 if (ads->ds_txstatus1 & AR_TxTimerExpired)
747 ds->ds_txstat.ts_status |= HAL_TXERR_TIMER_EXPIRED;
749 if (ads->ds_txstatus1 & AR_DescCfgErr)
750 ds->ds_txstat.ts_flags |= HAL_TX_DESC_CFG_ERR;
751 if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
752 ds->ds_txstat.ts_flags |= HAL_TX_DATA_UNDERRUN;
753 ar5416UpdateTxTrigLevel(ah, AH_TRUE);
755 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
756 ds->ds_txstat.ts_flags |= HAL_TX_DELIM_UNDERRUN;
757 ar5416UpdateTxTrigLevel(ah, AH_TRUE);
759 if (ads->ds_txstatus0 & AR_TxBaStatus) {
760 ds->ds_txstat.ts_flags |= HAL_TX_BA;
761 ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
762 ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
766 * Extract the transmit rate used and mark the rate as
767 * ``alternate'' if it wasn't the series 0 rate.
769 ds->ds_txstat.ts_rate = MS(ads->ds_txstatus9, AR_FinalTxIdx);
770 ds->ds_txstat.ts_rssi_combined =
771 MS(ads->ds_txstatus5, AR_TxRSSICombined);
772 ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
773 ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
774 ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
775 ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
776 ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
777 ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
778 ds->ds_txstat.evm0 = ads->AR_TxEVM0;
779 ds->ds_txstat.evm1 = ads->AR_TxEVM1;
780 ds->ds_txstat.evm2 = ads->AR_TxEVM2;
781 ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
782 ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
783 ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
784 ds->ds_txstat.ts_antenna = 0; /* ignored for owl */
789 void ar5416Set11nTxDesc_20(struct ath_tx_desc *ds,
790 a_uint32_t pktLen, HAL_PKT_TYPE type, a_uint32_t txPower,
791 a_uint32_t keyIx, HAL_KEY_TYPE keyType,
794 struct ar5416_desc *ads = AR5416DESC(ds);
796 HALASSERT(isValidPktType(type));
797 HALASSERT(isValidKeyType(keyType));
802 ads->ds_ctl0 = (pktLen & AR_FrameLen)
803 | (flags & HAL_TXDESC_VMF ? AR_VirtMoreFrag : 0)
804 | SM(txPower, AR_XmitPower)
805 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0)
806 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
807 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
808 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0)
809 | (keyIx != HAL_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
810 | (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0);
812 ads->ds_ctl1 = (keyIx != HAL_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
813 | SM(type, AR_FrameType)
814 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0)
815 | (flags & HAL_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
816 | (flags & HAL_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
818 ads->ds_ctl6 = SM(keyType, AR_EncrType);
821 void ar5416Set11nRateScenario_20(struct ath_tx_desc *ds,
822 a_uint32_t durUpdateEn, a_uint32_t rtsctsRate,
823 HAL_11N_RATE_SERIES series[], a_uint32_t nseries,
826 struct ar5416_desc *ads = AR5416DESC(ds);
829 HALASSERT(nseries == 4);
833 * Rate control settings override
835 ds_ctl0 = ads->ds_ctl0;
837 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
838 if (flags & HAL_TXDESC_RTSENA) {
839 ds_ctl0 &= ~AR_CTSEnable;
840 ds_ctl0 |= AR_RTSEnable;
842 ds_ctl0 &= ~AR_RTSEnable;
843 ds_ctl0 |= AR_CTSEnable;
846 /* this line is only difference between merlin and k2
847 * Current one is for merlin */
848 ds_ctl0 = (ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
851 ads->ds_ctl0 = ds_ctl0;
853 ads->ds_ctl2 = set11nTries(series, 0)
854 | set11nTries(series, 1)
855 | set11nTries(series, 2)
856 | set11nTries(series, 3)
857 | (durUpdateEn ? AR_DurUpdateEn : 0);
859 ads->ds_ctl3 = set11nRate(series, 0)
860 | set11nRate(series, 1)
861 | set11nRate(series, 2)
862 | set11nRate(series, 3);
864 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
865 | set11nPktDurRTSCTS(series, 1);
867 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
868 | set11nPktDurRTSCTS(series, 3);
870 ads->ds_ctl7 = set11nRateFlags(series, 0)
871 | set11nRateFlags(series, 1)
872 | set11nRateFlags(series, 2)
873 | set11nRateFlags(series, 3)
874 | SM(rtsctsRate, AR_RTSCTSRate);
877 void ar5416Set11nAggrFirst_20(struct ath_tx_desc *ds, a_uint32_t aggrLen,
878 a_uint32_t numDelims)
880 struct ar5416_desc *ads = AR5416DESC(ds);
882 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
884 ads->ds_ctl6 &= ~(AR_AggrLen | AR_PadDelim);
885 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen) |
886 SM(numDelims, AR_PadDelim);
889 void ar5416Set11nAggrMiddle_20(struct ath_tx_desc *ds, a_uint32_t numDelims)
891 struct ar5416_desc *ads = AR5416DESC(ds);
894 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
897 * We use a stack variable to manipulate ctl6 to reduce uncached
898 * read modify, modfiy, write.
901 ctl6 &= ~AR_PadDelim;
902 ctl6 |= SM(numDelims, AR_PadDelim);
906 void ar5416Set11nAggrLast_20(struct ath_tx_desc *ds)
908 struct ar5416_desc *ads = AR5416DESC(ds);
910 ads->ds_ctl1 |= AR_IsAggr;
911 ads->ds_ctl1 &= ~AR_MoreAggr;
912 ads->ds_ctl6 &= ~AR_PadDelim;
915 void ar5416Clr11nAggr_20(struct ath_tx_desc *ds)
917 struct ar5416_desc *ads = AR5416DESC(ds);
919 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
922 void ar5416Set11nBurstDuration_20(struct ath_tx_desc *ds,
923 a_uint32_t burstDuration)
925 struct ar5416_desc *ads = AR5416DESC(ds);
927 ads->ds_ctl2 &= ~AR_BurstDur;
928 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
931 void ar5416Set11nVirtualMoreFrag_20(struct ath_tx_desc *ds,
934 struct ar5416_desc *ads = AR5416DESC(ds);
937 ads->ds_ctl0 |= AR_VirtMoreFrag;
939 ads->ds_ctl0 &= ~AR_VirtMoreFrag;