2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2005 Atheros Communications, Inc.
6 * $Id: //depot/sw/branches/fusion_usb/target_firmware/wlan/target/hal/main/ah_internal.h#2 $
8 #ifndef _ATH_AH_INTERAL_H_
9 #define _ATH_AH_INTERAL_H_
13 #define IEEE80211_AMPDU_LIMIT_MAX (64 * 1024 - 1)
16 #define AH_MIN(a,b) ((a)<(b)?(a):(b))
17 #define AH_MAX(a,b) ((a)>(b)?(a):(b))
20 * Common assertion interface. Note: it is a bad idea to generate
21 * an assertion failure for any recoverable event. Instead catch
22 * the violation and, if possible, fix it up or recover from it; either
23 * with an error return value or a diagnostic messages. System software
24 * does not panic unless the situation is hopeless.
27 #define HALASSERT(_x) do { \
32 #endif /* AH_ASSERT */
35 #define NBBY 8 /* number of bits/byte */
38 #define IEEE80211_ADDR_LEN 6
41 * Internal form of a HAL_CHANNEL. Note that the structure
42 * must be defined such that you can cast references to a
43 * HAL_CHANNEL so don't shuffle the first two members.
46 a_uint16_t channel; /* NB: must be first for casting */
47 a_uint32_t channelFlags;
51 int8_t minTxPower; /* as above... */
52 a_uint8_t regClassId; /* Regulatory class id */
56 HAL_BOOL oneTimeCalsDone;
59 a_int16_t rawNoiseFloor;
60 a_int16_t finalNoiseFloor;
62 a_uint32_t regDmnFlags; /* Flags for channel use in reg */
63 a_uint32_t conformanceTestLimit; /* conformance test limit from reg domain */
64 a_uint16_t mainSpur; /* cached spur value for this cahnnel */
65 u_int64_t ah_tsf_last; /* tsf @ which time accured is computed */
66 u_int64_t ah_channel_time; /* time on the channel */
67 u_int64_t dfsTsf; /* Tsf when channel leaves NOL */
68 } HAL_CHANNEL_INTERNAL;
71 a_uint32_t halChanSpreadSupport : 1,
72 halSleepAfterBeaconBroken : 1,
73 halCompressSupport : 1,
75 halFastFramesSupport : 1,
76 halChapTuningSupport : 1,
78 halTurboPrimeSupport : 1,
80 halMicAesCcmSupport : 1,
81 halMicCkipSupport : 1,
82 halMicTkipSupport : 1,
83 halCipherAesCcmSupport : 1,
84 halCipherCkipSupport : 1,
85 halCipherTkipSupport : 1,
88 halBssIdMaskSupport : 1,
89 halMcastKeySrchSupport : 1,
92 halChanQuarterRate : 1,
98 halExtChanDfsSupport : 1,
99 halUseCombinedRadarRssi : 1,
101 halRifsRxSupport : 1,
102 halRifsTxSupport : 1,
104 halforcePpmSupport : 1,
105 halAutoSleepSupport : 1,
106 hal4kbSplitTransSupport : 1,
107 halEnhancedPmSupport : 1,
108 halMbssidAggrSupport : 1,
109 halTkipWepHtRateSupport : 1,
111 halRfSilentSupport : 1;
112 a_uint32_t halWirelessModes;
113 a_uint16_t halTotalQueues;
114 a_uint16_t halKeyCacheSize;
115 a_uint16_t halLow5GhzChan, halHigh5GhzChan;
116 a_uint16_t halLow2GhzChan, halHigh2GhzChan;
117 a_uint16_t halNumMRRetries;
118 a_uint8_t halTxChainMask;
119 a_uint8_t halRxChainMask;
120 a_uint16_t halRtsAggrLimit;
121 a_uint16_t halJapanRegCap;
122 a_uint8_t halNumGpioPins;
126 #if !defined(_NET_IF_IEEE80211_H_) && !defined(_NET80211__IEEE80211_H_)
128 * Stuff that would naturally come from _ieee80211.h
130 #define IEEE80211_ADDR_LEN 6
131 #define IEEE80211_WEP_KEYLEN 5 /* 40bit */
132 #define IEEE80211_WEP_IVLEN 3 /* 24bit */
133 #define IEEE80211_WEP_KIDLEN 1 /* 1 octet */
134 #define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */
135 #define IEEE80211_CRC_LEN 4
136 #define IEEE80211_MTU 1500
137 #define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \
138 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN))
140 #define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */
143 IEEE80211_T_DS, /* direct sequence spread spectrum */
144 IEEE80211_T_FH, /* frequency hopping */
145 IEEE80211_T_OFDM, /* frequency division multiplexing */
146 IEEE80211_T_TURBO, /* high rate DS */
147 IEEE80211_T_HT, /* HT - full GI */
150 #define IEEE80211_T_CCK IEEE80211_T_DS /* more common nomenclatur */
151 #endif /* _NET_IF_IEEE80211_H_ */
153 /* NB: these are defined privately until XR support is announced */
155 ATHEROS_T_XR = IEEE80211_T_MAX, /* extended range */
158 struct ath_hal_private {
161 a_uint32_t ah_macVersion;
162 a_uint16_t ah_macRev;
163 a_uint16_t ah_phyRev;
165 HAL_CAPABILITIES ah_caps; /* device capabilities */
166 HAL_CHANNEL_INTERNAL *ah_curchan; /* current channel */
169 #define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah))
171 #define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \
172 (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20))
173 #define IS_CHAN_B(_c) (((_c)->channelFlags & CHANNEL_B) == CHANNEL_B)
174 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_108G|CHANNEL_G)) == CHANNEL_G) || \
175 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20))
176 #define IS_CHAN_108G(_c)(((_c)->channelFlags & CHANNEL_108G) == CHANNEL_108G)
177 #define IS_CHAN_T(_c) (((_c)->channelFlags & CHANNEL_T) == CHANNEL_T)
178 #define IS_CHAN_X(_c) (((_c)->channelFlags & CHANNEL_X) == CHANNEL_X)
179 #define IS_CHAN_PUREG(_c) \
180 (((_c)->channelFlags & CHANNEL_PUREG) == CHANNEL_PUREG)
181 #define IS_CHAN_NA(_c) (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20)
182 #define IS_CHAN_NG(_c) (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20)
184 #define IS_CHAN_TURBO(_c) (((_c)->channelFlags & CHANNEL_TURBO) != 0)
185 #define IS_CHAN_CCK(_c) (((_c)->channelFlags & CHANNEL_CCK) != 0)
186 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
187 #define IS_CHAN_XR(_c) (((_c)->channelFlags & CHANNEL_XR) != 0)
188 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
189 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
190 #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
191 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
192 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
193 #define IS_CHAN_HT(_c) (((_c)->channelFlags & CHANNEL_HT20) != 0)
194 #define IS_CHAN_HT20(_c) (((_c)->channelFlags & CHANNEL_HT20) != 0)
195 #define IS_CHAN_HT40(_c) (((_c)->channelFlags & CHANNEL_HT40) != 0)
197 #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
200 * Register manipulation macros that expect bit field defines
201 * to follow the convention that an _S suffix is appended for
202 * a shift count, while the field mask has no suffix.
204 #define SM(_v, _f) (((_v) << _f##_S) & _f)
205 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
206 #define OS_REG_RMW_FIELD(_a, _r, _f, _v) \
207 OS_REG_WRITE(_a, _r, \
208 (OS_REG_READ(_a, _r) &~ _f) | (((_v) << _f##_S) & _f))
209 #define OS_REG_RMW(_a, _r, _set, _clr) \
210 OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set))
211 #define OS_REG_SET_BIT(_a, _r, _f) \
212 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | _f)
213 #define OS_REG_CLR_BIT(_a, _r, _f) \
214 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ _f)
217 /* wait for the register contents to have the specified value */
218 extern HAL_BOOL ath_hal_wait(struct ath_hal *, a_uint32_t reg,
219 a_uint32_t mask, a_uint32_t val);
221 extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list);
223 /* allocate and free memory */
224 extern void *ath_hal_malloc(size_t);
225 extern void ath_hal_free(void *);
228 * Generic get/set capability support. Each chip overrides
229 * this routine to support chip-specific capabilities.
231 extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah,
232 HAL_CAPABILITY_TYPE type, a_uint32_t capability,
234 extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah,
235 HAL_CAPABILITY_TYPE type, a_uint32_t capability,
236 a_uint32_t setting, HAL_STATUS *status);
238 #endif /* _ATH_AH_INTERAL_H_ */